Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T37
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T14
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T37
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T14
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T37
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T37
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T14
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11658812	13026	0	0
gen_assertions[0].RstEnOn_A	11658812	1141	0	0
gen_assertions[0].RstNOff_A	11658812	13026	0	0
gen_assertions[0].RstNOn_A	11658812	1141	0	0
gen_assertions[1].RstEnOff_A	46634603	11838	0	0
gen_assertions[1].RstEnOn_A	46634603	1083	0	0
gen_assertions[1].RstNOff_A	46634603	11838	0	0
gen_assertions[1].RstNOn_A	46634603	1083	0	0
gen_assertions[2].RstEnOff_A	23318350	11923	0	0
gen_assertions[2].RstEnOn_A	23318350	1098	0	0
gen_assertions[2].RstNOff_A	23318350	11923	0	0
gen_assertions[2].RstNOn_A	23318350	1098	0	0
gen_assertions[3].RstEnOff_A	23318412	11964	0	0
gen_assertions[3].RstEnOn_A	23318412	1131	0	0
gen_assertions[3].RstNOff_A	23318412	11964	0	0
gen_assertions[3].RstNOn_A	23318412	1131	0	0
gen_assertions[4].RstEnOff_A	1472054	19800	0	0
gen_assertions[4].RstEnOn_A	1472054	1167	0	0
gen_assertions[4].RstNOff_A	1472054	19800	0	0
gen_assertions[4].RstNOn_A	1472054	1167	0	0
gen_assertions[5].RstEnOff_A	11658812	13224	0	0
gen_assertions[5].RstEnOn_A	11658812	1196	0	0
gen_assertions[5].RstNOff_A	11658812	13224	0	0
gen_assertions[5].RstNOn_A	11658812	1196	0	0
gen_assertions[6].RstEnOff_A	11658812	13303	0	0
gen_assertions[6].RstEnOn_A	11658812	1284	0	0
gen_assertions[6].RstNOff_A	11658812	13303	0	0
gen_assertions[6].RstNOn_A	11658812	1284	0	0
gen_assertions[7].RstEnOff_A	11658812	13375	0	0
gen_assertions[7].RstEnOn_A	11658812	1360	0	0
gen_assertions[7].RstNOff_A	11658812	13375	0	0
gen_assertions[7].RstNOn_A	11658812	1360	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13026	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	5	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	6	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	112	0	0
T23	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1141	0	0
T2	4038	2	0	0
T3	2060	0	0	0
T4	3630	0	0	0
T5	2048	0	0	0
T6	4673	1	0	0
T7	7194	0	0	0
T8	2772	0	0	0
T9	7198	0	0	0
T10	9077	6	0	0
T11	31718	0	0	0
T14	0	13	0	0
T37	0	6	0	0
T56	0	1	0	0
T57	0	6	0	0
T72	0	8	0	0
T76	0	1	0	0
T77	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13026	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	5	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	6	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	112	0	0
T23	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1141	0	0
T2	4038	2	0	0
T3	2060	0	0	0
T4	3630	0	0	0
T5	2048	0	0	0
T6	4673	1	0	0
T7	7194	0	0	0
T8	2772	0	0	0
T9	7198	0	0	0
T10	9077	6	0	0
T11	31718	0	0	0
T14	0	13	0	0
T37	0	6	0	0
T56	0	1	0	0
T57	0	6	0	0
T72	0	8	0	0
T76	0	1	0	0
T77	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46634603	11838	0	0
T2	16156	8	0	0
T3	8244	0	0	0
T4	14523	4	0	0
T5	8201	0	0	0
T6	18698	4	0	0
T7	28802	0	0	0
T8	11097	3	0	0
T9	28794	0	0	0
T10	36313	9	0	0
T11	126876	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	106	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46634603	1083	0	0
T10	36313	9	0	0
T11	126876	0	0	0
T12	121300	0	0	0
T13	187423	0	0	0
T14	242696	14	0	0
T23	10745	0	0	0
T24	16940	0	0	0
T33	6236	0	0	0
T34	29185	0	0	0
T35	808113	0	0	0
T37	0	8	0	0
T56	0	1	0	0
T57	0	5	0	0
T59	0	2	0	0
T72	0	4	0	0
T77	0	1	0	0
T78	0	6	0	0
T79	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46634603	11838	0	0
T2	16156	8	0	0
T3	8244	0	0	0
T4	14523	4	0	0
T5	8201	0	0	0
T6	18698	4	0	0
T7	28802	0	0	0
T8	11097	3	0	0
T9	28794	0	0	0
T10	36313	9	0	0
T11	126876	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	106	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46634603	1083	0	0
T10	36313	9	0	0
T11	126876	0	0	0
T12	121300	0	0	0
T13	187423	0	0	0
T14	242696	14	0	0
T23	10745	0	0	0
T24	16940	0	0	0
T33	6236	0	0	0
T34	29185	0	0	0
T35	808113	0	0	0
T37	0	8	0	0
T56	0	1	0	0
T57	0	5	0	0
T59	0	2	0	0
T72	0	4	0	0
T77	0	1	0	0
T78	0	6	0	0
T79	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318350	11923	0	0
T2	8077	8	0	0
T3	4121	0	0	0
T4	7264	4	0	0
T5	4100	0	0	0
T6	9349	4	0	0
T7	14398	0	0	0
T8	5545	4	0	0
T9	14398	0	0	0
T10	18157	10	0	0
T11	63442	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	105	0	0
T23	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318350	1098	0	0
T8	5545	1	0	0
T9	14398	0	0	0
T10	18157	10	0	0
T11	63442	0	0	0
T12	60679	0	0	0
T13	93731	0	0	0
T14	121321	13	0	0
T23	5373	0	0	0
T33	3118	0	0	0
T34	14595	0	0	0
T37	0	8	0	0
T56	0	1	0	0
T59	0	3	0	0
T72	0	7	0	0
T78	0	11	0	0
T79	0	6	0	0
T80	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318350	11923	0	0
T2	8077	8	0	0
T3	4121	0	0	0
T4	7264	4	0	0
T5	4100	0	0	0
T6	9349	4	0	0
T7	14398	0	0	0
T8	5545	4	0	0
T9	14398	0	0	0
T10	18157	10	0	0
T11	63442	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	105	0	0
T23	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318350	1098	0	0
T8	5545	1	0	0
T9	14398	0	0	0
T10	18157	10	0	0
T11	63442	0	0	0
T12	60679	0	0	0
T13	93731	0	0	0
T14	121321	13	0	0
T23	5373	0	0	0
T33	3118	0	0	0
T34	14595	0	0	0
T37	0	8	0	0
T56	0	1	0	0
T59	0	3	0	0
T72	0	7	0	0
T78	0	11	0	0
T79	0	6	0	0
T80	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318412	11964	0	0
T2	8078	8	0	0
T3	4121	0	0	0
T4	7264	4	0	0
T5	4100	0	0	0
T6	9352	4	0	0
T7	14392	0	0	0
T8	5546	3	0	0
T9	14397	0	0	0
T10	18157	11	0	0
T11	63433	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	106	0	0
T23	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318412	1131	0	0
T10	18157	11	0	0
T11	63433	0	0	0
T12	60668	0	0	0
T13	93734	0	0	0
T14	121333	14	0	0
T23	5377	0	0	0
T24	8470	0	0	0
T33	3118	0	0	0
T34	14599	0	0	0
T35	404103	0	0	0
T37	0	12	0	0
T59	0	4	0	0
T72	0	8	0	0
T78	0	9	0	0
T79	0	6	0	0
T81	0	7	0	0
T82	0	1	0	0
T83	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318412	11964	0	0
T2	8078	8	0	0
T3	4121	0	0	0
T4	7264	4	0	0
T5	4100	0	0	0
T6	9352	4	0	0
T7	14392	0	0	0
T8	5546	3	0	0
T9	14397	0	0	0
T10	18157	11	0	0
T11	63433	32	0	0
T12	0	65	0	0
T13	0	73	0	0
T14	0	106	0	0
T23	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23318412	1131	0	0
T10	18157	11	0	0
T11	63433	0	0	0
T12	60668	0	0	0
T13	93734	0	0	0
T14	121333	14	0	0
T23	5377	0	0	0
T24	8470	0	0	0
T33	3118	0	0	0
T34	14599	0	0	0
T35	404103	0	0	0
T37	0	12	0	0
T59	0	4	0	0
T72	0	8	0	0
T78	0	9	0	0
T79	0	6	0	0
T81	0	7	0	0
T82	0	1	0	0
T83	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1472054	19800	0	0
T1	318	2	0	0
T2	504	10	0	0
T3	256	1	0	0
T4	452	6	0	0
T5	255	2	0	0
T6	583	6	0	0
T7	903	3	0	0
T8	346	7	0	0
T9	902	2	0	0
T10	1133	13	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1472054	1167	0	0
T8	346	1	0	0
T9	902	0	0	0
T10	1133	12	0	0
T11	4005	0	0	0
T12	3806	0	0	0
T13	5873	0	0	0
T14	7778	11	0	0
T23	335	0	0	0
T33	194	0	0	0
T34	915	0	0	0
T37	0	13	0	0
T59	0	5	0	0
T72	0	7	0	0
T78	0	12	0	0
T79	0	6	0	0
T81	0	8	0	0
T82	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1472054	19800	0	0
T1	318	2	0	0
T2	504	10	0	0
T3	256	1	0	0
T4	452	6	0	0
T5	255	2	0	0
T6	583	6	0	0
T7	903	3	0	0
T8	346	7	0	0
T9	902	2	0	0
T10	1133	13	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1472054	1167	0	0
T8	346	1	0	0
T9	902	0	0	0
T10	1133	12	0	0
T11	4005	0	0	0
T12	3806	0	0	0
T13	5873	0	0	0
T14	7778	11	0	0
T23	335	0	0	0
T33	194	0	0	0
T34	915	0	0	0
T37	0	13	0	0
T59	0	5	0	0
T72	0	7	0	0
T78	0	12	0	0
T79	0	6	0	0
T81	0	8	0	0
T82	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13224	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	111	0	0
T23	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1196	0	0
T10	9077	14	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	12	0	0
T23	2687	0	0	0
T24	4234	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T35	202055	0	0	0
T37	0	13	0	0
T56	0	1	0	0
T59	0	6	0	0
T72	0	6	0	0
T78	0	12	0	0
T79	0	9	0	0
T81	0	9	0	0
T83	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13224	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	111	0	0
T23	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1196	0	0
T10	9077	14	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	12	0	0
T23	2687	0	0	0
T24	4234	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T35	202055	0	0	0
T37	0	13	0	0
T56	0	1	0	0
T59	0	6	0	0
T72	0	6	0	0
T78	0	12	0	0
T79	0	9	0	0
T81	0	9	0	0
T83	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13303	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	12	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	113	0	0
T23	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1284	0	0
T10	9077	12	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	15	0	0
T23	2687	0	0	0
T24	4234	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T35	202055	0	0	0
T37	0	13	0	0
T59	0	7	0	0
T72	0	7	0	0
T78	0	12	0	0
T79	0	9	0	0
T81	0	11	0	0
T83	0	13	0	0
T84	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13303	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	4	0	0
T9	7198	0	0	0
T10	9077	12	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	113	0	0
T23	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1284	0	0
T10	9077	12	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	15	0	0
T23	2687	0	0	0
T24	4234	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T35	202055	0	0	0
T37	0	13	0	0
T59	0	7	0	0
T72	0	7	0	0
T78	0	12	0	0
T79	0	9	0	0
T81	0	11	0	0
T83	0	13	0	0
T84	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13375	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	5	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	113	0	0
T23	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1360	0	0
T8	2772	1	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	15	0	0
T23	2687	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T37	0	16	0	0
T59	0	7	0	0
T72	0	4	0	0
T78	0	15	0	0
T79	0	9	0	0
T85	0	1	0	0
T86	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	13375	0	0
T2	4038	9	0	0
T3	2060	0	0	0
T4	3630	4	0	0
T5	2048	0	0	0
T6	4673	4	0	0
T7	7194	0	0	0
T8	2772	5	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	33	0	0
T12	0	78	0	0
T13	0	78	0	0
T14	0	113	0	0
T23	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11658812	1360	0	0
T8	2772	1	0	0
T9	7198	0	0	0
T10	9077	14	0	0
T11	31718	0	0	0
T12	30339	0	0	0
T13	46861	0	0	0
T14	60666	15	0	0
T23	2687	0	0	0
T33	1558	0	0	0
T34	7296	0	0	0
T37	0	16	0	0
T59	0	7	0	0
T72	0	4	0	0
T78	0	15	0	0
T79	0	9	0	0
T85	0	1	0	0
T86	0	1	0	0