Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11127646	8437	0	0
alert_regwen_rd_A	11127646	4750	0	0
cpu_regwen_rd_A	11127646	4703	0	0
sw_rst_ctrl_n_0_rd_A	11127646	9969	0	0
sw_rst_ctrl_n_1_rd_A	11127646	9766	0	0
sw_rst_ctrl_n_2_rd_A	11127646	9740	0	0
sw_rst_ctrl_n_3_rd_A	11127646	9692	0	0
sw_rst_ctrl_n_4_rd_A	11127646	9598	0	0
sw_rst_ctrl_n_5_rd_A	11127646	9495	0	0
sw_rst_ctrl_n_6_rd_A	11127646	9576	0	0
sw_rst_ctrl_n_7_rd_A	11127646	9675	0	0
sw_rst_regwen_0_rd_A	11127646	5539	0	0
sw_rst_regwen_1_rd_A	11127646	5426	0	0
sw_rst_regwen_2_rd_A	11127646	5408	0	0
sw_rst_regwen_3_rd_A	11127646	5330	0	0
sw_rst_regwen_4_rd_A	11127646	5266	0	0
sw_rst_regwen_5_rd_A	11127646	5586	0	0
sw_rst_regwen_6_rd_A	11127646	5369	0	0
sw_rst_regwen_7_rd_A	11127646	5421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	8437	0	0
T60	7418	365	0	0
T61	27340	1	0	0
T63	2812	5	0	0
T66	7518	396	0	0
T68	13020	1	0	0
T87	13282	659	0	0
T88	4538	33	0	0
T90	3981	360	0	0
T91	2586	61	0	0
T92	2627	10	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	4750	0	0
T25	43493	0	0	0
T53	18614	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	54	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T76	2636	0	0	0
T96	0	29	0	0
T102	0	78	0	0
T103	0	72	0	0
T105	0	113	0	0
T106	0	54	0	0
T133	0	48	0	0
T134	0	75	0	0
T135	0	83	0	0
T136	0	75	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	4703	0	0
T25	43493	0	0	0
T53	18614	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	50	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T76	2636	0	0	0
T96	0	49	0	0
T102	0	70	0	0
T103	0	81	0	0
T105	0	155	0	0
T106	0	62	0	0
T133	0	23	0	0
T134	0	73	0	0
T135	0	88	0	0
T136	0	73	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9969	0	0
T2	3328	28	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	31	0	0
T36	0	11	0	0
T71	0	67	0	0
T73	0	7	0	0
T81	0	185	0	0
T83	0	128	0	0
T84	0	142	0	0
T96	0	38	0	0
T137	0	52	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9766	0	0
T2	3328	46	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	39	0	0
T36	0	13	0	0
T71	0	64	0	0
T73	0	11	0	0
T81	0	189	0	0
T83	0	127	0	0
T84	0	94	0	0
T96	0	27	0	0
T137	0	33	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9740	0	0
T2	3328	36	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	19	0	0
T36	0	23	0	0
T71	0	72	0	0
T73	0	12	0	0
T81	0	164	0	0
T83	0	120	0	0
T84	0	160	0	0
T96	0	17	0	0
T137	0	47	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9692	0	0
T2	3328	26	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	27	0	0
T36	0	15	0	0
T71	0	47	0	0
T73	0	17	0	0
T81	0	176	0	0
T83	0	149	0	0
T84	0	134	0	0
T96	0	18	0	0
T137	0	46	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9598	0	0
T2	3328	32	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	26	0	0
T36	0	18	0	0
T71	0	59	0	0
T73	0	6	0	0
T81	0	147	0	0
T83	0	124	0	0
T84	0	103	0	0
T96	0	35	0	0
T137	0	40	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9495	0	0
T2	3328	32	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	36	0	0
T36	0	15	0	0
T71	0	69	0	0
T73	0	14	0	0
T81	0	157	0	0
T83	0	113	0	0
T84	0	105	0	0
T96	0	36	0	0
T137	0	69	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9576	0	0
T2	3328	22	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	36	0	0
T36	0	6	0	0
T71	0	42	0	0
T73	0	12	0	0
T81	0	164	0	0
T83	0	136	0	0
T84	0	123	0	0
T96	0	21	0	0
T137	0	49	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	9675	0	0
T2	3328	41	0	0
T3	1994	0	0	0
T4	3537	0	0	0
T5	1959	0	0	0
T6	4530	0	0	0
T7	6275	0	0	0
T8	2628	0	0	0
T9	6755	0	0	0
T10	9059	0	0	0
T11	26742	0	0	0
T24	0	45	0	0
T36	0	8	0	0
T71	0	55	0	0
T73	0	8	0	0
T81	0	143	0	0
T83	0	115	0	0
T84	0	136	0	0
T96	0	23	0	0
T137	0	46	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5539	0	0
T36	6069	7	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	73	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	16	0	0
T83	0	29	0	0
T84	0	28	0	0
T96	0	24	0	0
T102	0	92	0	0
T103	0	89	0	0
T138	0	11	0	0
T139	0	9	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5426	0	0
T36	6069	6	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	63	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	27	0	0
T83	0	14	0	0
T84	0	36	0	0
T96	0	20	0	0
T102	0	86	0	0
T103	0	100	0	0
T138	0	24	0	0
T140	0	31	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5408	0	0
T36	6069	3	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	79	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	33	0	0
T83	0	21	0	0
T84	0	40	0	0
T96	0	14	0	0
T102	0	95	0	0
T103	0	90	0	0
T138	0	30	0	0
T140	0	27	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5330	0	0
T36	6069	8	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	71	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	31	0	0
T83	0	9	0	0
T84	0	28	0	0
T96	0	14	0	0
T102	0	64	0	0
T103	0	84	0	0
T138	0	14	0	0
T139	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5266	0	0
T36	6069	12	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	72	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	28	0	0
T83	0	26	0	0
T84	0	48	0	0
T96	0	35	0	0
T102	0	81	0	0
T103	0	96	0	0
T138	0	18	0	0
T139	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5586	0	0
T36	6069	12	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	56	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	25	0	0
T83	0	7	0	0
T84	0	30	0	0
T96	0	26	0	0
T102	0	93	0	0
T103	0	72	0	0
T138	0	12	0	0
T140	0	38	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5369	0	0
T36	6069	2	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	52	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	18	0	0
T83	0	20	0	0
T84	0	28	0	0
T96	0	26	0	0
T102	0	72	0	0
T103	0	75	0	0
T138	0	24	0	0
T140	0	34	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11127646	5421	0	0
T36	6069	4	0	0
T37	3590	0	0	0
T48	189205	0	0	0
T59	2641	0	0	0
T67	1770	0	0	0
T71	35716	58	0	0
T72	22857	0	0	0
T73	1844	0	0	0
T74	3384	0	0	0
T75	6996	0	0	0
T81	0	33	0	0
T83	0	17	0	0
T84	0	22	0	0
T96	0	24	0	0
T102	0	72	0	0
T103	0	69	0	0
T138	0	8	0	0
T139	0	5	0	0