Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	625828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

373593

1

T2

141

T3

75

T4

66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	533430	1			T1	1		T2	186		T3	99
values[0x0]	232073	1			T2	94		T3	53		T4	53
values[0x1]	233918	1			T2	99		T3	60		T4	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	525286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

474135

1

T1

1

T2

175

T3

88

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3911	1			T3	1		T10	1		T12	9
valid_sources[0x01]	4013	1			T2	1		T4	1		T9	1
valid_sources[0x02]	3891	1			T2	3		T4	1		T9	1
valid_sources[0x03]	3770	1			T2	2		T9	1		T10	3
valid_sources[0x04]	4055	1			T10	3		T11	1		T12	11
valid_sources[0x05]	3377	1			T2	1		T9	1		T10	3
valid_sources[0x06]	3196	1			T2	15		T6	1		T9	1
valid_sources[0x07]	3111	1			T2	1		T3	3		T10	1
valid_sources[0x08]	4571	1			T10	1		T12	6		T60	1
valid_sources[0x09]	3563	1			T2	5		T4	1		T9	1
valid_sources[0x0a]	3499	1			T3	1		T4	1		T6	8
valid_sources[0x0b]	3777	1			T2	7		T3	7		T10	1
valid_sources[0x0c]	3260	1			T2	1		T3	5		T10	1
valid_sources[0x0d]	7697	1			T2	2		T9	2		T10	2
valid_sources[0x0e]	3367	1			T2	6		T4	1		T12	14
valid_sources[0x0f]	3636	1			T2	1		T4	3		T11	1
valid_sources[0x10]	4923	1			T10	1		T12	13		T23	1
valid_sources[0x11]	3901	1			T2	3		T3	6		T4	1
valid_sources[0x12]	2821	1			T10	2		T11	1		T12	11
valid_sources[0x13]	3668	1			T10	2		T12	2		T24	3
valid_sources[0x14]	3139	1			T3	4		T9	1		T10	1
valid_sources[0x15]	4342	1			T4	1		T10	4		T12	8
valid_sources[0x16]	3516	1			T6	7		T9	4		T10	2
valid_sources[0x17]	3223	1			T2	5		T8	4		T10	2
valid_sources[0x18]	4543	1			T2	1		T4	1		T9	2
valid_sources[0x19]	3742	1			T2	1		T6	19		T11	1
valid_sources[0x1a]	3515	1			T2	7		T3	2		T4	2
valid_sources[0x1b]	4296	1			T2	1		T3	4		T9	1
valid_sources[0x1c]	3639	1			T4	1		T12	5		T60	2
valid_sources[0x1d]	3577	1			T1	1		T2	2		T3	2
valid_sources[0x1e]	3986	1			T4	1		T8	1		T10	2
valid_sources[0x1f]	4089	1			T2	1		T6	2		T10	2
valid_sources[0x20]	3303	1			T10	1		T11	2		T12	9
valid_sources[0x21]	3151	1			T10	4		T11	2		T12	8
valid_sources[0x22]	3522	1			T4	1		T12	7		T60	6
valid_sources[0x23]	3747	1			T2	1		T3	2		T10	3
valid_sources[0x24]	6906	1			T2	2		T3	1		T9	2
valid_sources[0x25]	3618	1			T2	3		T4	2		T10	1
valid_sources[0x26]	4306	1			T2	3		T4	1		T10	3
valid_sources[0x27]	3963	1			T3	2		T4	2		T10	3
valid_sources[0x28]	3353	1			T4	1		T10	1		T12	10
valid_sources[0x29]	6902	1			T2	2		T3	1		T4	1
valid_sources[0x2a]	6631	1			T2	5		T3	1		T4	1
valid_sources[0x2b]	4421	1			T2	2		T4	1		T11	2
valid_sources[0x2c]	3984	1			T4	2		T10	1		T11	1
valid_sources[0x2d]	4034	1			T2	1		T4	1		T12	11
valid_sources[0x2e]	4144	1			T2	1		T3	4		T9	4
valid_sources[0x2f]	3311	1			T4	1		T10	2		T11	1
valid_sources[0x30]	6725	1			T4	1		T10	1		T12	11
valid_sources[0x31]	4189	1			T2	1		T3	2		T10	2
valid_sources[0x32]	3697	1			T2	1		T4	1		T9	1
valid_sources[0x33]	3865	1			T4	2		T11	1		T12	10
valid_sources[0x34]	3344	1			T2	4		T3	8		T4	2
valid_sources[0x35]	4112	1			T2	8		T4	1		T10	3
valid_sources[0x36]	3593	1			T4	1		T10	1		T11	1
valid_sources[0x37]	3503	1			T9	4		T10	5		T12	11
valid_sources[0x38]	2918	1			T10	1		T12	13		T60	8
valid_sources[0x39]	4086	1			T2	1		T3	1		T6	25
valid_sources[0x3a]	3283	1			T2	1		T3	2		T4	1
valid_sources[0x3b]	6328	1			T2	4		T11	3		T12	7
valid_sources[0x3c]	3262	1			T2	3		T3	1		T4	2
valid_sources[0x3d]	4019	1			T2	1		T11	2		T12	9
valid_sources[0x3e]	3347	1			T3	3		T10	1		T11	2
valid_sources[0x3f]	5386	1			T2	1		T10	3		T11	2
valid_sources[0x40]	3465	1			T10	2		T11	1		T12	5
valid_sources[0x41]	4187	1			T4	1		T10	2		T11	4
valid_sources[0x42]	3204	1			T10	2		T11	1		T12	11
valid_sources[0x43]	4921	1			T2	12		T3	1		T10	1
valid_sources[0x44]	3469	1			T2	3		T10	2		T11	1
valid_sources[0x45]	3798	1			T10	1		T12	5		T13	15
valid_sources[0x46]	3279	1			T2	3		T4	2		T6	22
valid_sources[0x47]	3711	1			T2	1		T4	1		T12	8
valid_sources[0x48]	3329	1			T2	6		T10	1		T11	1
valid_sources[0x49]	3894	1			T2	2		T3	3		T4	1
valid_sources[0x4a]	4136	1			T4	1		T10	1		T12	3
valid_sources[0x4b]	3375	1			T2	1		T3	3		T4	2
valid_sources[0x4c]	4031	1			T6	2		T10	1		T12	9
valid_sources[0x4d]	3629	1			T2	1		T4	1		T11	1
valid_sources[0x4e]	2842	1			T4	1		T9	1		T11	3
valid_sources[0x4f]	3399	1			T9	3		T10	1		T12	12
valid_sources[0x50]	3233	1			T2	3		T12	5		T60	3
valid_sources[0x51]	3450	1			T4	1		T11	6		T12	7
valid_sources[0x52]	3804	1			T2	4		T3	2		T4	1
valid_sources[0x53]	3554	1			T3	5		T6	75		T10	1
valid_sources[0x54]	3293	1			T2	7		T9	1		T10	1
valid_sources[0x55]	3231	1			T2	4		T3	1		T10	2
valid_sources[0x56]	4332	1			T4	1		T9	4		T10	4
valid_sources[0x57]	3989	1			T10	3		T11	1		T12	5
valid_sources[0x58]	3720	1			T6	27		T9	1		T12	21
valid_sources[0x59]	3932	1			T4	1		T10	1		T11	3
valid_sources[0x5a]	3777	1			T3	1		T4	1		T10	2
valid_sources[0x5b]	4483	1			T3	4		T6	17		T9	1
valid_sources[0x5c]	3701	1			T2	6		T3	4		T11	1
valid_sources[0x5d]	3324	1			T10	1		T12	5		T60	4
valid_sources[0x5e]	3581	1			T3	4		T10	1		T11	3
valid_sources[0x5f]	3810	1			T10	2		T12	12		T60	4
valid_sources[0x60]	6826	1			T2	2		T4	1		T9	1
valid_sources[0x61]	3155	1			T2	3		T9	2		T12	9
valid_sources[0x62]	3048	1			T2	1		T3	3		T4	3
valid_sources[0x63]	4544	1			T6	4		T10	2		T11	1
valid_sources[0x64]	3325	1			T2	5		T10	1		T11	1
valid_sources[0x65]	9873	1			T2	3		T4	1		T10	3
valid_sources[0x66]	3580	1			T2	3		T8	3		T9	4
valid_sources[0x67]	3419	1			T3	4		T10	2		T12	12
valid_sources[0x68]	3638	1			T3	1		T6	5		T11	1
valid_sources[0x69]	3222	1			T3	5		T9	1		T10	1
valid_sources[0x6a]	3315	1			T2	1		T4	1		T10	3
valid_sources[0x6b]	3730	1			T2	6		T4	1		T10	1
valid_sources[0x6c]	5657	1			T10	3		T11	1		T12	8
valid_sources[0x6d]	3516	1			T3	2		T4	3		T10	1
valid_sources[0x6e]	3048	1			T2	2		T10	1		T12	1
valid_sources[0x6f]	4190	1			T2	7		T10	2		T11	1
valid_sources[0x70]	4392	1			T2	7		T3	3		T10	2
valid_sources[0x71]	3050	1			T2	1		T12	7		T60	8
valid_sources[0x72]	4407	1			T2	2		T3	1		T4	1
valid_sources[0x73]	3629	1			T2	4		T4	2		T6	2
valid_sources[0x74]	3708	1			T2	6		T4	3		T10	2
valid_sources[0x75]	3283	1			T11	1		T12	12		T60	6
valid_sources[0x76]	3278	1			T4	2		T10	1		T11	2
valid_sources[0x77]	3378	1			T4	1		T8	5		T10	1
valid_sources[0x78]	5367	1			T2	3		T4	2		T10	1
valid_sources[0x79]	5772	1			T4	1		T9	1		T10	3
valid_sources[0x7a]	3568	1			T4	2		T10	3		T12	7
valid_sources[0x7b]	3300	1			T2	3		T10	1		T11	2
valid_sources[0x7c]	3124	1			T2	1		T4	1		T10	2
valid_sources[0x7d]	3595	1			T4	1		T10	3		T12	2
valid_sources[0x7e]	3779	1			T6	7		T10	1		T12	5
valid_sources[0x7f]	3409	1			T4	2		T11	2		T12	5
valid_sources[0x80]	3101	1			T4	1		T9	4		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

249513

1

T2

79

T3

47

T4

41

values[0x0]

all_enables

biggest_size

80654

1

T2

38

T3

15

T4

22

values[0x1]

all_enables

biggest_size

43426

1

T2

24

T3

13

T4

3