Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T2 T3 T10 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T2 T3 T10 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T12,T13,T67
1	0	Covered	T2,T92,T56

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54106492	9070	0	0
CascadeEffAonToRstPorAboveRise_A	54106492	9070	0	0
CascadeEffAonToRstPorIoAboveFall_A	51940267	9070	0	0
CascadeEffAonToRstPorIoAboveRise_A	51940267	9070	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25971125	9070	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25971125	9070	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12985223	9070	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12985223	9070	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25971343	9070	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25971343	9070	0	0
CascadeLcToLcAboveFall_A	54106492	22513	0	0
CascadeLcToLcAboveRise_A	54106492	22513	0	0
CascadeLcToLcAonAboveFall_A	1640650	22513	0	0
CascadeLcToLcAonAboveRise_A	1640650	22513	0	0
CascadeLcToLcShadowedAboveFall_A	54106492	22513	0	0
CascadeLcToLcShadowedAboveRise_A	54106492	22513	0	0
CascadePorToAonAboveFall_A	1640650	7218	0	0
CascadeSysToSysAboveFall_A	54106492	22513	0	0
CascadeSysToSysAboveRise_A	54106492	22513	0	0
ScanRstToAonRise_A	1640650	251	0	0
StablePorToAonRise_A	1640650	9070	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11439832	22513	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11439832	22513	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11439832	22513	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11439832	22513	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12985223	22513	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12985223	22513	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11439832	22513	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11439832	22513	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11439832	22513	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11439832	22513	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	9070	0	0
T1	9481	2	0	0
T2	18913	2	0	0
T3	11154	2	0	0
T4	11388	1	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	1	0	0
T10	11924	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	9070	0	0
T1	9481	2	0	0
T2	18913	2	0	0
T3	11154	2	0	0
T4	11388	1	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	1	0	0
T10	11924	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	9070	0	0
T1	9102	2	0	0
T2	18160	2	0	0
T3	10709	2	0	0
T4	10933	1	0	0
T5	28848	10	0	0
T6	12065	1	0	0
T7	14979	2	0	0
T8	6249	1	0	0
T9	10331	1	0	0
T10	11449	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	9070	0	0
T1	9102	2	0	0
T2	18160	2	0	0
T3	10709	2	0	0
T4	10933	1	0	0
T5	28848	10	0	0
T6	12065	1	0	0
T7	14979	2	0	0
T8	6249	1	0	0
T9	10331	1	0	0
T10	11449	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	9070	0	0
T1	4550	2	0	0
T2	9079	2	0	0
T3	5357	2	0	0
T4	5466	1	0	0
T5	14417	10	0	0
T6	6032	1	0	0
T7	7488	2	0	0
T8	3124	1	0	0
T9	5165	1	0	0
T10	5722	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	9070	0	0
T1	4550	2	0	0
T2	9079	2	0	0
T3	5357	2	0	0
T4	5466	1	0	0
T5	14417	10	0	0
T6	6032	1	0	0
T7	7488	2	0	0
T8	3124	1	0	0
T9	5165	1	0	0
T10	5722	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	9070	0	0
T1	2275	2	0	0
T2	4538	2	0	0
T3	2677	2	0	0
T4	2733	1	0	0
T5	7210	10	0	0
T6	3016	1	0	0
T7	3744	2	0	0
T8	1560	1	0	0
T9	2582	1	0	0
T10	2861	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	9070	0	0
T1	2275	2	0	0
T2	4538	2	0	0
T3	2677	2	0	0
T4	2733	1	0	0
T5	7210	10	0	0
T6	3016	1	0	0
T7	3744	2	0	0
T8	1560	1	0	0
T9	2582	1	0	0
T10	2861	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	9070	0	0
T1	4550	2	0	0
T2	9083	2	0	0
T3	5355	2	0	0
T4	5466	1	0	0
T5	14416	10	0	0
T6	6033	1	0	0
T7	7488	2	0	0
T8	3123	1	0	0
T9	5166	1	0	0
T10	5721	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	9070	0	0
T1	4550	2	0	0
T2	9083	2	0	0
T3	5355	2	0	0
T4	5466	1	0	0
T5	14416	10	0	0
T6	6033	1	0	0
T7	7488	2	0	0
T8	3123	1	0	0
T9	5166	1	0	0
T10	5721	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	22513	0	0
T1	284	2	0	0
T2	567	6	0	0
T3	333	6	0	0
T4	340	9	0	0
T5	903	10	0	0
T6	376	1	0	0
T7	466	2	0	0
T8	193	1	0	0
T9	322	8	0	0
T10	356	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	22513	0	0
T1	284	2	0	0
T2	567	6	0	0
T3	333	6	0	0
T4	340	9	0	0
T5	903	10	0	0
T6	376	1	0	0
T7	466	2	0	0
T8	193	1	0	0
T9	322	8	0	0
T10	356	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	7218	0	0
T1	284	4	0	0
T2	567	1	0	0
T3	333	1	0	0
T4	340	1	0	0
T5	903	10	0	0
T6	376	1	0	0
T7	466	12	0	0
T8	193	1	0	0
T9	322	1	0	0
T10	356	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106492	22513	0	0
T1	9481	2	0	0
T2	18913	6	0	0
T3	11154	6	0	0
T4	11388	9	0	0
T5	30045	10	0	0
T6	12568	1	0	0
T7	15603	2	0	0
T8	6507	1	0	0
T9	10763	8	0	0
T10	11924	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	251	0	0
T17	567	0	0	0
T36	0	2	0	0
T56	7460	1	0	0
T57	3134	4	0	0
T58	283	0	0	0
T59	7366	0	0	0
T91	0	1	0	0
T93	345	0	0	0
T94	333	0	0	0
T95	442	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T110	0	4	0	0
T111	906	0	0	0
T112	222	0	0	0
T113	0	3	0	0
T116	0	8	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	9070	0	0
T1	284	2	0	0
T2	567	2	0	0
T3	333	2	0	0
T4	340	1	0	0
T5	903	10	0	0
T6	376	1	0	0
T7	466	2	0	0
T8	193	1	0	0
T9	322	1	0	0
T10	356	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	22513	0	0
T1	2275	2	0	0
T2	4538	6	0	0
T3	2677	6	0	0
T4	2733	9	0	0
T5	7210	10	0	0
T6	3016	1	0	0
T7	3744	2	0	0
T8	1560	1	0	0
T9	2582	8	0	0
T10	2861	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	22513	0	0
T1	2275	2	0	0
T2	4538	6	0	0
T3	2677	6	0	0
T4	2733	9	0	0
T5	7210	10	0	0
T6	3016	1	0	0
T7	3744	2	0	0
T8	1560	1	0	0
T9	2582	8	0	0
T10	2861	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	22513	0	0
T1	2136	2	0	0
T2	4398	6	0	0
T3	2388	6	0	0
T4	2075	9	0	0
T5	6768	10	0	0
T6	2925	1	0	0
T7	3605	2	0	0
T8	1495	1	0	0
T9	1979	8	0	0
T10	2621	6	0	0