Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T60
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T60,T69
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T60
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T60
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T60
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12985223	14250	0	0
gen_assertions[0].RstEnOn_A	12985223	1009	0	0
gen_assertions[0].RstNOff_A	12985223	14250	0	0
gen_assertions[0].RstNOn_A	12985223	1009	0	0
gen_assertions[1].RstEnOff_A	51940267	13037	0	0
gen_assertions[1].RstEnOn_A	51940267	949	0	0
gen_assertions[1].RstNOff_A	51940267	13037	0	0
gen_assertions[1].RstNOn_A	51940267	949	0	0
gen_assertions[2].RstEnOff_A	25971125	13083	0	0
gen_assertions[2].RstEnOn_A	25971125	942	0	0
gen_assertions[2].RstNOff_A	25971125	13083	0	0
gen_assertions[2].RstNOn_A	25971125	942	0	0
gen_assertions[3].RstEnOff_A	25971343	13145	0	0
gen_assertions[3].RstEnOn_A	25971343	987	0	0
gen_assertions[3].RstNOff_A	25971343	13145	0	0
gen_assertions[3].RstNOn_A	25971343	987	0	0
gen_assertions[4].RstEnOff_A	1640650	21944	0	0
gen_assertions[4].RstEnOn_A	1640650	1023	0	0
gen_assertions[4].RstNOff_A	1640650	21944	0	0
gen_assertions[4].RstNOn_A	1640650	1023	0	0
gen_assertions[5].RstEnOff_A	12985223	14492	0	0
gen_assertions[5].RstEnOn_A	12985223	1083	0	0
gen_assertions[5].RstNOff_A	12985223	14492	0	0
gen_assertions[5].RstNOn_A	12985223	1083	0	0
gen_assertions[6].RstEnOff_A	12985223	14542	0	0
gen_assertions[6].RstEnOn_A	12985223	1135	0	0
gen_assertions[6].RstNOff_A	12985223	14542	0	0
gen_assertions[6].RstNOn_A	12985223	1135	0	0
gen_assertions[7].RstEnOff_A	12985223	14607	0	0
gen_assertions[7].RstEnOn_A	12985223	1195	0	0
gen_assertions[7].RstNOff_A	12985223	14607	0	0
gen_assertions[7].RstNOn_A	12985223	1195	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14250	0	0
T2	4538	5	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	2	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	4	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1009	0	0
T2	4538	1	0	0
T3	2677	0	0	0
T4	2733	3	0	0
T5	7210	0	0	0
T6	3016	2	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	4	0	0
T10	2861	0	0	0
T11	2519	0	0	0
T24	0	2	0	0
T56	0	13	0	0
T60	0	7	0	0
T69	0	9	0	0
T70	0	2	0	0
T72	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14250	0	0
T2	4538	5	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	2	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	4	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1009	0	0
T2	4538	1	0	0
T3	2677	0	0	0
T4	2733	3	0	0
T5	7210	0	0	0
T6	3016	2	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	4	0	0
T10	2861	0	0	0
T11	2519	0	0	0
T24	0	2	0	0
T56	0	13	0	0
T60	0	7	0	0
T69	0	9	0	0
T70	0	2	0	0
T72	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	13037	0	0
T2	18160	3	0	0
T3	10709	4	0	0
T4	10933	7	0	0
T5	28848	0	0	0
T6	12065	3	0	0
T7	14979	0	0	0
T8	6249	0	0	0
T9	10331	7	0	0
T10	11449	5	0	0
T11	10077	4	0	0
T12	0	31	0	0
T13	0	4	0	0
T60	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	949	0	0
T4	10933	3	0	0
T5	28848	0	0	0
T6	12065	3	0	0
T7	14979	0	0	0
T8	6249	0	0	0
T9	10331	1	0	0
T10	11449	1	0	0
T11	10077	0	0	0
T12	97311	0	0	0
T14	28791	0	0	0
T56	0	13	0	0
T60	0	7	0	0
T69	0	8	0	0
T70	0	3	0	0
T93	0	1	0	0
T94	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	13037	0	0
T2	18160	3	0	0
T3	10709	4	0	0
T4	10933	7	0	0
T5	28848	0	0	0
T6	12065	3	0	0
T7	14979	0	0	0
T8	6249	0	0	0
T9	10331	7	0	0
T10	11449	5	0	0
T11	10077	4	0	0
T12	0	31	0	0
T13	0	4	0	0
T60	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51940267	949	0	0
T4	10933	3	0	0
T5	28848	0	0	0
T6	12065	3	0	0
T7	14979	0	0	0
T8	6249	0	0	0
T9	10331	1	0	0
T10	11449	1	0	0
T11	10077	0	0	0
T12	97311	0	0	0
T14	28791	0	0	0
T56	0	13	0	0
T60	0	7	0	0
T69	0	8	0	0
T70	0	3	0	0
T93	0	1	0	0
T94	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	13083	0	0
T2	9079	3	0	0
T3	5357	4	0	0
T4	5466	7	0	0
T5	14417	0	0	0
T6	6032	5	0	0
T7	7488	0	0	0
T8	3124	0	0	0
T9	5165	7	0	0
T10	5722	5	0	0
T11	5037	4	0	0
T12	0	31	0	0
T13	0	5	0	0
T60	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	942	0	0
T6	6032	5	0	0
T7	7488	0	0	0
T8	3124	0	0	0
T9	5165	0	0	0
T10	5722	1	0	0
T11	5037	0	0	0
T12	48649	0	0	0
T13	0	1	0	0
T14	14394	0	0	0
T54	2947	0	0	0
T56	0	14	0	0
T60	6367	7	0	0
T67	0	1	0	0
T69	0	9	0	0
T70	0	3	0	0
T95	0	8	0	0
T96	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	13083	0	0
T2	9079	3	0	0
T3	5357	4	0	0
T4	5466	7	0	0
T5	14417	0	0	0
T6	6032	5	0	0
T7	7488	0	0	0
T8	3124	0	0	0
T9	5165	7	0	0
T10	5722	5	0	0
T11	5037	4	0	0
T12	0	31	0	0
T13	0	5	0	0
T60	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971125	942	0	0
T6	6032	5	0	0
T7	7488	0	0	0
T8	3124	0	0	0
T9	5165	0	0	0
T10	5722	1	0	0
T11	5037	0	0	0
T12	48649	0	0	0
T13	0	1	0	0
T14	14394	0	0	0
T54	2947	0	0	0
T56	0	14	0	0
T60	6367	7	0	0
T67	0	1	0	0
T69	0	9	0	0
T70	0	3	0	0
T95	0	8	0	0
T96	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	13145	0	0
T2	9083	3	0	0
T3	5355	4	0	0
T4	5466	7	0	0
T5	14416	0	0	0
T6	6033	5	0	0
T7	7488	0	0	0
T8	3123	0	0	0
T9	5166	7	0	0
T10	5721	4	0	0
T11	5041	4	0	0
T12	0	31	0	0
T13	0	4	0	0
T60	0	9	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	987	0	0
T6	6033	5	0	0
T7	7488	0	0	0
T8	3123	0	0	0
T9	5166	0	0	0
T10	5721	0	0	0
T11	5041	0	0	0
T12	48654	0	0	0
T14	14390	0	0	0
T50	0	7	0	0
T54	2948	0	0	0
T56	0	11	0	0
T60	6367	9	0	0
T69	0	10	0	0
T70	0	5	0	0
T93	0	1	0	0
T95	0	7	0	0
T96	0	3	0	0
T97	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	13145	0	0
T2	9083	3	0	0
T3	5355	4	0	0
T4	5466	7	0	0
T5	14416	0	0	0
T6	6033	5	0	0
T7	7488	0	0	0
T8	3123	0	0	0
T9	5166	7	0	0
T10	5721	4	0	0
T11	5041	4	0	0
T12	0	31	0	0
T13	0	4	0	0
T60	0	9	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25971343	987	0	0
T6	6033	5	0	0
T7	7488	0	0	0
T8	3123	0	0	0
T9	5166	0	0	0
T10	5721	0	0	0
T11	5041	0	0	0
T12	48654	0	0	0
T14	14390	0	0	0
T50	0	7	0	0
T54	2948	0	0	0
T56	0	11	0	0
T60	6367	9	0	0
T69	0	10	0	0
T70	0	5	0	0
T93	0	1	0	0
T95	0	7	0	0
T96	0	3	0	0
T97	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	21944	0	0
T1	284	2	0	0
T2	567	7	0	0
T3	333	5	0	0
T4	340	8	0	0
T5	903	2	0	0
T6	376	8	0	0
T7	466	2	0	0
T8	193	1	0	0
T9	322	7	0	0
T10	356	7	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	1023	0	0
T2	567	1	0	0
T3	333	0	0	0
T4	340	0	0	0
T5	903	0	0	0
T6	376	7	0	0
T7	466	0	0	0
T8	193	0	0	0
T9	322	0	0	0
T10	356	1	0	0
T11	314	0	0	0
T13	0	1	0	0
T56	0	14	0	0
T60	0	10	0	0
T69	0	10	0	0
T70	0	6	0	0
T93	0	1	0	0
T95	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	21944	0	0
T1	284	2	0	0
T2	567	7	0	0
T3	333	5	0	0
T4	340	8	0	0
T5	903	2	0	0
T6	376	8	0	0
T7	466	2	0	0
T8	193	1	0	0
T9	322	7	0	0
T10	356	7	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640650	1023	0	0
T2	567	1	0	0
T3	333	0	0	0
T4	340	0	0	0
T5	903	0	0	0
T6	376	7	0	0
T7	466	0	0	0
T8	193	0	0	0
T9	322	0	0	0
T10	356	1	0	0
T11	314	0	0	0
T13	0	1	0	0
T56	0	14	0	0
T60	0	10	0	0
T69	0	10	0	0
T70	0	6	0	0
T93	0	1	0	0
T95	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14492	0	0
T2	4538	4	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	5	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	5	0	0
T60	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1083	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	1	0	0
T11	2519	0	0	0
T12	24329	0	0	0
T13	0	1	0	0
T14	7199	0	0	0
T54	1473	0	0	0
T56	0	13	0	0
T60	3182	9	0	0
T69	0	13	0	0
T70	0	7	0	0
T93	0	1	0	0
T95	0	11	0	0
T96	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14492	0	0
T2	4538	4	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	5	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	5	0	0
T60	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1083	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	1	0	0
T11	2519	0	0	0
T12	24329	0	0	0
T13	0	1	0	0
T14	7199	0	0	0
T54	1473	0	0	0
T56	0	13	0	0
T60	3182	9	0	0
T69	0	13	0	0
T70	0	7	0	0
T93	0	1	0	0
T95	0	11	0	0
T96	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14542	0	0
T2	4538	4	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	5	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1135	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	1	0	0
T11	2519	0	0	0
T12	24329	0	0	0
T14	7199	0	0	0
T50	0	8	0	0
T54	1473	0	0	0
T56	0	13	0	0
T60	3182	8	0	0
T69	0	14	0	0
T70	0	7	0	0
T95	0	9	0	0
T96	0	7	0	0
T97	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14542	0	0
T2	4538	4	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	5	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1135	0	0
T6	3016	7	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	1	0	0
T11	2519	0	0	0
T12	24329	0	0	0
T14	7199	0	0	0
T50	0	8	0	0
T54	1473	0	0	0
T56	0	13	0	0
T60	3182	8	0	0
T69	0	14	0	0
T70	0	7	0	0
T95	0	9	0	0
T96	0	7	0	0
T97	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14607	0	0
T2	4538	5	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	9	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	4	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	13	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1195	0	0
T2	4538	1	0	0
T3	2677	0	0	0
T4	2733	0	0	0
T5	7210	0	0	0
T6	3016	9	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	0	0	0
T11	2519	0	0	0
T56	0	11	0	0
T60	0	13	0	0
T69	0	13	0	0
T70	0	8	0	0
T93	0	1	0	0
T95	0	14	0	0
T96	0	9	0	0
T98	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	14607	0	0
T2	4538	5	0	0
T3	2677	4	0	0
T4	2733	8	0	0
T5	7210	0	0	0
T6	3016	9	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	7	0	0
T10	2861	4	0	0
T11	2519	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T60	0	13	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12985223	1195	0	0
T2	4538	1	0	0
T3	2677	0	0	0
T4	2733	0	0	0
T5	7210	0	0	0
T6	3016	9	0	0
T7	3744	0	0	0
T8	1560	0	0	0
T9	2582	0	0	0
T10	2861	0	0	0
T11	2519	0	0	0
T56	0	11	0	0
T60	0	13	0	0
T69	0	13	0	0
T70	0	8	0	0
T93	0	1	0	0
T95	0	14	0	0
T96	0	9	0	0
T98	0	1	0	0