Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12194319	7331	0	0
alert_regwen_rd_A	12194319	5935	0	0
cpu_regwen_rd_A	12194319	5836	0	0
sw_rst_ctrl_n_0_rd_A	12194319	8805	0	0
sw_rst_ctrl_n_1_rd_A	12194319	8848	0	0
sw_rst_ctrl_n_2_rd_A	12194319	8760	0	0
sw_rst_ctrl_n_3_rd_A	12194319	8785	0	0
sw_rst_ctrl_n_4_rd_A	12194319	8916	0	0
sw_rst_ctrl_n_5_rd_A	12194319	8640	0	0
sw_rst_ctrl_n_6_rd_A	12194319	8573	0	0
sw_rst_ctrl_n_7_rd_A	12194319	8913	0	0
sw_rst_regwen_0_rd_A	12194319	6014	0	0
sw_rst_regwen_1_rd_A	12194319	6004	0	0
sw_rst_regwen_2_rd_A	12194319	6214	0	0
sw_rst_regwen_3_rd_A	12194319	6018	0	0
sw_rst_regwen_4_rd_A	12194319	6141	0	0
sw_rst_regwen_5_rd_A	12194319	5955	0	0
sw_rst_regwen_6_rd_A	12194319	6120	0	0
sw_rst_regwen_7_rd_A	12194319	6101	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	7331	0	0
T76	2366	1	0	0
T80	2878	65	0	0
T81	3355	182	0	0
T82	20167	1	0	0
T83	10904	1	0	0
T84	7110	431	0	0
T85	3219	16	0	0
T99	4676	28	0	0
T100	2635	3	0	0
T101	11001	710	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	5935	0	0
T17	4474	0	0	0
T56	53687	46	0	0
T57	19133	0	0	0
T58	2132	0	0	0
T59	55530	0	0	0
T93	2482	0	0	0
T94	1918	0	0	0
T95	3457	0	0	0
T111	7021	0	0	0
T112	1693	0	0	0
T119	0	186	0	0
T120	0	25	0	0
T123	0	121	0	0
T125	0	88	0	0
T127	0	65	0	0
T148	0	25	0	0
T149	0	49	0	0
T150	0	78	0	0
T151	0	192	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	5836	0	0
T17	4474	0	0	0
T56	53687	40	0	0
T57	19133	0	0	0
T58	2132	0	0	0
T59	55530	0	0	0
T93	2482	0	0	0
T94	1918	0	0	0
T95	3457	0	0	0
T111	7021	0	0	0
T112	1693	0	0	0
T119	0	187	0	0
T120	0	41	0	0
T123	0	124	0	0
T125	0	88	0	0
T127	0	65	0	0
T148	0	42	0	0
T149	0	58	0	0
T150	0	46	0	0
T151	0	174	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8805	0	0
T17	4474	0	0	0
T38	0	206	0	0
T56	53687	157	0	0
T57	19133	0	0	0
T69	11525	133	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	69	0	0
T73	1992	0	0	0
T89	0	18	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	1	0	0
T152	0	66	0	0
T153	0	84	0	0
T154	0	10	0	0
T155	0	77	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8848	0	0
T17	4474	0	0	0
T38	0	162	0	0
T56	53687	158	0	0
T57	19133	0	0	0
T69	11525	171	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	66	0	0
T73	1992	0	0	0
T89	0	24	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	4	0	0
T152	0	37	0	0
T153	0	109	0	0
T154	0	12	0	0
T155	0	91	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8760	0	0
T17	4474	0	0	0
T38	0	189	0	0
T56	53687	126	0	0
T57	19133	0	0	0
T69	11525	174	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	74	0	0
T73	1992	0	0	0
T89	0	17	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	13	0	0
T152	0	47	0	0
T153	0	128	0	0
T154	0	13	0	0
T155	0	39	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8785	0	0
T17	4474	0	0	0
T38	0	152	0	0
T56	53687	153	0	0
T57	19133	0	0	0
T69	11525	112	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	51	0	0
T73	1992	0	0	0
T89	0	16	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	6	0	0
T152	0	56	0	0
T153	0	128	0	0
T154	0	33	0	0
T155	0	57	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8916	0	0
T17	4474	0	0	0
T38	0	192	0	0
T56	53687	160	0	0
T57	19133	0	0	0
T69	11525	150	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	78	0	0
T73	1992	0	0	0
T89	0	26	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	10	0	0
T152	0	41	0	0
T153	0	107	0	0
T154	0	18	0	0
T155	0	97	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8640	0	0
T17	4474	0	0	0
T38	0	205	0	0
T56	53687	122	0	0
T57	19133	0	0	0
T69	11525	138	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	53	0	0
T73	1992	0	0	0
T89	0	18	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	6	0	0
T152	0	54	0	0
T153	0	110	0	0
T154	0	15	0	0
T155	0	88	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8573	0	0
T17	4474	0	0	0
T38	0	198	0	0
T56	53687	138	0	0
T57	19133	0	0	0
T69	11525	103	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	48	0	0
T73	1992	0	0	0
T89	0	17	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	9	0	0
T152	0	57	0	0
T153	0	110	0	0
T154	0	20	0	0
T155	0	75	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	8913	0	0
T17	4474	0	0	0
T38	0	200	0	0
T56	53687	136	0	0
T57	19133	0	0	0
T69	11525	162	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	69	0	0
T73	1992	0	0	0
T89	0	14	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	7	0	0
T152	0	55	0	0
T153	0	85	0	0
T154	0	23	0	0
T155	0	48	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6014	0	0
T17	4474	0	0	0
T38	0	29	0	0
T56	53687	36	0	0
T57	19133	0	0	0
T69	11525	21	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	4	0	0
T125	0	96	0	0
T127	0	50	0	0
T153	0	10	0	0
T154	0	6	0	0
T155	0	22	0	0
T156	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6004	0	0
T17	4474	0	0	0
T38	0	30	0	0
T56	53687	31	0	0
T57	19133	0	0	0
T69	11525	6	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	5	0	0
T125	0	66	0	0
T127	0	65	0	0
T153	0	19	0	0
T154	0	5	0	0
T155	0	21	0	0
T156	0	16	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6214	0	0
T17	4474	0	0	0
T38	0	52	0	0
T56	53687	68	0	0
T57	19133	0	0	0
T69	11525	22	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	8	0	0
T125	0	68	0	0
T127	0	75	0	0
T153	0	10	0	0
T154	0	5	0	0
T155	0	19	0	0
T156	0	25	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6018	0	0
T17	4474	0	0	0
T38	0	27	0	0
T56	53687	53	0	0
T57	19133	0	0	0
T69	11525	19	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	1	0	0
T119	0	150	0	0
T125	0	85	0	0
T127	0	68	0	0
T153	0	15	0	0
T155	0	9	0	0
T156	0	18	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6141	0	0
T17	4474	0	0	0
T38	0	17	0	0
T56	53687	51	0	0
T57	19133	0	0	0
T69	11525	20	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	10	0	0
T125	0	96	0	0
T127	0	50	0	0
T153	0	20	0	0
T154	0	3	0	0
T155	0	8	0	0
T156	0	6	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	5955	0	0
T17	4474	0	0	0
T38	0	28	0	0
T56	53687	35	0	0
T57	19133	0	0	0
T69	11525	18	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	3	0	0
T125	0	83	0	0
T127	0	61	0	0
T153	0	11	0	0
T154	0	8	0	0
T155	0	19	0	0
T156	0	5	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6120	0	0
T17	4474	0	0	0
T38	0	26	0	0
T56	53687	54	0	0
T57	19133	0	0	0
T69	11525	22	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T119	0	143	0	0
T125	0	57	0	0
T127	0	58	0	0
T153	0	13	0	0
T154	0	8	0	0
T155	0	26	0	0
T156	0	8	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194319	6101	0	0
T17	4474	0	0	0
T38	0	40	0	0
T56	53687	35	0	0
T57	19133	0	0	0
T69	11525	19	0	0
T70	2842	0	0	0
T71	3511	0	0	0
T72	5372	0	0	0
T73	1992	0	0	0
T92	31132	0	0	0
T93	2482	0	0	0
T98	0	6	0	0
T125	0	90	0	0
T127	0	46	0	0
T153	0	43	0	0
T154	0	2	0	0
T155	0	28	0	0
T156	0	18	0	0