Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11439832	13443	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11439832	123747	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11439832	6533747	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11439832	197485	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11439832	13443	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11439832	123747	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11439832	6533747	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11439832	197485	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	13443	0	0
T2	4398	4	0	0
T3	2388	4	0	0
T4	2075	8	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	7	0	0
T10	2621	4	0	0
T11	2375	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T23	0	4	0	0
T24	0	14	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	123747	0	0
T2	4398	38	0	0
T3	2388	37	0	0
T4	2075	72	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	63	0	0
T10	2621	37	0	0
T11	2375	38	0	0
T12	0	318	0	0
T13	0	37	0	0
T23	0	38	0	0
T24	0	126	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	6533747	0	0
T1	2136	602	0	0
T2	4398	3431	0	0
T3	2388	1415	0	0
T4	2075	1311	0	0
T5	6768	630	0	0
T6	2925	2358	0	0
T7	3605	732	0	0
T8	1495	894	0	0
T9	1979	1306	0	0
T10	2621	1624	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	197485	0	0
T2	4398	51	0	0
T3	2388	70	0	0
T4	2075	115	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	101	0	0
T10	2621	64	0	0
T11	2375	64	0	0
T12	0	512	0	0
T13	0	65	0	0
T23	0	50	0	0
T24	0	190	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	13443	0	0
T2	4398	4	0	0
T3	2388	4	0	0
T4	2075	8	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	7	0	0
T10	2621	4	0	0
T11	2375	4	0	0
T12	0	35	0	0
T13	0	4	0	0
T23	0	4	0	0
T24	0	14	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	123747	0	0
T2	4398	38	0	0
T3	2388	37	0	0
T4	2075	72	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	63	0	0
T10	2621	37	0	0
T11	2375	38	0	0
T12	0	318	0	0
T13	0	37	0	0
T23	0	38	0	0
T24	0	126	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	6533747	0	0
T1	2136	602	0	0
T2	4398	3431	0	0
T3	2388	1415	0	0
T4	2075	1311	0	0
T5	6768	630	0	0
T6	2925	2358	0	0
T7	3605	732	0	0
T8	1495	894	0	0
T9	1979	1306	0	0
T10	2621	1624	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11439832	197485	0	0
T2	4398	51	0	0
T3	2388	70	0	0
T4	2075	115	0	0
T5	6768	0	0	0
T6	2925	0	0	0
T7	3605	0	0	0
T8	1495	0	0	0
T9	1979	101	0	0
T10	2621	64	0	0
T11	2375	64	0	0
T12	0	512	0	0
T13	0	65	0	0
T23	0	50	0	0
T24	0	190	0	0