f0ee8f0c36| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 0 | 50 | 0.00 | ||
| V1 | random | keymgr_random | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | keymgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | keymgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 0 | 20 | 0.00 | ||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 155 | 0.00 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 0 | 50 | 0.00 | ||
| V2 | sideload | keymgr_sideload | 0 | 50 | 0.00 | ||
| keymgr_sideload_kmac | 0 | 50 | 0.00 | ||||
| keymgr_sideload_aes | 0 | 50 | 0.00 | ||||
| keymgr_sideload_otbn | 0 | 50 | 0.00 | ||||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 0 | 50 | 0.00 | ||
| V2 | lc_disable | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 0 | 50 | 0.00 | ||
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 0 | 50 | 0.00 | ||
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 0 | 50 | 0.00 | ||
| V2 | stress_all | keymgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | keymgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | keymgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | keymgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| keymgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| keymgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| keymgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | tl_intg_err | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| keymgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 0 | 50 | 0.00 | ||
| keymgr_csr_rw | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 0 | 50 | 0.00 | ||
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 0 | 50 | 0.00 | ||
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 0 | 165 | 0.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1110 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 6 | 6 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1112 failures:
0.keymgr_smoke.932291121
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log
1.keymgr_smoke.2757629430
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_smoke/latest/run.log
... and 48 more failures.
0.keymgr_sideload.3060172703
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload/latest/run.log
1.keymgr_sideload.4026833987
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload/latest/run.log
... and 48 more failures.
0.keymgr_sideload_kmac.965731259
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest/run.log
1.keymgr_sideload_kmac.410857507
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest/run.log
... and 48 more failures.
0.keymgr_sideload_aes.4146250176
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log
1.keymgr_sideload_aes.1854176747
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_aes/latest/run.log
... and 48 more failures.
0.keymgr_sideload_otbn.3524457640
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest/run.log
1.keymgr_sideload_otbn.3411754955
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest/run.log
... and 48 more failures.
Job keymgr-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/default/build.log
Job ID: smart:ae869716-65d2-4165-bd36-d57a04c03a3a
Job keymgr-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/build.log
Job ID: smart:ef21663d-2a79-4e35-ae36-772bbd84c1a0