Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : keymgr_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.79 100.00 98.06 100.00 100.00 90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl 97.79 100.00 98.06 100.00 100.00 90.91



Module Instance : tb.dut.u_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.79 100.00 98.06 100.00 100.00 90.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 99.70 95.19 95.40 100.00 98.62 94.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 97.95 97.95
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 93.15 93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 97.26 97.26
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 93.15 93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 97.26 97.26
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 97.95 97.95
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 97.26 97.26
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 95.89 95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 95.89 95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 95.89 95.89
u_cnt 100.00 100.00
u_data_en 84.15 97.44 33.33 100.00 90.00 100.00
u_err 94.81 100.00 84.44 100.00
u_hw_sel 100.00 100.00 100.00 100.00
u_key_valid_sync 100.00 100.00 100.00
u_op_state 100.00 100.00 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_ctrl
Line No.TotalCoveredPercent
TOTAL183183100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23711100.00
ALWAYS24333100.00
ALWAYS24633100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN27011100.00
ALWAYS27277100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN32811100.00
ALWAYS3312121100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN43311100.00
ALWAYS4377373100.00
ALWAYS65544100.00
ALWAYS6631212100.00
ALWAYS69955100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN74311100.00
CONT_ASSIGN77411100.00
ALWAYS78233100.00
CONT_ASSIGN79211100.00
ALWAYS86933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
149 1 1
150 1 1
151 1 1
152 1 1
154 1 1
164 1 1
165 1 1
168 1 1
184 1 1
185 1 1
186 1 1
187 1 1
201 1 1
206 1 1
212 1 1
214 1 1
229 1 1
237 1 1
243 3 3
246 1 1
247 1 1
249 1 1
257 1 1
259 1 1
263 2 2
270 1 1
272 1 1
273 1 1
274 1 1
276 1 1
277 1 1
278 1 1
279 1 1
298 16 16
305 1 1
328 1 1
331 1 1
332 1 1
333 1 1
337 1 1
339 1 1
340 1 1
343 1 1
349 1 1
350 1 1
351 1 1
352 1 1
353 1 1
355 unreachable
357 unreachable
362 1 1
363 1 1
364 1 1
370 1 1
371 1 1
375 1 1
376 1 1
377 1 1
378 1 1
415 1 1
426 1 1
427 1 1
433 1 1
437 1 1
440 1 1
441 1 1
442 1 1
445 1 1
448 1 1
451 1 1
454 1 1
457 1 1
460 1 1
463 1 1
466 1 1
470 1 1
472 1 1
475 1 1
479 1 1
483 1 1
486 1 1
487 1 1
488 1 1
489 1 1
MISSING_ELSE
495 1 1
496 1 1
498 1 1
499 1 1
MISSING_ELSE
505 1 1
506 1 1
511 1 1
512 unreachable
513 unreachable
MISSING_ELSE
519 1 1
520 1 1
521 1 1
528 1 1
531 1 1
532 1 1
534 1 1
535 1 1
536 1 1
537 1 1
538 1 1
539 1 1
MISSING_ELSE
545 1 1
550 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
MISSING_ELSE
564 1 1
569 1 1
572 1 1
573 1 1
574 1 1
575 1 1
576 1 1
577 1 1
MISSING_ELSE
584 1 1
589 1 1
591 1 1
592 1 1
593 1 1
594 1 1
MISSING_ELSE
603 1 1
605 1 1
606 1 1
615 1 1
616 1 1
MISSING_ELSE
627 1 1
628 1 1
630 1 1
631 1 1
MISSING_ELSE
636 1 1
637 1 1
655 1 1
656 1 1
657 1 1
658 1 1
MISSING_ELSE
663 1 1
664 1 1
666 1 1
668 1 1
671 1 1
674 1 1
677 1 1
680 1 1
683 1 1
686 1 1
687 1 1
691 1 1
699 1 1
700 1 1
704 1 1
705 1 1
706 1 1
MISSING_ELSE
737 1 1
743 1 1
774 1 1
782 1 1
783 1 1
785 1 1
792 1 1
869 3 3


Cond Coverage for Module : keymgr_ctrl
TotalCoveredPercent
Conditions20620298.06
Logical20620298.06
Non-Logical00
Event00

 LINE       149
 EXPRESSION (op_i == OpAdvance)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (op_i == OpGenId)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (op_i == OpGenSwOut)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       152
 EXPRESSION (op_i == OpGenHwOut)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       154
 EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
             ----1----   ----2----   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       164
 EXPRESSION (op_start_i & adv_op & en_i)
             -----1----   ---2--   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT6,T48,T49
111CoveredT1,T2,T3

 LINE       165
 EXPRESSION (op_start_i & gen_hw_op & en_i)
             -----1----   ----2----   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT6,T7,T8
111CoveredT1,T2,T3

 LINE       168
 EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
             ----------1----------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T6,T50

 LINE       168
 SUB-EXPRESSION (op_start_i & dis_op)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T6,T50
10CoveredT1,T2,T3
11CoveredT2,T6,T50

 LINE       184
 EXPRESSION (op_req & adv_op)
             ---1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       185
 EXPRESSION (op_req & dis_op)
             ---1--   ---2--
-1--2-StatusTests
01CoveredT2,T6,T50
10CoveredT1,T2,T3
11CoveredT2,T6,T50

 LINE       186
 EXPRESSION (op_req & gen_id_op)
             ---1--   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       187
 EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
             ---1--   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       187
 SUB-EXPRESSION (gen_sw_op | gen_hw_op)
                 ----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T4,T5

 LINE       201
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T3,T4
111CoveredT1,T2,T3

 LINE       201
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T36,T40
10CoveredT1,T2,T3

 LINE       229
 EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T35,T6

 LINE       229
 SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       229
 SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       237
 EXPRESSION (random_req | disabled | invalid | wipe_req)
             -----1----   ----2---   ---3---   ----4---
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT41,T35,T6
0010CoveredT41,T35,T6
0100CoveredT1,T2,T3
1000CoveredT1,T2,T3

 LINE       259
 EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       315
 EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
             --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       328
 EXPRESSION (op_req ? cnt[0] : '0)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (adv_op || dis_op)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T50
10CoveredT1,T2,T3

 LINE       390
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       390
 EXPRESSION (op_update | random_req)
             ----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       415
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       415
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T17
10CoveredT1,T2,T3

 LINE       426
 EXPRESSION (op_ack & adv_req & ((~op_err)))
             ---1--   ---2---   -----3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T3,T4
111CoveredT1,T2,T3

 LINE       427
 EXPRESSION (op_ack & dis_req)
             ---1--   ---2---
-1--2-StatusTests
01CoveredT2,T6,T50
10CoveredT1,T2,T3
11CoveredT2,T6,T50

 LINE       483
 EXPRESSION (op_start_i & ((~advance_sel)))
             -----1----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T17

 LINE       511
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T3

 LINE       521
 EXPRESSION (en_i ? StCtrlInit : StCtrlWipe)
             --1-
-1-StatusTests
0CoveredT51,T52,T53
1CoveredT1,T2,T3

 LINE       531
 EXPRESSION (advance_sel ? Creator : Disable)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       532
 EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
             -----1----   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       532
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T50,T7
10CoveredT1,T2,T3

 LINE       534
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT41,T27,T29
10CoveredT6,T50,T7

 LINE       550
 EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT54,T55,T56

 LINE       550
 SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       553
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT36,T40,T57
10CoveredT8,T58,T59

 LINE       569
 EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T50,T60

 LINE       569
 SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       572
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT42,T37,T43
10CoveredT61,T62,T63

 LINE       589
 EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       589
 SUB-EXPRESSION (disable_sel | advance_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT2,T7,T64

 LINE       591
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT46,T65,T66
10CoveredT67,T68,T69

 LINE       593
 EXPRESSION (adv_state || dis_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T7,T64
10CoveredT1,T3,T4

 LINE       630
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT33,T70,T71
10CoveredT72,T73,T74

 LINE       704
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       737
 EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
             -----------------------1----------------------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT33,T34,T75
10CoveredT22,T38,T24

 LINE       737
 SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
                 ----1---   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT31,T22,T38

 LINE       737
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       737
 SUB-EXPRESSION (gen_en_o & ((~gen_op)))
                 ----1---   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT31,T33,T34

 LINE       743
 EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T35,T36

 LINE       743
 SUB-EXPRESSION ((op_ack | op_update) & invalid)
                 ----------1---------   ---2---
-1--2-StatusTests
01CoveredT41,T35,T6
10CoveredT1,T2,T3
11CoveredT41,T35,T36

 LINE       743
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T36,T40

 LINE       743
 SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
                 ----------1---------   ------2-----
-1--2-StatusTests
01CoveredT35,T36,T40
10CoveredT1,T2,T3
11CoveredT41,T36,T40

 LINE       743
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION ((op_ack | op_update) & disabled)
                 ----------1---------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
                 ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION ((op_ack | op_update) & op_err)
                 ----------1---------   ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       743
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       774
 EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
             ----------1---------   --------------------------------------------2--------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       774
 SUB-EXPRESSION (state_d != state_q)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       792
 EXPRESSION (vld_state_change_q & ((!adv_op)))
             ---------1--------   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       794
 EXPRESSION (disabled | (initialized & ((~en_i))))
             ----1---   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T50,T7
10CoveredT1,T2,T3

 LINE       794
 SUB-EXPRESSION (initialized & ((~en_i)))
                 -----1-----   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT6,T50,T7

 LINE       794
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T14
10Not Covered

FSM Coverage for Module : keymgr_ctrl
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 19 19 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrlCreatorRootKey 539 Covered T1,T2,T3
StCtrlDisabled 537 Covered T1,T2,T3
StCtrlEntropyReseed 489 Covered T1,T2,T3
StCtrlInit 521 Covered T1,T2,T3
StCtrlInvalid 616 Covered T41,T35,T6
StCtrlOwnerIntKey 558 Covered T1,T2,T3
StCtrlOwnerKey 577 Covered T1,T2,T3
StCtrlRandom 499 Covered T1,T2,T3
StCtrlReset 474 Covered T1,T2,T3
StCtrlRootKey 513 Covered T1,T2,T3
StCtrlWipe 487 Covered T41,T35,T6


transitions   Line No.   Covered   Tests   
StCtrlCreatorRootKey->StCtrlDisabled 556 Covered T54,T55,T56
StCtrlCreatorRootKey->StCtrlOwnerIntKey 558 Covered T1,T2,T3
StCtrlCreatorRootKey->StCtrlWipe 554 Covered T36,T40,T57
StCtrlDisabled->StCtrlWipe 631 Covered T72,T33,T73
StCtrlEntropyReseed->StCtrlRandom 499 Covered T1,T2,T3
StCtrlInit->StCtrlCreatorRootKey 539 Covered T1,T2,T3
StCtrlInit->StCtrlDisabled 537 Covered T76,T77,T78
StCtrlInit->StCtrlWipe 535 Covered T41,T6,T50
StCtrlOwnerIntKey->StCtrlDisabled 575 Covered T6,T50,T60
StCtrlOwnerIntKey->StCtrlOwnerKey 577 Covered T1,T2,T3
StCtrlOwnerIntKey->StCtrlWipe 573 Covered T42,T37,T43
StCtrlOwnerKey->StCtrlDisabled 594 Covered T1,T2,T3
StCtrlOwnerKey->StCtrlWipe 592 Covered T46,T67,T65
StCtrlRandom->StCtrlRootKey 513 Covered T1,T2,T3
StCtrlReset->StCtrlEntropyReseed 489 Covered T1,T2,T3
StCtrlReset->StCtrlWipe 487 Covered T35,T31,T12
StCtrlRootKey->StCtrlInit 521 Covered T1,T2,T3
StCtrlRootKey->StCtrlWipe 521 Covered T51,T52,T53
StCtrlWipe->StCtrlInvalid 616 Covered T41,T35,T6



Branch Coverage for Module : keymgr_ctrl
Line No.TotalCoveredPercent
Branches 92 92 100.00
TERNARY 229 4 4 100.00
TERNARY 259 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 415 2 2 100.00
TERNARY 743 6 6 100.00
TERNARY 263 2 2 100.00
TERNARY 263 2 2 100.00
IF 243 2 2 100.00
IF 246 2 2 100.00
IF 272 2 2 100.00
CASE 337 7 7 100.00
CASE 472 39 39 100.00
IF 655 3 3 100.00
CASE 666 9 9 100.00
IF 700 4 4 100.00
IF 782 2 2 100.00
IF 869 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 229 (wipe_req) ? -2-: 229 (random_req) ? -3-: 229 (init_o) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T41,T35,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 259 (advance_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 (op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 415 (op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 743 (((op_ack | op_update) & invalid)) ? -2-: 743 (((op_ack | op_update) & op_fault_err)) ? -3-: 743 (((op_ack | op_update) & disabled)) ? -4-: 743 (((op_ack | op_update) & op_err)) ? -5-: 743 ((op_ack | op_update)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T41,T35,T36
0 1 - - - Covered T41,T36,T40
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 263 (invalid_stage_sel_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 263 (invalid_stage_sel_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 243 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 246 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 272 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 case (update_sel) -2-: 349 if (root_key_valid_q) -3-: 371 ((adv_op || dis_op)) ?

Branches:
-1--2--3-StatusTests
KeyUpdateRandom - - Covered T1,T2,T3
KeyUpdateRoot 1 - Covered T1,T2,T3
KeyUpdateRoot 0 - Covered T27,T28,T29
KeyUpdateKmac - 1 Covered T1,T2,T3
KeyUpdateKmac - 0 Covered T1,T2,T3
KeyUpdateWipe - - Covered T41,T35,T6
default - - Covered T1,T2,T3


LineNo. Expression -1-: 472 case (state_q) -2-: 486 if (inv_state) -3-: 488 if (advance_sel) -4-: 498 if (prng_reseed_ack_i) -5-: 511 if ((int'(cnt) == (EntropyRounds - 1))) -6-: 521 (en_i) ? -7-: 531 (advance_sel) ? -8-: 534 if (((!en_i) || inv_state)) -9-: 536 if (dis_state) -10-: 538 if (adv_state) -11-: 550 (disable_sel) ? -12-: 550 (advance_sel) ? -13-: 553 if (((!en_i) || inv_state)) -14-: 555 if (dis_state) -15-: 557 if (adv_state) -16-: 569 (disable_sel) ? -17-: 569 (advance_sel) ? -18-: 572 if (((!en_i) || inv_state)) -19-: 574 if (dis_state) -20-: 576 if (adv_state) -21-: 589 ((disable_sel | advance_sel)) ? -22-: 591 if (((!en_i) || inv_state)) -23-: 593 if ((adv_state || dis_state)) -24-: 615 if ((!op_start_i)) -25-: 630 if (((!en_i) || inv_state))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25-StatusTests
StCtrlReset 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T35,T31,T12
StCtrlReset 0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlReset 0 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlEntropyReseed - - 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlEntropyReseed - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlRandom - - - 1 - - - - - - - - - - - - - - - - - - - - Unreachable T1,T2,T3
StCtrlRandom - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlRootKey - - - - 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlRootKey - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T51,T52,T53
StCtrlInit - - - - - 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlInit - - - - - 0 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlInit - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T41,T6,T50
StCtrlInit - - - - - - 0 1 - - - - - - - - - - - - - - - - Covered T76,T77,T78
StCtrlInit - - - - - - 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlInit - - - - - - 0 0 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlCreatorRootKey - - - - - - - - - 1 - - - - - - - - - - - - - - Covered T54,T55,T56
StCtrlCreatorRootKey - - - - - - - - - 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlCreatorRootKey - - - - - - - - - 0 0 - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlCreatorRootKey - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T36,T40,T57
StCtrlCreatorRootKey - - - - - - - - - - - 0 1 - - - - - - - - - - - Covered T54,T55,T56
StCtrlCreatorRootKey - - - - - - - - - - - 0 0 1 - - - - - - - - - - Covered T1,T2,T3
StCtrlCreatorRootKey - - - - - - - - - - - 0 0 0 - - - - - - - - - - Covered T1,T2,T3
StCtrlOwnerIntKey - - - - - - - - - - - - - - 1 - - - - - - - - - Covered T6,T50,T60
StCtrlOwnerIntKey - - - - - - - - - - - - - - 0 1 - - - - - - - - Covered T1,T2,T3
StCtrlOwnerIntKey - - - - - - - - - - - - - - 0 0 - - - - - - - - Covered T1,T2,T3
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 1 - - - - - - - Covered T42,T37,T43
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 1 - - - - - - Covered T6,T50,T60
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 0 1 - - - - - Covered T1,T2,T3
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 0 0 - - - - - Covered T1,T2,T3
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - 1 - - - - Covered T1,T2,T3
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - 0 - - - - Covered T1,T2,T3
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T46,T67,T65
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 0 1 - - Covered T1,T2,T3
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 0 0 - - Covered T1,T2,T3
StCtrlWipe - - - - - - - - - - - - - - - - - - - - - - 1 - Covered T41,T35,T6
StCtrlWipe - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T6,T36,T7
StCtrlDisabled - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T72,T33,T73
StCtrlDisabled - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T1,T2,T3
StCtrlInvalid - - - - - - - - - - - - - - - - - - - - - - - - Covered T41,T35,T6
default - - - - - - - - - - - - - - - - - - - - - - - - Covered T12,T13,T14


LineNo. Expression -1-: 655 if ((!rst_ni)) -2-: 657 if (update_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T41,T35,T6


LineNo. Expression -1-: 666 case (state_q)

Branches:
-1-StatusTests
StCtrlReset StCtrlEntropyReseed StCtrlRandom Covered T1,T2,T3
StCtrlRootKey StCtrlInit Covered T1,T2,T3
StCtrlCreatorRootKey Covered T1,T2,T3
StCtrlOwnerIntKey Covered T1,T2,T3
StCtrlOwnerKey Covered T1,T2,T3
StCtrlDisabled Covered T1,T2,T3
StCtrlWipe Covered T41,T35,T6
StCtrlInvalid Covered T41,T35,T6
default Covered T12,T13,T14


LineNo. Expression -1-: 700 if (op_done_o) -2-: 704 ((|{error_o, fault_o})) ? -3-: 705 if (op_start_i)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 782 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 869 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keymgr_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 10 90.91
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 10 90.91




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntZero_A 34439256 29244 0 0
DataEnDis_A 34142527 28570 0 0
DataEn_A 34142527 8138067 0 0
GeneralLegalCommands_A 35202661 36370 0 0
InitLegalCommands_A 35202661 1492488 0 0
LoadKey_A 34982223 28139943 0 0
OwnerLegalCommands_A 35202661 2396536 0 0
SameErrCnt_A 895 895 0 0
SecCmCFILinear_A 35202661 0 0 4807
StageDisableSel_A 35202661 882994 0 0
u_state_regs_A 35202661 35027933 0 0


CntZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34439256 29244 0 0
T1 4738 16 0 0
T2 4273 18 0 0
T3 25784 20 0 0
T4 25089 32 0 0
T5 3746 19 0 0
T15 7266 16 0 0
T16 6117 16 0 0
T17 3658 18 0 0
T18 146230 30 0 0
T19 9753 29 0 0

DataEnDis_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34142527 28570 0 0
T1 4738 16 0 0
T2 4273 18 0 0
T3 25784 20 0 0
T4 25089 32 0 0
T5 3746 19 0 0
T15 7266 16 0 0
T16 6117 16 0 0
T17 3658 18 0 0
T18 146230 30 0 0
T19 9753 29 0 0

DataEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34142527 8138067 0 0
T1 4738 112 0 0
T2 4273 910 0 0
T3 25784 5140 0 0
T4 25089 4881 0 0
T5 3746 109 0 0
T15 7266 832 0 0
T16 6117 530 0 0
T17 3658 572 0 0
T18 146230 38291 0 0
T19 9753 2609 0 0

GeneralLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 36370 0 0
T6 355346 2356 0 0
T7 339872 0 0 0
T36 4541 0 0 0
T40 5453 0 0 0
T48 8347 0 0 0
T50 92975 0 0 0
T56 0 251 0 0
T60 109752 496 0 0
T79 0 170 0 0
T80 0 1413 0 0
T81 0 588 0 0
T82 0 1309 0 0
T83 0 58 0 0
T84 0 199 0 0
T85 0 179 0 0
T86 13471 0 0 0
T87 92661 0 0 0
T88 15252 0 0 0

InitLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 1492488 0 0
T1 4738 16 0 0
T2 4273 251 0 0
T3 25784 538 0 0
T4 25089 501 0 0
T5 3746 23 0 0
T15 7266 133 0 0
T16 6117 110 0 0
T17 3658 95 0 0
T18 146230 3163 0 0
T19 9753 684 0 0

LoadKey_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34982223 28139943 0 0
T1 4738 534 0 0
T2 4273 1565 0 0
T3 25784 21977 0 0
T4 25089 15157 0 0
T5 3746 537 0 0
T15 7266 3098 0 0
T16 6117 1621 0 0
T17 3658 1818 0 0
T18 146230 136922 0 0
T19 9753 5985 0 0

OwnerLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 2396536 0 0
T1 4738 58 0 0
T2 4273 0 0 0
T3 25784 2908 0 0
T4 25089 1209 0 0
T5 3746 58 0 0
T15 7266 382 0 0
T16 6117 138 0 0
T17 3658 115 0 0
T18 146230 14084 0 0
T19 9753 499 0 0
T30 0 7351 0 0

SameErrCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SecCmCFILinear_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 0 0 4807

StageDisableSel_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 882994 0 0
T1 4738 52 0 0
T2 4273 459 0 0
T3 25784 87 0 0
T4 25089 129 0 0
T5 3746 3 0 0
T15 7266 38 0 0
T16 6117 15 0 0
T17 3658 178 0 0
T18 146230 25 0 0
T19 9753 1026 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 35027933 0 0
T1 4738 4675 0 0
T2 4273 4203 0 0
T3 25784 25722 0 0
T4 25089 25036 0 0
T5 3746 3662 0 0
T15 7266 7198 0 0
T16 6117 6038 0 0
T17 3658 3560 0 0
T18 146230 146138 0 0
T19 9753 9662 0 0