Unified Coverage Report :: Module :: prim_flop_2sync

Module : prim_flop_2sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync	100.00	100.00				100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
tb.dut.u_ctrl.u_key_valid_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_lc_keymgr_en_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33			100.00	100.00	u_prim_sync_reqack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33			100.00	100.00	u_prim_sync_reqack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_ctrl.u_key_valid_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.09		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync	100.00	100.00				100.00

Line Coverage for Module : prim_flop_2sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1

---

Branch Coverage for Module : prim_flop_2sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	39	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1

---

Branch Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	39	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1

---

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	39	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1

---

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	39	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1

---

Branch Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	39	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv' or '../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3