KEYMGR_DPE Simulation Results

Monday February 05 2024 20:02:51 UTC

GitHub Revision: 0d61ea543e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 226220803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_dpe_smoke 6.869m 56.672ms 47 50 94.00
V1 csr_hw_reset keymgr_dpe_csr_hw_reset 1.330s 57.833us 5 5 100.00
V1 csr_rw keymgr_dpe_csr_rw 1.340s 97.862us 20 20 100.00
V1 csr_bit_bash keymgr_dpe_csr_bit_bash 20.110s 734.381us 5 5 100.00
V1 csr_aliasing keymgr_dpe_csr_aliasing 8.780s 865.856us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_dpe_csr_mem_rw_with_rand_reset 2.080s 28.294us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_dpe_csr_rw 1.340s 97.862us 20 20 100.00
keymgr_dpe_csr_aliasing 8.780s 865.856us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 intr_test keymgr_dpe_intr_test 0.900s 127.960us 50 50 100.00
V2 alert_test keymgr_dpe_alert_test 1.030s 20.687us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_dpe_tl_errors 6.210s 166.050us 20 20 100.00
V2 tl_d_illegal_access keymgr_dpe_tl_errors 6.210s 166.050us 20 20 100.00
V2 tl_d_outstanding_access keymgr_dpe_csr_hw_reset 1.330s 57.833us 5 5 100.00
keymgr_dpe_csr_rw 1.340s 97.862us 20 20 100.00
keymgr_dpe_csr_aliasing 8.780s 865.856us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.260s 96.805us 20 20 100.00
V2 tl_d_partial_access keymgr_dpe_csr_hw_reset 1.330s 57.833us 5 5 100.00
keymgr_dpe_csr_rw 1.340s 97.862us 20 20 100.00
keymgr_dpe_csr_aliasing 8.780s 865.856us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.260s 96.805us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S tl_intg_err keymgr_dpe_sec_cm 20.890s 702.406us 5 5 100.00
keymgr_dpe_tl_intg_err 8.200s 1.342ms 20 20 100.00
V2S shadow_reg_update_error keymgr_dpe_shadow_reg_errors 4.600s 212.576us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_dpe_shadow_reg_errors 4.600s 212.576us 20 20 100.00
V2S shadow_reg_storage_error keymgr_dpe_shadow_reg_errors 4.600s 212.576us 20 20 100.00
V2S shadowed_reset_glitch keymgr_dpe_shadow_reg_errors 4.600s 212.576us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_dpe_shadow_reg_errors_with_csr_rw 9.340s 1.067ms 20 20 100.00
V2S prim_count_check keymgr_dpe_sec_cm 20.890s 702.406us 5 5 100.00
V2S prim_fsm_check keymgr_dpe_sec_cm 20.890s 702.406us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset keymgr_dpe_stress_all_with_rand_reset 0.700s 3.066us 0 50 0.00
V3 TOTAL 0 50 0.00
Unmapped tests keymgr_dpe_stress_all 0.680s 0 50 0.00
TOTAL 307 410 74.88

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 5 83.33
V2 4 4 4 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.26 97.70 90.62 57.52 76.92 94.94 98.34 17.75

Failure Buckets

Past Results