KEYMGR_DPE Simulation Results

Thursday February 08 2024 20:05:57 UTC

GitHub Revision: `5470b05185`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2313004684

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	1.959m	15.520ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.400s	50.291us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.320s	82.952us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	19.550s	9.160ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.100s	246.642us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.820s	32.876us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.320s	82.952us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.100s	246.642us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	0.880s	10.611us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	0.950s	15.936us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.980s	323.503us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.980s	323.503us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.400s	50.291us	5	5	100.00
		keymgr_dpe_csr_rw	1.320s	82.952us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.100s	246.642us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.840s	226.624us	19	20	95.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.400s	50.291us	5	5	100.00
		keymgr_dpe_csr_rw	1.320s	82.952us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.100s	246.642us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.840s	226.624us	19	20	95.00
V2		TOTAL			139	140	99.29
V2S	tl_intg_err	keymgr_dpe_sec_cm	19.790s	842.369us	5	5	100.00
		keymgr_dpe_tl_intg_err	8.470s	266.775us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.370s	192.389us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.370s	192.389us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.370s	192.389us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.370s	192.389us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	8.600s	311.184us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	19.790s	842.369us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	19.790s	842.369us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset	0.720s	1.966us	0	50	0.00
V3		TOTAL			0	50	0.00
	Unmapped tests	keymgr_dpe_stress_all	0.660s		0	50	0.00
		TOTAL			308	410	75.12

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	5	83.33
V2	4	4	3	75.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.27	97.70	90.62	57.52	76.92	94.94	98.34	17.85

Failure Buckets

UVM_WARNING [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory. has 100 failures:

Test keymgr_dpe_stress_all_with_rand_reset has 50 failures.

0.keymgr_dpe_stress_all_with_rand_reset.3322033462
Line 253, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/0.keymgr_dpe_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @   1600640 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @   1600640 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.keymgr_dpe_stress_all_with_rand_reset.3090397486
Line 253, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/1.keymgr_dpe_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @   9382395 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @   9382395 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

Test keymgr_dpe_stress_all has 50 failures.

0.keymgr_dpe_stress_all.4011255250
Line 249, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/0.keymgr_dpe_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.keymgr_dpe_stress_all.2271426842
Line 249, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/1.keymgr_dpe_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:

Test keymgr_dpe_smoke has 1 failures.

5.keymgr_dpe_smoke.2364177086
Line 2435, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/5.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 2192849725 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hfc96d72191f8bb12d053300a0815c5f73aca72363f69913acd44620faf7c5e4d1320d37b8d2933b35c7c821fa221a406782701b3db8347617cb198cde2cbb09a vs. act 'h0
  UVM_INFO @ 2192849725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:248) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test keymgr_dpe_same_csr_outstanding has 1 failures.
  - 9.keymgr_dpe_same_csr_outstanding.4068780249
    Line 254, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/9.keymgr_dpe_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @   1471557 ps: (cip_base_vseq.sv:248) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xb047bfd0 read out mismatch
  UVM_INFO @   1471557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```