KEYMGR_DPE Simulation Results

Saturday April 20 2024 19:02:14 UTC

GitHub Revision: `d4aa482ae5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4197540902

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.745m	10.177ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.270s	27.927us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.440s	27.632us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	10.360s	675.748us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	10.290s	1.077ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.690s	67.593us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.440s	27.632us	20	20	100.00
		keymgr_dpe_csr_aliasing	10.290s	1.077ms	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.030s	21.144us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.060s	21.691us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.670s	156.699us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.670s	156.699us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.270s	27.927us	5	5	100.00
		keymgr_dpe_csr_rw	1.440s	27.632us	20	20	100.00
		keymgr_dpe_csr_aliasing	10.290s	1.077ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.050s	294.720us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.270s	27.927us	5	5	100.00
		keymgr_dpe_csr_rw	1.440s	27.632us	20	20	100.00
		keymgr_dpe_csr_aliasing	10.290s	1.077ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.050s	294.720us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	19.520s	2.495ms	5	5	100.00
		keymgr_dpe_tl_intg_err	10.020s	901.934us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.950s	229.605us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.950s	229.605us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.950s	229.605us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.950s	229.605us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	9.460s	1.167ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	19.520s	2.495ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	19.520s	2.495ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			309	310	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.28	97.70	90.76	57.52	76.92	94.94	98.34	17.78

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act *

has 1 failures:

Test keymgr_dpe_smoke has 1 failures.

35.keymgr_dpe_smoke.1946996619
Line 2099, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/35.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 315514318 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'he163216d23a878e158bfa5dde3ca50047a2547390aaec371de91f8017be9422800a4b9adc5bfea764201e8e059ca0cae0b56cef08b609df8f8c6f1c439dc3e4f vs. act 'h0
  UVM_INFO @ 315514318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---