ADC_CTRL Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.080s	5.816ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.600s	1.215ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.070s	569.543us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.661m	51.871ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.190s	665.747us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	512.512us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.070s	569.543us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	665.747us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.800m	495.009ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.488m	492.349ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.524m	484.807ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.700m	495.327ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.535m	521.574ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.060m	484.803ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.586m	509.778ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.017m	497.201ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.640s	5.470ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.889m	46.829ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.478m	128.751ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.421m	379.831ms	40	50	80.00
V2	alert_test	adc_ctrl_alert_test	1.770s	503.000us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	502.769us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.070s	597.844us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.070s	597.844us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.600s	1.215ms	5	5	100.00
		adc_ctrl_csr_rw	2.070s	569.543us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	665.747us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.170s	5.407ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.600s	1.215ms	5	5	100.00
		adc_ctrl_csr_rw	2.070s	569.543us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	665.747us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.170s	5.407ms	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	tl_intg_err	adc_ctrl_sec_cm	19.230s	8.216ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.190s	8.066ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.190s	8.066ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.424m	365.406ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			884	920	96.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.47	99.01	95.70	100.00	100.00	98.18	98.64	90.75

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 26 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 26 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.3256869397
    Line 379, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 23560969101 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 23560969101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.adc_ctrl_stress_all_with_rand_reset.1282393598
    Line 445, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 191359638450 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 191359638450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 24 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 10 failures:

Test adc_ctrl_stress_all has 10 failures.

7.adc_ctrl_stress_all.4248825840
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 330976928034 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 330976928034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.adc_ctrl_stress_all.3424711590
Line 439, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 521823286513 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 521823286513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.