ADC_CTRL Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.990s	5.730ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.020s	1.014ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.090s	556.208us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	59.730s	52.404ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.980s	772.390us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.110s	554.905us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.090s	556.208us	20	20	100.00
		adc_ctrl_csr_aliasing	2.980s	772.390us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.012m	497.762ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.773m	481.528ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.432m	485.429ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.740m	501.042ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.537m	492.404ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.466m	494.371ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.631m	484.659ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.461m	486.272ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.790s	5.754ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.883m	44.817ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.835m	125.028ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.483m	577.201ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.790s	493.715us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.790s	519.582us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.570s	557.540us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.570s	557.540us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.020s	1.014ms	5	5	100.00
		adc_ctrl_csr_rw	2.090s	556.208us	20	20	100.00
		adc_ctrl_csr_aliasing	2.980s	772.390us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.000s	5.082ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.020s	1.014ms	5	5	100.00
		adc_ctrl_csr_rw	2.090s	556.208us	20	20	100.00
		adc_ctrl_csr_aliasing	2.980s	772.390us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.000s	5.082ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	17.650s	7.867ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.430s	8.366ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.430s	8.366ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.850m	673.213ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			913	920	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	98.98	95.70	100.00	100.00	98.18	98.64	91.37

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
  • Test adc_ctrl_stress_all has 6 failures.

    • 2.adc_ctrl_stress_all.33802137776304606132743146473536176502445324808047723209839152348787079836258
      Line 388, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 483513269857 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 483513269857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.adc_ctrl_stress_all.49340532197112863806715366881101021176671859195337883810754706601050551086513
      Line 399, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 529596548724 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 529596548724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (* [*] vs * [*]) has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.adc_ctrl_stress_all_with_rand_reset.66703760978825026102648236294269008067017929305341585211983492322916081687478
      Line 367, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 84176759335 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 84176759335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2023.12.28_03.08.47
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• 2023.12.21_00.00.36
• 2023.12.18_22.13.27
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