| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.67 | 99.07 | 96.67 | 100.00 | 100.00 | 98.82 | 98.33 | 90.79 |
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.6739164 | Oct 09 07:11:12 AM UTC 24 | Oct 09 07:11:17 AM UTC 24 | 701483172 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1303435360 | Oct 09 07:11:14 AM UTC 24 | Oct 09 07:11:17 AM UTC 24 | 481022984 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3156232798 | Oct 09 07:11:14 AM UTC 24 | Oct 09 07:11:18 AM UTC 24 | 858156253 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.901484714 | Oct 09 07:11:16 AM UTC 24 | Oct 09 07:11:20 AM UTC 24 | 831791529 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4128375769 | Oct 09 07:11:18 AM UTC 24 | Oct 09 07:11:21 AM UTC 24 | 396722515 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2474631873 | Oct 09 07:11:19 AM UTC 24 | Oct 09 07:11:22 AM UTC 24 | 349463992 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2397367936 | Oct 09 07:11:19 AM UTC 24 | Oct 09 07:11:22 AM UTC 24 | 1829580057 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2323205515 | Oct 09 07:10:50 AM UTC 24 | Oct 09 07:11:23 AM UTC 24 | 8228171539 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2920722221 | Oct 09 07:11:09 AM UTC 24 | Oct 09 07:11:23 AM UTC 24 | 8232242248 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1713650528 | Oct 09 07:11:19 AM UTC 24 | Oct 09 07:11:25 AM UTC 24 | 1223576194 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1948368010 | Oct 09 07:11:41 AM UTC 24 | Oct 09 07:12:10 AM UTC 24 | 8419108031 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1150465972 | Oct 09 07:11:21 AM UTC 24 | Oct 09 07:11:26 AM UTC 24 | 729773076 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1556460405 | Oct 09 07:11:24 AM UTC 24 | Oct 09 07:11:27 AM UTC 24 | 409801063 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2541608467 | Oct 09 07:11:23 AM UTC 24 | Oct 09 07:11:27 AM UTC 24 | 451676395 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3541173752 | Oct 09 07:11:23 AM UTC 24 | Oct 09 07:11:29 AM UTC 24 | 818547486 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4258312711 | Oct 09 07:11:14 AM UTC 24 | Oct 09 07:11:29 AM UTC 24 | 8882842582 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1109378026 | Oct 09 07:11:26 AM UTC 24 | Oct 09 07:11:31 AM UTC 24 | 470014119 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1172337896 | Oct 09 07:11:26 AM UTC 24 | Oct 09 07:11:32 AM UTC 24 | 2271500861 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3285067516 | Oct 09 07:11:27 AM UTC 24 | Oct 09 07:11:34 AM UTC 24 | 475066652 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.824657739 | Oct 09 07:11:32 AM UTC 24 | Oct 09 07:11:35 AM UTC 24 | 338185094 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.680464142 | Oct 09 07:11:27 AM UTC 24 | Oct 09 07:11:35 AM UTC 24 | 468109778 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.4237810024 | Oct 09 07:11:32 AM UTC 24 | Oct 09 07:11:35 AM UTC 24 | 297712614 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2292872747 | Oct 09 07:11:19 AM UTC 24 | Oct 09 07:11:37 AM UTC 24 | 21322316546 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.281310774 | Oct 09 07:11:32 AM UTC 24 | Oct 09 07:11:38 AM UTC 24 | 1488927027 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1560087677 | Oct 09 07:11:34 AM UTC 24 | Oct 09 07:11:39 AM UTC 24 | 1303864306 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.770539387 | Oct 09 07:12:12 AM UTC 24 | Oct 09 07:12:15 AM UTC 24 | 493698352 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.1000333334 | Oct 09 07:11:36 AM UTC 24 | Oct 09 07:11:39 AM UTC 24 | 346883677 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3881536743 | Oct 09 07:11:29 AM UTC 24 | Oct 09 07:11:40 AM UTC 24 | 9049390229 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2841478835 | Oct 09 07:11:37 AM UTC 24 | Oct 09 07:11:41 AM UTC 24 | 484773583 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.469583525 | Oct 09 07:11:36 AM UTC 24 | Oct 09 07:11:41 AM UTC 24 | 540556777 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1060825379 | Oct 09 07:11:36 AM UTC 24 | Oct 09 07:11:41 AM UTC 24 | 427272205 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.68684994 | Oct 09 07:11:39 AM UTC 24 | Oct 09 07:11:43 AM UTC 24 | 586370709 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3031657485 | Oct 09 07:11:42 AM UTC 24 | Oct 09 07:11:44 AM UTC 24 | 456665463 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3814967039 | Oct 09 07:11:39 AM UTC 24 | Oct 09 07:11:44 AM UTC 24 | 525544393 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.989362185 | Oct 09 07:11:35 AM UTC 24 | Oct 09 07:11:44 AM UTC 24 | 4381406646 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4057589183 | Oct 09 07:11:42 AM UTC 24 | Oct 09 07:11:46 AM UTC 24 | 443389494 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3199260120 | Oct 09 07:11:44 AM UTC 24 | Oct 09 07:11:47 AM UTC 24 | 492164392 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.757638060 | Oct 09 07:11:45 AM UTC 24 | Oct 09 07:11:48 AM UTC 24 | 322653468 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3841241745 | Oct 09 07:11:47 AM UTC 24 | Oct 09 07:11:50 AM UTC 24 | 473964885 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3552243719 | Oct 09 07:11:45 AM UTC 24 | Oct 09 07:11:50 AM UTC 24 | 307367349 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4216917477 | Oct 09 07:11:22 AM UTC 24 | Oct 09 07:11:51 AM UTC 24 | 8315451875 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.867745687 | Oct 09 07:11:49 AM UTC 24 | Oct 09 07:11:54 AM UTC 24 | 490973573 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.210725421 | Oct 09 07:11:11 AM UTC 24 | Oct 09 07:11:55 AM UTC 24 | 21106444466 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2872573974 | Oct 09 07:11:50 AM UTC 24 | Oct 09 07:11:55 AM UTC 24 | 499189249 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3251842495 | Oct 09 07:11:47 AM UTC 24 | Oct 09 07:11:55 AM UTC 24 | 2072034155 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2195630074 | Oct 09 07:11:52 AM UTC 24 | Oct 09 07:11:55 AM UTC 24 | 340898220 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.229195409 | Oct 09 07:11:36 AM UTC 24 | Oct 09 07:11:58 AM UTC 24 | 3915949924 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.379453004 | Oct 09 07:11:45 AM UTC 24 | Oct 09 07:11:58 AM UTC 24 | 8753148095 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2163785196 | Oct 09 07:11:56 AM UTC 24 | Oct 09 07:11:58 AM UTC 24 | 605370931 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.259658918 | Oct 09 07:11:39 AM UTC 24 | Oct 09 07:11:59 AM UTC 24 | 4693904055 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.823451806 | Oct 09 07:11:54 AM UTC 24 | Oct 09 07:11:59 AM UTC 24 | 472456348 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4010494744 | Oct 09 07:11:56 AM UTC 24 | Oct 09 07:12:00 AM UTC 24 | 948952460 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.1066231205 | Oct 09 07:11:59 AM UTC 24 | Oct 09 07:12:01 AM UTC 24 | 473079594 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2013306687 | Oct 09 07:11:59 AM UTC 24 | Oct 09 07:12:02 AM UTC 24 | 431306204 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3695929525 | Oct 09 07:12:00 AM UTC 24 | Oct 09 07:12:02 AM UTC 24 | 699085785 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3659307120 | Oct 09 07:11:59 AM UTC 24 | Oct 09 07:12:03 AM UTC 24 | 2701436656 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.725992952 | Oct 09 07:11:42 AM UTC 24 | Oct 09 07:12:04 AM UTC 24 | 4289486896 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2027257000 | Oct 09 07:11:51 AM UTC 24 | Oct 09 07:12:04 AM UTC 24 | 4664386945 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1134726933 | Oct 09 07:11:56 AM UTC 24 | Oct 09 07:12:05 AM UTC 24 | 4165785921 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3765503443 | Oct 09 07:12:06 AM UTC 24 | Oct 09 07:12:08 AM UTC 24 | 463181495 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3077093231 | Oct 09 07:12:02 AM UTC 24 | Oct 09 07:12:05 AM UTC 24 | 485722592 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2101495465 | Oct 09 07:12:03 AM UTC 24 | Oct 09 07:12:06 AM UTC 24 | 588696043 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2174385759 | Oct 09 07:12:00 AM UTC 24 | Oct 09 07:12:07 AM UTC 24 | 552672747 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3978639276 | Oct 09 07:12:05 AM UTC 24 | Oct 09 07:12:07 AM UTC 24 | 310690346 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1946285199 | Oct 09 07:12:03 AM UTC 24 | Oct 09 07:12:08 AM UTC 24 | 455798747 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.631258374 | Oct 09 07:12:06 AM UTC 24 | Oct 09 07:12:09 AM UTC 24 | 654409742 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2481854290 | Oct 09 07:12:03 AM UTC 24 | Oct 09 07:12:10 AM UTC 24 | 2283315060 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2683351156 | Oct 09 07:12:04 AM UTC 24 | Oct 09 07:12:11 AM UTC 24 | 559242064 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2939805891 | Oct 09 07:12:07 AM UTC 24 | Oct 09 07:12:11 AM UTC 24 | 687345916 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3976141042 | Oct 09 07:12:08 AM UTC 24 | Oct 09 07:12:11 AM UTC 24 | 489647228 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2582942133 | Oct 09 07:12:09 AM UTC 24 | Oct 09 07:12:13 AM UTC 24 | 454510391 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3857576363 | Oct 09 07:12:01 AM UTC 24 | Oct 09 07:12:14 AM UTC 24 | 8878143130 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.30592847 | Oct 09 07:12:10 AM UTC 24 | Oct 09 07:12:14 AM UTC 24 | 509730858 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1994007379 | Oct 09 07:12:12 AM UTC 24 | Oct 09 07:12:15 AM UTC 24 | 531372327 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1151220579 | Oct 09 07:12:07 AM UTC 24 | Oct 09 07:12:17 AM UTC 24 | 8726788881 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2348158309 | Oct 09 07:12:12 AM UTC 24 | Oct 09 07:12:18 AM UTC 24 | 473439633 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1744931095 | Oct 09 07:12:14 AM UTC 24 | Oct 09 07:12:19 AM UTC 24 | 363154528 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2668593830 | Oct 09 07:12:17 AM UTC 24 | Oct 09 07:12:20 AM UTC 24 | 314732641 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2358763549 | Oct 09 07:12:17 AM UTC 24 | Oct 09 07:12:20 AM UTC 24 | 583592992 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.786369765 | Oct 09 07:12:15 AM UTC 24 | Oct 09 07:12:20 AM UTC 24 | 374756347 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3845078050 | Oct 09 07:12:12 AM UTC 24 | Oct 09 07:12:20 AM UTC 24 | 4669004021 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4148634870 | Oct 09 07:12:09 AM UTC 24 | Oct 09 07:12:21 AM UTC 24 | 2268663838 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2302990322 | Oct 09 07:12:19 AM UTC 24 | Oct 09 07:12:22 AM UTC 24 | 416939239 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1395068077 | Oct 09 07:12:49 AM UTC 24 | Oct 09 07:12:51 AM UTC 24 | 380773451 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3586244714 | Oct 09 07:12:18 AM UTC 24 | Oct 09 07:12:23 AM UTC 24 | 2464179401 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3119207006 | Oct 09 07:12:20 AM UTC 24 | Oct 09 07:12:24 AM UTC 24 | 514313120 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3684148777 | Oct 09 07:12:20 AM UTC 24 | Oct 09 07:12:25 AM UTC 24 | 332914736 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.781596811 | Oct 09 07:12:22 AM UTC 24 | Oct 09 07:12:25 AM UTC 24 | 603140482 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.346861112 | Oct 09 07:12:21 AM UTC 24 | Oct 09 07:12:26 AM UTC 24 | 405652694 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3653931693 | Oct 09 07:11:33 AM UTC 24 | Oct 09 07:12:26 AM UTC 24 | 11497693763 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2740563476 | Oct 09 07:11:56 AM UTC 24 | Oct 09 07:12:27 AM UTC 24 | 5116562212 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2438166262 | Oct 09 07:12:25 AM UTC 24 | Oct 09 07:12:27 AM UTC 24 | 282501459 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.940608450 | Oct 09 07:12:24 AM UTC 24 | Oct 09 07:12:28 AM UTC 24 | 800171109 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.892233638 | Oct 09 07:12:12 AM UTC 24 | Oct 09 07:12:28 AM UTC 24 | 8660527387 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.907688771 | Oct 09 07:12:26 AM UTC 24 | Oct 09 07:12:28 AM UTC 24 | 525316927 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.281887324 | Oct 09 07:12:26 AM UTC 24 | Oct 09 07:12:29 AM UTC 24 | 478707113 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.714467898 | Oct 09 07:12:27 AM UTC 24 | Oct 09 07:12:30 AM UTC 24 | 289972873 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.765527541 | Oct 09 07:12:26 AM UTC 24 | Oct 09 07:12:30 AM UTC 24 | 2536979571 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3922546693 | Oct 09 07:12:06 AM UTC 24 | Oct 09 07:12:30 AM UTC 24 | 3677374628 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3129094434 | Oct 09 07:12:28 AM UTC 24 | Oct 09 07:12:31 AM UTC 24 | 492837487 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.869023003 | Oct 09 07:12:21 AM UTC 24 | Oct 09 07:12:31 AM UTC 24 | 2832613947 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1656747643 | Oct 09 07:12:27 AM UTC 24 | Oct 09 07:12:32 AM UTC 24 | 538288477 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2175186632 | Oct 09 07:12:04 AM UTC 24 | Oct 09 07:12:32 AM UTC 24 | 8672618026 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1482658414 | Oct 09 07:12:31 AM UTC 24 | Oct 09 07:12:33 AM UTC 24 | 401124179 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3333136029 | Oct 09 07:12:29 AM UTC 24 | Oct 09 07:12:33 AM UTC 24 | 394779244 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2845585027 | Oct 09 07:12:31 AM UTC 24 | Oct 09 07:12:33 AM UTC 24 | 551910340 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1753461189 | Oct 09 07:12:29 AM UTC 24 | Oct 09 07:12:33 AM UTC 24 | 500767621 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2054832678 | Oct 09 07:12:32 AM UTC 24 | Oct 09 07:12:35 AM UTC 24 | 353915294 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.3894545874 | Oct 09 07:12:33 AM UTC 24 | Oct 09 07:12:36 AM UTC 24 | 366038976 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2292319343 | Oct 09 07:12:33 AM UTC 24 | Oct 09 07:12:36 AM UTC 24 | 505744120 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3596691834 | Oct 09 07:12:32 AM UTC 24 | Oct 09 07:12:36 AM UTC 24 | 378814494 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2065145402 | Oct 09 07:12:34 AM UTC 24 | Oct 09 07:12:37 AM UTC 24 | 498630880 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1268929749 | Oct 09 07:12:34 AM UTC 24 | Oct 09 07:12:37 AM UTC 24 | 510066081 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3974742615 | Oct 09 07:12:35 AM UTC 24 | Oct 09 07:12:39 AM UTC 24 | 306767110 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1325621538 | Oct 09 07:12:36 AM UTC 24 | Oct 09 07:12:39 AM UTC 24 | 514730455 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1729060278 | Oct 09 07:12:34 AM UTC 24 | Oct 09 07:12:39 AM UTC 24 | 539082541 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.913972132 | Oct 09 07:12:36 AM UTC 24 | Oct 09 07:12:40 AM UTC 24 | 424457826 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.205117815 | Oct 09 07:12:37 AM UTC 24 | Oct 09 07:12:40 AM UTC 24 | 537587157 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2342303138 | Oct 09 07:12:38 AM UTC 24 | Oct 09 07:12:41 AM UTC 24 | 295586145 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3484061248 | Oct 09 07:12:36 AM UTC 24 | Oct 09 07:12:41 AM UTC 24 | 512222196 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1002861711 | Oct 09 07:12:40 AM UTC 24 | Oct 09 07:12:42 AM UTC 24 | 337033949 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2288735602 | Oct 09 07:12:40 AM UTC 24 | Oct 09 07:12:43 AM UTC 24 | 311358542 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.2123944782 | Oct 09 07:12:41 AM UTC 24 | Oct 09 07:12:43 AM UTC 24 | 396465046 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3559265430 | Oct 09 07:12:41 AM UTC 24 | Oct 09 07:12:43 AM UTC 24 | 335711448 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2376746464 | Oct 09 07:12:40 AM UTC 24 | Oct 09 07:12:44 AM UTC 24 | 481738169 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.941176529 | Oct 09 07:12:42 AM UTC 24 | Oct 09 07:12:44 AM UTC 24 | 404275412 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3420301612 | Oct 09 07:12:34 AM UTC 24 | Oct 09 07:12:44 AM UTC 24 | 2080210248 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2044447128 | Oct 09 07:12:42 AM UTC 24 | Oct 09 07:12:45 AM UTC 24 | 423163885 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.877936333 | Oct 09 07:12:20 AM UTC 24 | Oct 09 07:12:45 AM UTC 24 | 8404057430 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2291770443 | Oct 09 07:12:42 AM UTC 24 | Oct 09 07:12:45 AM UTC 24 | 448863172 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2988634545 | Oct 09 07:12:44 AM UTC 24 | Oct 09 07:12:47 AM UTC 24 | 372434452 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1579237536 | Oct 09 07:12:24 AM UTC 24 | Oct 09 07:12:51 AM UTC 24 | 8363204279 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.793338067 | Oct 09 07:12:44 AM UTC 24 | Oct 09 07:12:47 AM UTC 24 | 408379073 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2814643930 | Oct 09 07:12:44 AM UTC 24 | Oct 09 07:12:47 AM UTC 24 | 525289684 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.817957023 | Oct 09 07:12:44 AM UTC 24 | Oct 09 07:12:48 AM UTC 24 | 378438530 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.59158521 | Oct 09 07:12:45 AM UTC 24 | Oct 09 07:12:48 AM UTC 24 | 502058268 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3520176913 | Oct 09 07:12:32 AM UTC 24 | Oct 09 07:12:48 AM UTC 24 | 7759511106 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2236448177 | Oct 09 07:12:45 AM UTC 24 | Oct 09 07:12:48 AM UTC 24 | 327634496 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3686677245 | Oct 09 07:12:46 AM UTC 24 | Oct 09 07:12:48 AM UTC 24 | 300868149 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.928881091 | Oct 09 07:12:28 AM UTC 24 | Oct 09 07:12:49 AM UTC 24 | 4370449322 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4194281046 | Oct 09 07:12:46 AM UTC 24 | Oct 09 07:12:49 AM UTC 24 | 425211447 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2296605341 | Oct 09 07:12:45 AM UTC 24 | Oct 09 07:12:49 AM UTC 24 | 390792941 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.2769319119 | Oct 09 07:12:48 AM UTC 24 | Oct 09 07:12:51 AM UTC 24 | 428277451 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3873455351 | Oct 09 07:12:48 AM UTC 24 | Oct 09 07:12:51 AM UTC 24 | 304293431 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2247088713 | Oct 09 07:12:49 AM UTC 24 | Oct 09 07:12:52 AM UTC 24 | 524874005 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.189359853 | Oct 09 07:12:29 AM UTC 24 | Oct 09 07:12:52 AM UTC 24 | 8823024970 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1731880203 | Oct 09 07:12:49 AM UTC 24 | Oct 09 07:12:53 AM UTC 24 | 391362877 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1347999668 | Oct 09 07:12:17 AM UTC 24 | Oct 09 07:13:00 AM UTC 24 | 8277620195 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2249531494 | Oct 09 07:12:32 AM UTC 24 | Oct 09 07:13:04 AM UTC 24 | 4371067980 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2248869452 | Oct 09 07:12:27 AM UTC 24 | Oct 09 07:13:06 AM UTC 24 | 7644862445 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1399962210 | Oct 09 07:11:24 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 43545833819 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.323585182 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4129621966 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 06:07:31 AM UTC 24 |
| Finished | Oct 09 06:07:39 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=323585182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.323585182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2874480763 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 499151466131 ps |
| CPU time | 71.96 seconds |
| Started | Oct 09 06:07:36 AM UTC 24 |
| Finished | Oct 09 06:08:53 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874480763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2874480763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.225466109 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3618682795 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 06:07:16 AM UTC 24 |
| Finished | Oct 09 06:07:37 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225466109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.225466109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3668173584 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 111539537560 ps |
| CPU time | 624.71 seconds |
| Started | Oct 09 06:07:43 AM UTC 24 |
| Finished | Oct 09 06:18:14 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668173584 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.3668173584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.2013220405 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 520411027992 ps |
| CPU time | 134.22 seconds |
| Started | Oct 09 06:07:04 AM UTC 24 |
| Finished | Oct 09 06:09:55 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013220405 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.2013220405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3782461403 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11505387046 ps |
| CPU time | 24.74 seconds |
| Started | Oct 09 06:07:43 AM UTC 24 |
| Finished | Oct 09 06:08:09 AM UTC 24 |
| Peak memory | 221240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3782461403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.adc_ctrl_stress_all_with_rand_reset.3782461403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1645274117 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 574170122624 ps |
| CPU time | 392.56 seconds |
| Started | Oct 09 06:07:16 AM UTC 24 |
| Finished | Oct 09 06:14:11 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645274117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1645274117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3099284340 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 609404205782 ps |
| CPU time | 767.35 seconds |
| Started | Oct 09 06:07:06 AM UTC 24 |
| Finished | Oct 09 06:20:19 AM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099284340 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.3099284340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1690058942 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 512895752510 ps |
| CPU time | 220.09 seconds |
| Started | Oct 09 06:15:31 AM UTC 24 |
| Finished | Oct 09 06:19:14 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690058942 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1690058942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.1869932459 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 627308492239 ps |
| CPU time | 241.33 seconds |
| Started | Oct 09 06:17:18 AM UTC 24 |
| Finished | Oct 09 06:21:23 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869932459 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.1869932459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.885841714 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 556829773055 ps |
| CPU time | 633.7 seconds |
| Started | Oct 09 06:33:18 AM UTC 24 |
| Finished | Oct 09 06:43:58 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885841714 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.885841714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.382860172 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 514416250442 ps |
| CPU time | 792.01 seconds |
| Started | Oct 09 06:12:07 AM UTC 24 |
| Finished | Oct 09 06:25:28 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382860172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.382860172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3035605895 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 555879747980 ps |
| CPU time | 293.06 seconds |
| Started | Oct 09 06:07:37 AM UTC 24 |
| Finished | Oct 09 06:12:37 AM UTC 24 |
| Peak memory | 210668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035605895 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.3035605895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2488882080 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 510306128 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 07:11:08 AM UTC 24 |
| Finished | Oct 09 07:11:11 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488882080 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2488882080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3541095066 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8128568706 ps |
| CPU time | 5.07 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:30 AM UTC 24 |
| Peak memory | 242776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541095066 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3541095066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.829503654 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 521503045311 ps |
| CPU time | 134.37 seconds |
| Started | Oct 09 06:08:11 AM UTC 24 |
| Finished | Oct 09 06:10:28 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829503654 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.829503654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4062766844 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 337845967453 ps |
| CPU time | 716.6 seconds |
| Started | Oct 09 06:07:37 AM UTC 24 |
| Finished | Oct 09 06:19:42 AM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062766844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4062766844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3704139481 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 203052171453 ps |
| CPU time | 152.33 seconds |
| Started | Oct 09 06:07:04 AM UTC 24 |
| Finished | Oct 09 06:10:16 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704139481 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.3704139481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3611573015 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 552477546612 ps |
| CPU time | 415.66 seconds |
| Started | Oct 09 06:23:45 AM UTC 24 |
| Finished | Oct 09 06:30:46 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611573015 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.3611573015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.153238302 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 477563409847 ps |
| CPU time | 1081.46 seconds |
| Started | Oct 09 06:19:09 AM UTC 24 |
| Finished | Oct 09 06:37:22 AM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153238302 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.153238302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2867821058 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 497291525038 ps |
| CPU time | 200.65 seconds |
| Started | Oct 09 06:21:47 AM UTC 24 |
| Finished | Oct 09 06:25:11 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867821058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2867821058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2292872747 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 21322316546 ps |
| CPU time | 16.93 seconds |
| Started | Oct 09 07:11:19 AM UTC 24 |
| Finished | Oct 09 07:11:37 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292872747 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.2292872747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2747001903 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 497478120993 ps |
| CPU time | 321.44 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:12:53 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747001903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2747001903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2473843955 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 356935852627 ps |
| CPU time | 319.99 seconds |
| Started | Oct 09 06:14:02 AM UTC 24 |
| Finished | Oct 09 06:19:27 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473843955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2473843955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.3454649487 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 505724589808 ps |
| CPU time | 1392.77 seconds |
| Started | Oct 09 06:10:27 AM UTC 24 |
| Finished | Oct 09 06:33:54 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454649487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3454649487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1633957018 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 440900226053 ps |
| CPU time | 302.62 seconds |
| Started | Oct 09 06:35:47 AM UTC 24 |
| Finished | Oct 09 06:40:53 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633957018 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.1633957018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2089810370 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 344550657710 ps |
| CPU time | 924.75 seconds |
| Started | Oct 09 06:08:11 AM UTC 24 |
| Finished | Oct 09 06:23:45 AM UTC 24 |
| Peak memory | 213572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089810370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2089810370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2791694049 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 375399000535 ps |
| CPU time | 220.82 seconds |
| Started | Oct 09 06:19:15 AM UTC 24 |
| Finished | Oct 09 06:22:59 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791694049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2791694049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2876573338 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 554176983329 ps |
| CPU time | 1586.47 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:34:11 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876573338 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.2876573338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2323205515 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8228171539 ps |
| CPU time | 31.34 seconds |
| Started | Oct 09 07:10:50 AM UTC 24 |
| Finished | Oct 09 07:11:23 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323205515 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.2323205515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3125877030 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 380852935 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 07:11:10 AM UTC 24 |
| Finished | Oct 09 07:11:12 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125877030 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3125877030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3269800782 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 342766100364 ps |
| CPU time | 271.04 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:12:05 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269800782 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.3269800782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3426346093 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 328090534427 ps |
| CPU time | 734.74 seconds |
| Started | Oct 09 06:31:24 AM UTC 24 |
| Finished | Oct 09 06:43:47 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426346093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3426346093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.765451882 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 443266202 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:32 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765451882 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.765451882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3686412384 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 379530949536 ps |
| CPU time | 925.91 seconds |
| Started | Oct 09 06:13:23 AM UTC 24 |
| Finished | Oct 09 06:28:59 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686412384 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.3686412384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1937283040 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 327942543358 ps |
| CPU time | 252.34 seconds |
| Started | Oct 09 06:15:18 AM UTC 24 |
| Finished | Oct 09 06:19:34 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937283040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.1937283040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3572196378 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 519723864207 ps |
| CPU time | 1162.65 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:26:34 AM UTC 24 |
| Peak memory | 213616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572196378 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.3572196378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.627921697 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 503753277453 ps |
| CPU time | 1191.95 seconds |
| Started | Oct 09 06:35:32 AM UTC 24 |
| Finished | Oct 09 06:55:36 AM UTC 24 |
| Peak memory | 213572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627921697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.627921697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1662671531 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10949203983 ps |
| CPU time | 17.38 seconds |
| Started | Oct 09 06:10:49 AM UTC 24 |
| Finished | Oct 09 06:11:08 AM UTC 24 |
| Peak memory | 221376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1662671531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.adc_ctrl_stress_all_with_rand_reset.1662671531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.3812596318 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 534933951172 ps |
| CPU time | 878.55 seconds |
| Started | Oct 09 06:51:10 AM UTC 24 |
| Finished | Oct 09 07:05:59 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812596318 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.3812596318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.81668966 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 503316529192 ps |
| CPU time | 1432.66 seconds |
| Started | Oct 09 06:23:39 AM UTC 24 |
| Finished | Oct 09 06:47:46 AM UTC 24 |
| Peak memory | 213304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81668966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.81668966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1490682034 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5392983962 ps |
| CPU time | 7.52 seconds |
| Started | Oct 09 06:07:50 AM UTC 24 |
| Finished | Oct 09 06:08:02 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1490682034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.adc_ctrl_stress_all_with_rand_reset.1490682034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.4208735592 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 163587358259 ps |
| CPU time | 373.78 seconds |
| Started | Oct 09 06:22:23 AM UTC 24 |
| Finished | Oct 09 06:28:41 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208735592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4208735592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1688872113 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 101896013714 ps |
| CPU time | 429.74 seconds |
| Started | Oct 09 06:07:30 AM UTC 24 |
| Finished | Oct 09 06:14:48 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688872113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1688872113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1933046821 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 339441729816 ps |
| CPU time | 129.84 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:09:42 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933046821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1933046821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.1238080425 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4728572519412 ps |
| CPU time | 1555.54 seconds |
| Started | Oct 09 06:23:32 AM UTC 24 |
| Finished | Oct 09 06:49:42 AM UTC 24 |
| Peak memory | 223940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238080425 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.1238080425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2214846540 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 581554980511 ps |
| CPU time | 690.65 seconds |
| Started | Oct 09 07:04:01 AM UTC 24 |
| Finished | Oct 09 07:15:40 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214846540 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.2214846540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2195607542 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 489497527264 ps |
| CPU time | 474.99 seconds |
| Started | Oct 09 07:05:44 AM UTC 24 |
| Finished | Oct 09 07:13:45 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195607542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2195607542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3881536743 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9049390229 ps |
| CPU time | 7.98 seconds |
| Started | Oct 09 07:11:29 AM UTC 24 |
| Finished | Oct 09 07:11:40 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881536743 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.3881536743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.377548151 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 540010468692 ps |
| CPU time | 342.64 seconds |
| Started | Oct 09 06:31:05 AM UTC 24 |
| Finished | Oct 09 06:36:52 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377548151 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.377548151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.2396894116 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 315967552128 ps |
| CPU time | 1529.17 seconds |
| Started | Oct 09 06:39:13 AM UTC 24 |
| Finished | Oct 09 07:04:57 AM UTC 24 |
| Peak memory | 213720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396894116 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.2396894116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.2005705799 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 325994197902 ps |
| CPU time | 217.71 seconds |
| Started | Oct 09 06:47:33 AM UTC 24 |
| Finished | Oct 09 06:51:14 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005705799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2005705799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1836198113 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 352458591940 ps |
| CPU time | 878.64 seconds |
| Started | Oct 09 07:03:12 AM UTC 24 |
| Finished | Oct 09 07:18:00 AM UTC 24 |
| Peak memory | 213304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836198113 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.1836198113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.489068393 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 161958270306 ps |
| CPU time | 161.17 seconds |
| Started | Oct 09 06:30:00 AM UTC 24 |
| Finished | Oct 09 06:32:44 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489068393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.489068393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.4137223314 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 541927867459 ps |
| CPU time | 378.81 seconds |
| Started | Oct 09 06:34:23 AM UTC 24 |
| Finished | Oct 09 06:40:47 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137223314 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.4137223314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.2267587707 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 186461600751 ps |
| CPU time | 164.11 seconds |
| Started | Oct 09 06:59:21 AM UTC 24 |
| Finished | Oct 09 07:02:08 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267587707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2267587707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3704523763 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 319026725987 ps |
| CPU time | 729.93 seconds |
| Started | Oct 09 06:15:10 AM UTC 24 |
| Finished | Oct 09 06:27:28 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704523763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3704523763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3341960196 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 345505792772 ps |
| CPU time | 225.37 seconds |
| Started | Oct 09 06:15:20 AM UTC 24 |
| Finished | Oct 09 06:19:09 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341960196 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.3341960196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.9487266 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 381321882465 ps |
| CPU time | 1020.86 seconds |
| Started | Oct 09 06:24:50 AM UTC 24 |
| Finished | Oct 09 06:42:02 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9487266 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.9487266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.805145120 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 179924986527 ps |
| CPU time | 95.92 seconds |
| Started | Oct 09 06:49:49 AM UTC 24 |
| Finished | Oct 09 06:51:27 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805145120 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.805145120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1127679522 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 445395833121 ps |
| CPU time | 572.32 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:17:28 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127679522 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.1127679522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3673093350 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 352781659935 ps |
| CPU time | 314.07 seconds |
| Started | Oct 09 06:08:58 AM UTC 24 |
| Finished | Oct 09 06:14:16 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673093350 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.3673093350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2604854890 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 165392183969 ps |
| CPU time | 111.91 seconds |
| Started | Oct 09 06:14:57 AM UTC 24 |
| Finished | Oct 09 06:16:51 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604854890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2604854890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.4113450369 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 368985848404 ps |
| CPU time | 202.41 seconds |
| Started | Oct 09 06:20:19 AM UTC 24 |
| Finished | Oct 09 06:23:44 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113450369 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.4113450369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.301921262 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 118966277751 ps |
| CPU time | 712.33 seconds |
| Started | Oct 09 06:23:19 AM UTC 24 |
| Finished | Oct 09 06:35:18 AM UTC 24 |
| Peak memory | 213756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301921262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.301921262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.1785824622 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 438662192008 ps |
| CPU time | 1289.43 seconds |
| Started | Oct 09 06:26:28 AM UTC 24 |
| Finished | Oct 09 06:48:11 AM UTC 24 |
| Peak memory | 213372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785824622 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.1785824622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.605498692 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 164724931928 ps |
| CPU time | 409.72 seconds |
| Started | Oct 09 06:29:00 AM UTC 24 |
| Finished | Oct 09 06:35:55 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605498692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.605498692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.164611021 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 335263443789 ps |
| CPU time | 224.82 seconds |
| Started | Oct 09 06:32:33 AM UTC 24 |
| Finished | Oct 09 06:36:21 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164611021 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.164611021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.52932230 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 123764349623 ps |
| CPU time | 688.91 seconds |
| Started | Oct 09 06:33:04 AM UTC 24 |
| Finished | Oct 09 06:44:40 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52932230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.52932230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.3075098919 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 502723804848 ps |
| CPU time | 640.03 seconds |
| Started | Oct 09 06:41:24 AM UTC 24 |
| Finished | Oct 09 06:52:11 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075098919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3075098919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.1522755424 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 108755460238 ps |
| CPU time | 651.7 seconds |
| Started | Oct 09 06:43:53 AM UTC 24 |
| Finished | Oct 09 06:54:52 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522755424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1522755424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.168208193 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 346486128702 ps |
| CPU time | 499.14 seconds |
| Started | Oct 09 06:45:04 AM UTC 24 |
| Finished | Oct 09 06:53:29 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168208193 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.168208193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2560129125 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 326966326409 ps |
| CPU time | 484.71 seconds |
| Started | Oct 09 07:02:38 AM UTC 24 |
| Finished | Oct 09 07:10:48 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560129125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2560129125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2866827598 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 115401653848 ps |
| CPU time | 824.4 seconds |
| Started | Oct 09 06:07:50 AM UTC 24 |
| Finished | Oct 09 06:21:46 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866827598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2866827598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2225347760 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 175153818093 ps |
| CPU time | 66.88 seconds |
| Started | Oct 09 06:13:55 AM UTC 24 |
| Finished | Oct 09 06:15:04 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225347760 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.2225347760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.52786936 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 324976427741 ps |
| CPU time | 445.06 seconds |
| Started | Oct 09 06:16:23 AM UTC 24 |
| Finished | Oct 09 06:23:53 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52786936 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.52786936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2676156359 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 364409092927 ps |
| CPU time | 59.53 seconds |
| Started | Oct 09 06:16:21 AM UTC 24 |
| Finished | Oct 09 06:17:22 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2676156359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.adc_ctrl_stress_all_with_rand_reset.2676156359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3414184639 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 369557661183 ps |
| CPU time | 1192.34 seconds |
| Started | Oct 09 06:27:52 AM UTC 24 |
| Finished | Oct 09 06:47:57 AM UTC 24 |
| Peak memory | 213372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414184639 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.3414184639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.889888576 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 105540043565 ps |
| CPU time | 417.15 seconds |
| Started | Oct 09 06:41:08 AM UTC 24 |
| Finished | Oct 09 06:48:09 AM UTC 24 |
| Peak memory | 221296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889888576 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.889888576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.3522847271 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 332725765920 ps |
| CPU time | 180.57 seconds |
| Started | Oct 09 06:46:12 AM UTC 24 |
| Finished | Oct 09 06:49:15 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522847271 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.3522847271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3388714811 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 128945165526 ps |
| CPU time | 766.51 seconds |
| Started | Oct 09 06:49:22 AM UTC 24 |
| Finished | Oct 09 07:02:18 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388714811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3388714811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.3077266629 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 550814629200 ps |
| CPU time | 1310.05 seconds |
| Started | Oct 09 06:53:24 AM UTC 24 |
| Finished | Oct 09 07:15:27 AM UTC 24 |
| Peak memory | 213432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077266629 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.3077266629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1672858032 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 337439743391 ps |
| CPU time | 409.52 seconds |
| Started | Oct 09 07:08:06 AM UTC 24 |
| Finished | Oct 09 07:15:00 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672858032 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.1672858032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1311612959 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 166342574136 ps |
| CPU time | 336.25 seconds |
| Started | Oct 09 07:07:55 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311612959 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.1311612959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.586304974 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 817597090 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 07:10:57 AM UTC 24 |
| Finished | Oct 09 07:11:05 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586304974 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.586304974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1891835158 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1109222959 ps |
| CPU time | 9.95 seconds |
| Started | Oct 09 07:10:55 AM UTC 24 |
| Finished | Oct 09 07:11:06 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891835158 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.1891835158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3520338111 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 990173108 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 07:10:54 AM UTC 24 |
| Finished | Oct 09 07:11:00 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520338111 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.3520338111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.119444422 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 551644407 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 07:11:05 AM UTC 24 |
| Finished | Oct 09 07:11:09 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=119444422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr _mem_rw_with_rand_reset.119444422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1716300678 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 500478153 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 07:10:54 AM UTC 24 |
| Finished | Oct 09 07:10:57 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716300678 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1716300678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2184467285 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 367158074 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 07:10:50 AM UTC 24 |
| Finished | Oct 09 07:10:54 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184467285 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2184467285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3766877103 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2268877139 ps |
| CPU time | 7.08 seconds |
| Started | Oct 09 07:11:00 AM UTC 24 |
| Finished | Oct 09 07:11:09 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766877103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.3766877103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1924290586 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1121501681 ps |
| CPU time | 3.34 seconds |
| Started | Oct 09 07:10:49 AM UTC 24 |
| Finished | Oct 09 07:10:53 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924290586 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1924290586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.6739164 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 701483172 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 07:11:12 AM UTC 24 |
| Finished | Oct 09 07:11:17 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6739164 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.6739164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.210725421 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 21106444466 ps |
| CPU time | 42.16 seconds |
| Started | Oct 09 07:11:11 AM UTC 24 |
| Finished | Oct 09 07:11:55 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210725421 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.210725421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1864719553 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 794704654 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 07:11:10 AM UTC 24 |
| Finished | Oct 09 07:11:13 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864719553 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.1864719553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.639363487 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 456125086 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 07:11:13 AM UTC 24 |
| Finished | Oct 09 07:11:17 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=639363487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr _mem_rw_with_rand_reset.639363487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2255391447 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 367490495 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 07:11:10 AM UTC 24 |
| Finished | Oct 09 07:11:13 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255391447 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2255391447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3492243839 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4734876972 ps |
| CPU time | 2.86 seconds |
| Started | Oct 09 07:11:13 AM UTC 24 |
| Finished | Oct 09 07:11:17 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492243839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.3492243839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2920722221 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8232242248 ps |
| CPU time | 13.1 seconds |
| Started | Oct 09 07:11:09 AM UTC 24 |
| Finished | Oct 09 07:11:23 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920722221 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.2920722221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2101495465 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 588696043 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 07:12:03 AM UTC 24 |
| Finished | Oct 09 07:12:06 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2101495465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c sr_mem_rw_with_rand_reset.2101495465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1946285199 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 455798747 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 07:12:03 AM UTC 24 |
| Finished | Oct 09 07:12:08 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946285199 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1946285199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3077093231 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 485722592 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 07:12:02 AM UTC 24 |
| Finished | Oct 09 07:12:05 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077093231 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3077093231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2481854290 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2283315060 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 07:12:03 AM UTC 24 |
| Finished | Oct 09 07:12:10 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481854290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.2481854290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2174385759 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 552672747 ps |
| CPU time | 5.37 seconds |
| Started | Oct 09 07:12:00 AM UTC 24 |
| Finished | Oct 09 07:12:07 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174385759 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2174385759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3857576363 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 8878143130 ps |
| CPU time | 11.35 seconds |
| Started | Oct 09 07:12:01 AM UTC 24 |
| Finished | Oct 09 07:12:14 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857576363 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.3857576363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.631258374 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 654409742 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 07:12:06 AM UTC 24 |
| Finished | Oct 09 07:12:09 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=631258374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_cs r_mem_rw_with_rand_reset.631258374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3765503443 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 463181495 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 07:12:06 AM UTC 24 |
| Finished | Oct 09 07:12:08 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765503443 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3765503443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3978639276 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 310690346 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 07:12:05 AM UTC 24 |
| Finished | Oct 09 07:12:07 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978639276 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3978639276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3922546693 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3677374628 ps |
| CPU time | 23.09 seconds |
| Started | Oct 09 07:12:06 AM UTC 24 |
| Finished | Oct 09 07:12:30 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922546693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.3922546693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2683351156 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 559242064 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 07:12:04 AM UTC 24 |
| Finished | Oct 09 07:12:11 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683351156 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2683351156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2175186632 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 8672618026 ps |
| CPU time | 25.94 seconds |
| Started | Oct 09 07:12:04 AM UTC 24 |
| Finished | Oct 09 07:12:32 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175186632 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.2175186632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.30592847 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 509730858 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 07:12:10 AM UTC 24 |
| Finished | Oct 09 07:12:14 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=30592847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr _mem_rw_with_rand_reset.30592847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2582942133 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 454510391 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 07:12:09 AM UTC 24 |
| Finished | Oct 09 07:12:13 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582942133 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2582942133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3976141042 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 489647228 ps |
| CPU time | 2.01 seconds |
| Started | Oct 09 07:12:08 AM UTC 24 |
| Finished | Oct 09 07:12:11 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976141042 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3976141042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4148634870 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2268663838 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 07:12:09 AM UTC 24 |
| Finished | Oct 09 07:12:21 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148634870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.4148634870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2939805891 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 687345916 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 07:12:07 AM UTC 24 |
| Finished | Oct 09 07:12:11 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939805891 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2939805891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1151220579 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 8726788881 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 07:12:07 AM UTC 24 |
| Finished | Oct 09 07:12:17 AM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151220579 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.1151220579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1744931095 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 363154528 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 07:12:14 AM UTC 24 |
| Finished | Oct 09 07:12:19 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1744931095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c sr_mem_rw_with_rand_reset.1744931095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.770539387 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 493698352 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 07:12:12 AM UTC 24 |
| Finished | Oct 09 07:12:15 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770539387 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.770539387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1994007379 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 531372327 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 07:12:12 AM UTC 24 |
| Finished | Oct 09 07:12:15 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994007379 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1994007379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3845078050 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4669004021 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 07:12:12 AM UTC 24 |
| Finished | Oct 09 07:12:20 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845078050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.3845078050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2348158309 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 473439633 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 07:12:12 AM UTC 24 |
| Finished | Oct 09 07:12:18 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348158309 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2348158309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.892233638 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 8660527387 ps |
| CPU time | 14.48 seconds |
| Started | Oct 09 07:12:12 AM UTC 24 |
| Finished | Oct 09 07:12:28 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892233638 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.892233638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2302990322 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 416939239 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 07:12:19 AM UTC 24 |
| Finished | Oct 09 07:12:22 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2302990322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c sr_mem_rw_with_rand_reset.2302990322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2358763549 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 583592992 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 07:12:17 AM UTC 24 |
| Finished | Oct 09 07:12:20 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358763549 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2358763549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2668593830 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 314732641 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 07:12:17 AM UTC 24 |
| Finished | Oct 09 07:12:20 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668593830 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2668593830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3586244714 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2464179401 ps |
| CPU time | 3.44 seconds |
| Started | Oct 09 07:12:18 AM UTC 24 |
| Finished | Oct 09 07:12:23 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586244714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.3586244714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.786369765 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 374756347 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 07:12:15 AM UTC 24 |
| Finished | Oct 09 07:12:20 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786369765 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.786369765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1347999668 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8277620195 ps |
| CPU time | 41.46 seconds |
| Started | Oct 09 07:12:17 AM UTC 24 |
| Finished | Oct 09 07:13:00 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347999668 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.1347999668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.781596811 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 603140482 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 07:12:22 AM UTC 24 |
| Finished | Oct 09 07:12:25 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=781596811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs r_mem_rw_with_rand_reset.781596811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.346861112 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 405652694 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 07:12:21 AM UTC 24 |
| Finished | Oct 09 07:12:26 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346861112 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.346861112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3119207006 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 514313120 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 07:12:20 AM UTC 24 |
| Finished | Oct 09 07:12:24 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119207006 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3119207006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.869023003 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2832613947 ps |
| CPU time | 8.19 seconds |
| Started | Oct 09 07:12:21 AM UTC 24 |
| Finished | Oct 09 07:12:31 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869023003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.869023003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3684148777 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 332914736 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 07:12:20 AM UTC 24 |
| Finished | Oct 09 07:12:25 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684148777 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3684148777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.877936333 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 8404057430 ps |
| CPU time | 22.21 seconds |
| Started | Oct 09 07:12:20 AM UTC 24 |
| Finished | Oct 09 07:12:45 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877936333 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.877936333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.281887324 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 478707113 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 07:12:26 AM UTC 24 |
| Finished | Oct 09 07:12:29 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=281887324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_cs r_mem_rw_with_rand_reset.281887324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.907688771 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 525316927 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 07:12:26 AM UTC 24 |
| Finished | Oct 09 07:12:28 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907688771 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.907688771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2438166262 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 282501459 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 07:12:25 AM UTC 24 |
| Finished | Oct 09 07:12:27 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438166262 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2438166262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.765527541 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2536979571 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 07:12:26 AM UTC 24 |
| Finished | Oct 09 07:12:30 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765527541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.765527541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.940608450 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 800171109 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 07:12:24 AM UTC 24 |
| Finished | Oct 09 07:12:28 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940608450 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.940608450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1579237536 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 8363204279 ps |
| CPU time | 26.29 seconds |
| Started | Oct 09 07:12:24 AM UTC 24 |
| Finished | Oct 09 07:12:51 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579237536 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.1579237536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3333136029 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 394779244 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 07:12:29 AM UTC 24 |
| Finished | Oct 09 07:12:33 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3333136029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c sr_mem_rw_with_rand_reset.3333136029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3129094434 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 492837487 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 07:12:28 AM UTC 24 |
| Finished | Oct 09 07:12:31 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129094434 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3129094434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.714467898 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 289972873 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 07:12:27 AM UTC 24 |
| Finished | Oct 09 07:12:30 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714467898 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.714467898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.928881091 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 4370449322 ps |
| CPU time | 19.07 seconds |
| Started | Oct 09 07:12:28 AM UTC 24 |
| Finished | Oct 09 07:12:49 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928881091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.928881091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1656747643 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 538288477 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 07:12:27 AM UTC 24 |
| Finished | Oct 09 07:12:32 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656747643 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1656747643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2248869452 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 7644862445 ps |
| CPU time | 37.09 seconds |
| Started | Oct 09 07:12:27 AM UTC 24 |
| Finished | Oct 09 07:13:06 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248869452 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.2248869452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3596691834 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 378814494 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 07:12:32 AM UTC 24 |
| Finished | Oct 09 07:12:36 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3596691834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c sr_mem_rw_with_rand_reset.3596691834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2845585027 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 551910340 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 07:12:31 AM UTC 24 |
| Finished | Oct 09 07:12:33 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845585027 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2845585027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1482658414 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 401124179 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 07:12:31 AM UTC 24 |
| Finished | Oct 09 07:12:33 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482658414 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1482658414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2249531494 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4371067980 ps |
| CPU time | 31.39 seconds |
| Started | Oct 09 07:12:32 AM UTC 24 |
| Finished | Oct 09 07:13:04 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249531494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.2249531494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1753461189 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 500767621 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 07:12:29 AM UTC 24 |
| Finished | Oct 09 07:12:33 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753461189 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1753461189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.189359853 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 8823024970 ps |
| CPU time | 21.76 seconds |
| Started | Oct 09 07:12:29 AM UTC 24 |
| Finished | Oct 09 07:12:52 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189359853 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.189359853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1729060278 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 539082541 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 07:12:34 AM UTC 24 |
| Finished | Oct 09 07:12:39 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1729060278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c sr_mem_rw_with_rand_reset.1729060278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2292319343 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 505744120 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 07:12:33 AM UTC 24 |
| Finished | Oct 09 07:12:36 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292319343 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2292319343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.3894545874 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 366038976 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 07:12:33 AM UTC 24 |
| Finished | Oct 09 07:12:36 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894545874 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3894545874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3420301612 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2080210248 ps |
| CPU time | 9.13 seconds |
| Started | Oct 09 07:12:34 AM UTC 24 |
| Finished | Oct 09 07:12:44 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420301612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.3420301612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2054832678 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 353915294 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 07:12:32 AM UTC 24 |
| Finished | Oct 09 07:12:35 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054832678 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2054832678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3520176913 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7759511106 ps |
| CPU time | 15.07 seconds |
| Started | Oct 09 07:12:32 AM UTC 24 |
| Finished | Oct 09 07:12:48 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520176913 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.3520176913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1713650528 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1223576194 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 07:11:19 AM UTC 24 |
| Finished | Oct 09 07:11:25 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713650528 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.1713650528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.901484714 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 831791529 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 07:11:16 AM UTC 24 |
| Finished | Oct 09 07:11:20 AM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901484714 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.901484714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2474631873 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 349463992 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 07:11:19 AM UTC 24 |
| Finished | Oct 09 07:11:22 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2474631873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs r_mem_rw_with_rand_reset.2474631873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4128375769 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 396722515 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 07:11:18 AM UTC 24 |
| Finished | Oct 09 07:11:21 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128375769 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4128375769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1303435360 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 481022984 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 07:11:14 AM UTC 24 |
| Finished | Oct 09 07:11:17 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303435360 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1303435360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2397367936 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1829580057 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 07:11:19 AM UTC 24 |
| Finished | Oct 09 07:11:22 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397367936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.2397367936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3156232798 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 858156253 ps |
| CPU time | 2.85 seconds |
| Started | Oct 09 07:11:14 AM UTC 24 |
| Finished | Oct 09 07:11:18 AM UTC 24 |
| Peak memory | 221692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156232798 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3156232798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4258312711 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8882842582 ps |
| CPU time | 13.82 seconds |
| Started | Oct 09 07:11:14 AM UTC 24 |
| Finished | Oct 09 07:11:29 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258312711 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.4258312711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2065145402 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 498630880 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:12:34 AM UTC 24 |
| Finished | Oct 09 07:12:37 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065145402 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2065145402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1268929749 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 510066081 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 07:12:34 AM UTC 24 |
| Finished | Oct 09 07:12:37 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268929749 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1268929749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3974742615 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 306767110 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 07:12:35 AM UTC 24 |
| Finished | Oct 09 07:12:39 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974742615 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3974742615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3484061248 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 512222196 ps |
| CPU time | 3.34 seconds |
| Started | Oct 09 07:12:36 AM UTC 24 |
| Finished | Oct 09 07:12:41 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484061248 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3484061248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.913972132 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 424457826 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 07:12:36 AM UTC 24 |
| Finished | Oct 09 07:12:40 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913972132 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.913972132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1325621538 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 514730455 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 07:12:36 AM UTC 24 |
| Finished | Oct 09 07:12:39 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325621538 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1325621538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.205117815 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 537587157 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 07:12:37 AM UTC 24 |
| Finished | Oct 09 07:12:40 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205117815 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.205117815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2342303138 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 295586145 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 07:12:38 AM UTC 24 |
| Finished | Oct 09 07:12:41 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342303138 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2342303138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2288735602 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 311358542 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 07:12:40 AM UTC 24 |
| Finished | Oct 09 07:12:43 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288735602 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2288735602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1002861711 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 337033949 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 07:12:40 AM UTC 24 |
| Finished | Oct 09 07:12:42 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002861711 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1002861711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1109378026 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 470014119 ps |
| CPU time | 2.92 seconds |
| Started | Oct 09 07:11:26 AM UTC 24 |
| Finished | Oct 09 07:11:31 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109378026 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.1109378026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1399962210 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 43545833819 ps |
| CPU time | 119.66 seconds |
| Started | Oct 09 07:11:24 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399962210 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.1399962210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3541173752 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 818547486 ps |
| CPU time | 4.83 seconds |
| Started | Oct 09 07:11:23 AM UTC 24 |
| Finished | Oct 09 07:11:29 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541173752 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.3541173752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3285067516 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 475066652 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 07:11:27 AM UTC 24 |
| Finished | Oct 09 07:11:34 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3285067516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs r_mem_rw_with_rand_reset.3285067516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1556460405 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 409801063 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 07:11:24 AM UTC 24 |
| Finished | Oct 09 07:11:27 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556460405 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1556460405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2541608467 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 451676395 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 07:11:23 AM UTC 24 |
| Finished | Oct 09 07:11:27 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541608467 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2541608467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1172337896 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2271500861 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 07:11:26 AM UTC 24 |
| Finished | Oct 09 07:11:32 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172337896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.1172337896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1150465972 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 729773076 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 07:11:21 AM UTC 24 |
| Finished | Oct 09 07:11:26 AM UTC 24 |
| Peak memory | 221752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150465972 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1150465972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4216917477 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8315451875 ps |
| CPU time | 26.83 seconds |
| Started | Oct 09 07:11:22 AM UTC 24 |
| Finished | Oct 09 07:11:51 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216917477 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.4216917477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2376746464 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 481738169 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 07:12:40 AM UTC 24 |
| Finished | Oct 09 07:12:44 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376746464 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2376746464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.2123944782 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 396465046 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 07:12:41 AM UTC 24 |
| Finished | Oct 09 07:12:43 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123944782 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2123944782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3559265430 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 335711448 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 07:12:41 AM UTC 24 |
| Finished | Oct 09 07:12:43 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559265430 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3559265430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.941176529 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 404275412 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 07:12:42 AM UTC 24 |
| Finished | Oct 09 07:12:44 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941176529 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.941176529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2291770443 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 448863172 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 07:12:42 AM UTC 24 |
| Finished | Oct 09 07:12:45 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291770443 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2291770443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2044447128 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 423163885 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 07:12:42 AM UTC 24 |
| Finished | Oct 09 07:12:45 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044447128 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2044447128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.817957023 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 378438530 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 07:12:44 AM UTC 24 |
| Finished | Oct 09 07:12:48 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817957023 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.817957023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2814643930 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 525289684 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 07:12:44 AM UTC 24 |
| Finished | Oct 09 07:12:47 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814643930 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2814643930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2988634545 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 372434452 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 07:12:44 AM UTC 24 |
| Finished | Oct 09 07:12:47 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988634545 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2988634545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.793338067 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 408379073 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 07:12:44 AM UTC 24 |
| Finished | Oct 09 07:12:47 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793338067 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.793338067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1560087677 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1303864306 ps |
| CPU time | 3.8 seconds |
| Started | Oct 09 07:11:34 AM UTC 24 |
| Finished | Oct 09 07:11:39 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560087677 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.1560087677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3653931693 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 11497693763 ps |
| CPU time | 51.36 seconds |
| Started | Oct 09 07:11:33 AM UTC 24 |
| Finished | Oct 09 07:12:26 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653931693 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.3653931693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.281310774 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1488927027 ps |
| CPU time | 5.26 seconds |
| Started | Oct 09 07:11:32 AM UTC 24 |
| Finished | Oct 09 07:11:38 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281310774 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.281310774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.469583525 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 540556777 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 07:11:36 AM UTC 24 |
| Finished | Oct 09 07:11:41 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=469583525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr _mem_rw_with_rand_reset.469583525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.824657739 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 338185094 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 07:11:32 AM UTC 24 |
| Finished | Oct 09 07:11:35 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824657739 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.824657739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.4237810024 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 297712614 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 07:11:32 AM UTC 24 |
| Finished | Oct 09 07:11:35 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237810024 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4237810024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.989362185 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4381406646 ps |
| CPU time | 7.89 seconds |
| Started | Oct 09 07:11:35 AM UTC 24 |
| Finished | Oct 09 07:11:44 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989362185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.989362185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.680464142 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 468109778 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 07:11:27 AM UTC 24 |
| Finished | Oct 09 07:11:35 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680464142 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.680464142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2236448177 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 327634496 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 07:12:45 AM UTC 24 |
| Finished | Oct 09 07:12:48 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236448177 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2236448177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.59158521 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 502058268 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 07:12:45 AM UTC 24 |
| Finished | Oct 09 07:12:48 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59158521 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.59158521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2296605341 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 390792941 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 07:12:45 AM UTC 24 |
| Finished | Oct 09 07:12:49 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296605341 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2296605341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4194281046 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 425211447 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 07:12:46 AM UTC 24 |
| Finished | Oct 09 07:12:49 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194281046 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4194281046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3686677245 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 300868149 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 07:12:46 AM UTC 24 |
| Finished | Oct 09 07:12:48 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686677245 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3686677245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.2769319119 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 428277451 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 07:12:48 AM UTC 24 |
| Finished | Oct 09 07:12:51 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769319119 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2769319119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3873455351 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 304293431 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 07:12:48 AM UTC 24 |
| Finished | Oct 09 07:12:51 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873455351 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3873455351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1731880203 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 391362877 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:53 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731880203 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1731880203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1395068077 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 380773451 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:51 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395068077 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1395068077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2247088713 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 524874005 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:52 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247088713 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2247088713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3814967039 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 525544393 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 07:11:39 AM UTC 24 |
| Finished | Oct 09 07:11:44 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3814967039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs r_mem_rw_with_rand_reset.3814967039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2841478835 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 484773583 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 07:11:37 AM UTC 24 |
| Finished | Oct 09 07:11:41 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841478835 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2841478835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.1000333334 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 346883677 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 07:11:36 AM UTC 24 |
| Finished | Oct 09 07:11:39 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000333334 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1000333334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.259658918 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4693904055 ps |
| CPU time | 18.06 seconds |
| Started | Oct 09 07:11:39 AM UTC 24 |
| Finished | Oct 09 07:11:59 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259658918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.259658918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1060825379 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 427272205 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 07:11:36 AM UTC 24 |
| Finished | Oct 09 07:11:41 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060825379 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1060825379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.229195409 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3915949924 ps |
| CPU time | 20.35 seconds |
| Started | Oct 09 07:11:36 AM UTC 24 |
| Finished | Oct 09 07:11:58 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229195409 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.229195409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3199260120 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 492164392 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 07:11:44 AM UTC 24 |
| Finished | Oct 09 07:11:47 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3199260120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs r_mem_rw_with_rand_reset.3199260120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4057589183 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 443389494 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 07:11:42 AM UTC 24 |
| Finished | Oct 09 07:11:46 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057589183 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4057589183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3031657485 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 456665463 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 07:11:42 AM UTC 24 |
| Finished | Oct 09 07:11:44 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031657485 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3031657485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.725992952 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4289486896 ps |
| CPU time | 20.59 seconds |
| Started | Oct 09 07:11:42 AM UTC 24 |
| Finished | Oct 09 07:12:04 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725992952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.725992952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.68684994 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 586370709 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 07:11:39 AM UTC 24 |
| Finished | Oct 09 07:11:43 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68684994 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.68684994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1948368010 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 8419108031 ps |
| CPU time | 28.51 seconds |
| Started | Oct 09 07:11:41 AM UTC 24 |
| Finished | Oct 09 07:12:10 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948368010 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.1948368010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.867745687 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 490973573 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 07:11:49 AM UTC 24 |
| Finished | Oct 09 07:11:54 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=867745687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr _mem_rw_with_rand_reset.867745687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3841241745 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 473964885 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 07:11:47 AM UTC 24 |
| Finished | Oct 09 07:11:50 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841241745 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3841241745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.757638060 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 322653468 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 07:11:45 AM UTC 24 |
| Finished | Oct 09 07:11:48 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757638060 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.757638060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3251842495 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2072034155 ps |
| CPU time | 6.42 seconds |
| Started | Oct 09 07:11:47 AM UTC 24 |
| Finished | Oct 09 07:11:55 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251842495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.3251842495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3552243719 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 307367349 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 07:11:45 AM UTC 24 |
| Finished | Oct 09 07:11:50 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552243719 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3552243719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.379453004 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8753148095 ps |
| CPU time | 11.81 seconds |
| Started | Oct 09 07:11:45 AM UTC 24 |
| Finished | Oct 09 07:11:58 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379453004 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.379453004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2163785196 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 605370931 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 07:11:56 AM UTC 24 |
| Finished | Oct 09 07:11:58 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2163785196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs r_mem_rw_with_rand_reset.2163785196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.823451806 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 472456348 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 07:11:54 AM UTC 24 |
| Finished | Oct 09 07:11:59 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823451806 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.823451806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2195630074 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 340898220 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 07:11:52 AM UTC 24 |
| Finished | Oct 09 07:11:55 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195630074 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2195630074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2740563476 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5116562212 ps |
| CPU time | 29.48 seconds |
| Started | Oct 09 07:11:56 AM UTC 24 |
| Finished | Oct 09 07:12:27 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740563476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.2740563476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2872573974 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 499189249 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 07:11:50 AM UTC 24 |
| Finished | Oct 09 07:11:55 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872573974 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2872573974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2027257000 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4664386945 ps |
| CPU time | 11.44 seconds |
| Started | Oct 09 07:11:51 AM UTC 24 |
| Finished | Oct 09 07:12:04 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027257000 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.2027257000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3695929525 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 699085785 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 07:12:00 AM UTC 24 |
| Finished | Oct 09 07:12:02 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3695929525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs r_mem_rw_with_rand_reset.3695929525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2013306687 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 431306204 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 07:11:59 AM UTC 24 |
| Finished | Oct 09 07:12:02 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013306687 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2013306687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.1066231205 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 473079594 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:11:59 AM UTC 24 |
| Finished | Oct 09 07:12:01 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066231205 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1066231205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3659307120 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2701436656 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 07:11:59 AM UTC 24 |
| Finished | Oct 09 07:12:03 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659307120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.3659307120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4010494744 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 948952460 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 07:11:56 AM UTC 24 |
| Finished | Oct 09 07:12:00 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010494744 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4010494744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1134726933 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4165785921 ps |
| CPU time | 8.19 seconds |
| Started | Oct 09 07:11:56 AM UTC 24 |
| Finished | Oct 09 07:12:05 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134726933 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.1134726933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2981930729 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 164860100451 ps |
| CPU time | 103.43 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:08:45 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981930729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2981930729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3153131342 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 491949416904 ps |
| CPU time | 1334.33 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:29:28 AM UTC 24 |
| Peak memory | 213288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153131342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.3153131342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.671828094 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 168450180800 ps |
| CPU time | 87.16 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:08:29 AM UTC 24 |
| Peak memory | 213200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671828094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.671828094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.3596857248 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 488312030273 ps |
| CPU time | 288.74 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:11:52 AM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596857248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.3596857248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2693758068 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 614193341334 ps |
| CPU time | 343.54 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:12:48 AM UTC 24 |
| Peak memory | 213288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693758068 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.2693758068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1814360061 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5781376976 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 06:06:57 AM UTC 24 |
| Finished | Oct 09 06:07:05 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814360061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1814360061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2272528827 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 329567361159 ps |
| CPU time | 843.48 seconds |
| Started | Oct 09 06:07:04 AM UTC 24 |
| Finished | Oct 09 06:21:51 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272528827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2272528827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3212782949 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 353546589781 ps |
| CPU time | 989.61 seconds |
| Started | Oct 09 06:07:04 AM UTC 24 |
| Finished | Oct 09 06:24:04 AM UTC 24 |
| Peak memory | 213628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212782949 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.3212782949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.2578328218 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 24252940136 ps |
| CPU time | 12.64 seconds |
| Started | Oct 09 06:07:04 AM UTC 24 |
| Finished | Oct 09 06:07:52 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578328218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2578328218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.777729225 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 413441890 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 06:14:54 AM UTC 24 |
| Finished | Oct 09 06:14:56 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777729225 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.777729225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1744737157 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 162266814798 ps |
| CPU time | 325.58 seconds |
| Started | Oct 09 06:13:03 AM UTC 24 |
| Finished | Oct 09 06:18:33 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744737157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1744737157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3983970328 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 485790541131 ps |
| CPU time | 1355.36 seconds |
| Started | Oct 09 06:13:07 AM UTC 24 |
| Finished | Oct 09 06:35:56 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983970328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.3983970328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3768053794 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 483100691604 ps |
| CPU time | 631.66 seconds |
| Started | Oct 09 06:12:53 AM UTC 24 |
| Finished | Oct 09 06:23:31 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768053794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3768053794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1467391862 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 330690147275 ps |
| CPU time | 869.6 seconds |
| Started | Oct 09 06:12:54 AM UTC 24 |
| Finished | Oct 09 06:27:33 AM UTC 24 |
| Peak memory | 213288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467391862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.1467391862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1074213637 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 600559345104 ps |
| CPU time | 886.53 seconds |
| Started | Oct 09 06:13:54 AM UTC 24 |
| Finished | Oct 09 06:28:50 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074213637 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.1074213637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3808556652 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 104518557116 ps |
| CPU time | 382.07 seconds |
| Started | Oct 09 06:14:24 AM UTC 24 |
| Finished | Oct 09 06:20:50 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808556652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3808556652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.306752940 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 35795822108 ps |
| CPU time | 58.02 seconds |
| Started | Oct 09 06:14:18 AM UTC 24 |
| Finished | Oct 09 06:15:17 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306752940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.306752940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1038053983 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4614782028 ps |
| CPU time | 10.17 seconds |
| Started | Oct 09 06:14:11 AM UTC 24 |
| Finished | Oct 09 06:14:23 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038053983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1038053983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2532345110 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 6137914847 ps |
| CPU time | 10 seconds |
| Started | Oct 09 06:12:51 AM UTC 24 |
| Finished | Oct 09 06:13:02 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532345110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2532345110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3447665380 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 336477381983 ps |
| CPU time | 85.45 seconds |
| Started | Oct 09 06:14:49 AM UTC 24 |
| Finished | Oct 09 06:16:16 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447665380 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.3447665380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2517895276 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4955868094 ps |
| CPU time | 7.73 seconds |
| Started | Oct 09 06:14:45 AM UTC 24 |
| Finished | Oct 09 06:14:54 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2517895276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.adc_ctrl_stress_all_with_rand_reset.2517895276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.1209387492 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 496546718 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 06:16:30 AM UTC 24 |
| Finished | Oct 09 06:16:33 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209387492 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1209387492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2809179065 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 164669481045 ps |
| CPU time | 334.43 seconds |
| Started | Oct 09 06:15:38 AM UTC 24 |
| Finished | Oct 09 06:21:17 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809179065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2809179065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1720666799 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 483052044512 ps |
| CPU time | 543.07 seconds |
| Started | Oct 09 06:15:05 AM UTC 24 |
| Finished | Oct 09 06:24:14 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720666799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.1720666799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.11769466 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 395597712148 ps |
| CPU time | 417.35 seconds |
| Started | Oct 09 06:15:22 AM UTC 24 |
| Finished | Oct 09 06:22:25 AM UTC 24 |
| Peak memory | 210664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11769466 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.11769466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1436154807 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 97764047672 ps |
| CPU time | 476.9 seconds |
| Started | Oct 09 06:16:17 AM UTC 24 |
| Finished | Oct 09 06:24:19 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436154807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1436154807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.3768962390 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 31432133274 ps |
| CPU time | 112.27 seconds |
| Started | Oct 09 06:16:05 AM UTC 24 |
| Finished | Oct 09 06:18:00 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768962390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3768962390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1505736875 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4993231804 ps |
| CPU time | 16.88 seconds |
| Started | Oct 09 06:15:46 AM UTC 24 |
| Finished | Oct 09 06:16:04 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505736875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1505736875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.4223823549 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5903219348 ps |
| CPU time | 24.11 seconds |
| Started | Oct 09 06:14:54 AM UTC 24 |
| Finished | Oct 09 06:15:19 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223823549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4223823549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.409420322 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 403898416 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 06:18:03 AM UTC 24 |
| Finished | Oct 09 06:18:05 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409420322 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.409420322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.1247823965 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 208360337235 ps |
| CPU time | 244.71 seconds |
| Started | Oct 09 06:17:23 AM UTC 24 |
| Finished | Oct 09 06:21:32 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247823965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1247823965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1211829806 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 167411093159 ps |
| CPU time | 147.34 seconds |
| Started | Oct 09 06:16:52 AM UTC 24 |
| Finished | Oct 09 06:19:21 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211829806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1211829806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2670161153 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 327461823285 ps |
| CPU time | 297.15 seconds |
| Started | Oct 09 06:16:52 AM UTC 24 |
| Finished | Oct 09 06:21:53 AM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670161153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.2670161153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.41556276 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 488195105650 ps |
| CPU time | 732.87 seconds |
| Started | Oct 09 06:16:40 AM UTC 24 |
| Finished | Oct 09 06:29:01 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41556276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.41556276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1389731947 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 324598626338 ps |
| CPU time | 385.94 seconds |
| Started | Oct 09 06:16:48 AM UTC 24 |
| Finished | Oct 09 06:23:19 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389731947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.1389731947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.3374256231 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 348557920732 ps |
| CPU time | 271.21 seconds |
| Started | Oct 09 06:16:58 AM UTC 24 |
| Finished | Oct 09 06:21:33 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374256231 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.3374256231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3600568610 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 617017548728 ps |
| CPU time | 830.96 seconds |
| Started | Oct 09 06:17:04 AM UTC 24 |
| Finished | Oct 09 06:31:04 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600568610 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.3600568610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1289739356 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 95367074676 ps |
| CPU time | 625.01 seconds |
| Started | Oct 09 06:17:31 AM UTC 24 |
| Finished | Oct 09 06:28:03 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289739356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1289739356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.2013358791 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 34700028509 ps |
| CPU time | 39.49 seconds |
| Started | Oct 09 06:17:28 AM UTC 24 |
| Finished | Oct 09 06:18:09 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013358791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2013358791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1421508249 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4843984294 ps |
| CPU time | 6.63 seconds |
| Started | Oct 09 06:17:26 AM UTC 24 |
| Finished | Oct 09 06:17:34 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421508249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1421508249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1878215480 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5664164592 ps |
| CPU time | 20.92 seconds |
| Started | Oct 09 06:16:34 AM UTC 24 |
| Finished | Oct 09 06:16:57 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878215480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1878215480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3044810452 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 330424213678 ps |
| CPU time | 301.45 seconds |
| Started | Oct 09 06:18:00 AM UTC 24 |
| Finished | Oct 09 06:23:06 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044810452 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.3044810452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2145807965 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5595182071 ps |
| CPU time | 33.48 seconds |
| Started | Oct 09 06:17:34 AM UTC 24 |
| Finished | Oct 09 06:18:09 AM UTC 24 |
| Peak memory | 227660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2145807965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.adc_ctrl_stress_all_with_rand_reset.2145807965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3468435375 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 302650197 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 06:19:35 AM UTC 24 |
| Finished | Oct 09 06:19:38 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468435375 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3468435375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3795778682 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 332050441500 ps |
| CPU time | 291.3 seconds |
| Started | Oct 09 06:18:11 AM UTC 24 |
| Finished | Oct 09 06:23:06 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795778682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3795778682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.948827051 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 161818916734 ps |
| CPU time | 141.57 seconds |
| Started | Oct 09 06:18:15 AM UTC 24 |
| Finished | Oct 09 06:20:39 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948827051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.948827051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.925301131 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 495067688478 ps |
| CPU time | 1445.57 seconds |
| Started | Oct 09 06:18:10 AM UTC 24 |
| Finished | Oct 09 06:42:30 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925301131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.925301131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.712555133 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 486745617942 ps |
| CPU time | 1299.63 seconds |
| Started | Oct 09 06:18:10 AM UTC 24 |
| Finished | Oct 09 06:40:02 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712555133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.712555133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2239538130 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 363652069075 ps |
| CPU time | 1003.53 seconds |
| Started | Oct 09 06:18:29 AM UTC 24 |
| Finished | Oct 09 06:35:23 AM UTC 24 |
| Peak memory | 213300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239538130 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.2239538130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.397687865 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 588391080145 ps |
| CPU time | 1625.29 seconds |
| Started | Oct 09 06:18:34 AM UTC 24 |
| Finished | Oct 09 06:45:55 AM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397687865 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.397687865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2928042629 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 80056535572 ps |
| CPU time | 547.83 seconds |
| Started | Oct 09 06:19:24 AM UTC 24 |
| Finished | Oct 09 06:28:38 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928042629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2928042629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2476451904 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 29051088038 ps |
| CPU time | 73.6 seconds |
| Started | Oct 09 06:19:22 AM UTC 24 |
| Finished | Oct 09 06:20:37 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476451904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2476451904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3251705532 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5163941281 ps |
| CPU time | 22.23 seconds |
| Started | Oct 09 06:19:20 AM UTC 24 |
| Finished | Oct 09 06:19:43 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251705532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3251705532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.1082524779 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5669766213 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 06:18:06 AM UTC 24 |
| Finished | Oct 09 06:18:10 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082524779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1082524779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.3385576443 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 622599566068 ps |
| CPU time | 627.03 seconds |
| Started | Oct 09 06:19:32 AM UTC 24 |
| Finished | Oct 09 06:30:06 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385576443 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.3385576443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1843039673 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 14059286804 ps |
| CPU time | 11.38 seconds |
| Started | Oct 09 06:19:28 AM UTC 24 |
| Finished | Oct 09 06:19:41 AM UTC 24 |
| Peak memory | 220980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1843039673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.adc_ctrl_stress_all_with_rand_reset.1843039673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.388032182 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 504259251 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 06:21:15 AM UTC 24 |
| Finished | Oct 09 06:21:19 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388032182 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.388032182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1432447742 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 174735534641 ps |
| CPU time | 120.39 seconds |
| Started | Oct 09 06:20:20 AM UTC 24 |
| Finished | Oct 09 06:22:22 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432447742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1432447742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3728550265 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 162596434950 ps |
| CPU time | 417.14 seconds |
| Started | Oct 09 06:19:44 AM UTC 24 |
| Finished | Oct 09 06:26:46 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728550265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3728550265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1707080861 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 163838725769 ps |
| CPU time | 111.23 seconds |
| Started | Oct 09 06:20:02 AM UTC 24 |
| Finished | Oct 09 06:21:56 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707080861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.1707080861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.2234789988 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 490977059503 ps |
| CPU time | 708.64 seconds |
| Started | Oct 09 06:19:41 AM UTC 24 |
| Finished | Oct 09 06:31:38 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234789988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2234789988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4169184041 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 487980040978 ps |
| CPU time | 232.46 seconds |
| Started | Oct 09 06:19:42 AM UTC 24 |
| Finished | Oct 09 06:23:38 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169184041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.4169184041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.1058810191 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 506806977999 ps |
| CPU time | 811.64 seconds |
| Started | Oct 09 06:20:09 AM UTC 24 |
| Finished | Oct 09 06:33:49 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058810191 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.1058810191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3899134802 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 195652307595 ps |
| CPU time | 314.76 seconds |
| Started | Oct 09 06:20:14 AM UTC 24 |
| Finished | Oct 09 06:25:32 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899134802 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.3899134802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2335495784 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 78080758350 ps |
| CPU time | 306.58 seconds |
| Started | Oct 09 06:20:50 AM UTC 24 |
| Finished | Oct 09 06:26:00 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335495784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2335495784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3250869645 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 23579644779 ps |
| CPU time | 88.26 seconds |
| Started | Oct 09 06:20:40 AM UTC 24 |
| Finished | Oct 09 06:22:10 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250869645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3250869645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.1878901905 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3498492167 ps |
| CPU time | 14.58 seconds |
| Started | Oct 09 06:20:38 AM UTC 24 |
| Finished | Oct 09 06:20:54 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878901905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1878901905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.424633437 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 6082972871 ps |
| CPU time | 20.95 seconds |
| Started | Oct 09 06:19:39 AM UTC 24 |
| Finished | Oct 09 06:20:01 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424633437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.424633437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.2244001253 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 30577092418 ps |
| CPU time | 91.32 seconds |
| Started | Oct 09 06:20:56 AM UTC 24 |
| Finished | Oct 09 06:22:29 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244001253 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.2244001253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.300892582 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8477269587 ps |
| CPU time | 25.36 seconds |
| Started | Oct 09 06:20:54 AM UTC 24 |
| Finished | Oct 09 06:21:21 AM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=300892582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.300892582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.768164314 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 449163009 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 06:22:11 AM UTC 24 |
| Finished | Oct 09 06:22:13 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768164314 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.768164314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.3628907135 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 193205088202 ps |
| CPU time | 131.32 seconds |
| Started | Oct 09 06:21:34 AM UTC 24 |
| Finished | Oct 09 06:23:48 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628907135 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.3628907135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.898345562 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 492994130962 ps |
| CPU time | 1571.24 seconds |
| Started | Oct 09 06:21:22 AM UTC 24 |
| Finished | Oct 09 06:47:49 AM UTC 24 |
| Peak memory | 213300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898345562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.898345562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1571858857 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 330317595432 ps |
| CPU time | 299.03 seconds |
| Started | Oct 09 06:21:24 AM UTC 24 |
| Finished | Oct 09 06:26:27 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571858857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.1571858857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.4272316775 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 166632772519 ps |
| CPU time | 34.59 seconds |
| Started | Oct 09 06:21:17 AM UTC 24 |
| Finished | Oct 09 06:21:54 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272316775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4272316775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.595841076 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 505959880995 ps |
| CPU time | 302.68 seconds |
| Started | Oct 09 06:21:20 AM UTC 24 |
| Finished | Oct 09 06:26:26 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595841076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.595841076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3049129484 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 189018963092 ps |
| CPU time | 178.52 seconds |
| Started | Oct 09 06:21:26 AM UTC 24 |
| Finished | Oct 09 06:24:27 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049129484 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.3049129484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2369279015 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 197191392966 ps |
| CPU time | 281.97 seconds |
| Started | Oct 09 06:21:33 AM UTC 24 |
| Finished | Oct 09 06:26:18 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369279015 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.2369279015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.999991646 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 64444431661 ps |
| CPU time | 413.42 seconds |
| Started | Oct 09 06:21:54 AM UTC 24 |
| Finished | Oct 09 06:28:52 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999991646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.999991646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.3152453119 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 29943263843 ps |
| CPU time | 99.39 seconds |
| Started | Oct 09 06:21:53 AM UTC 24 |
| Finished | Oct 09 06:23:35 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152453119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3152453119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.280482924 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5104183180 ps |
| CPU time | 5.67 seconds |
| Started | Oct 09 06:21:51 AM UTC 24 |
| Finished | Oct 09 06:21:58 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280482924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.280482924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2006976568 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5855993018 ps |
| CPU time | 7.68 seconds |
| Started | Oct 09 06:21:16 AM UTC 24 |
| Finished | Oct 09 06:21:25 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006976568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2006976568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2322940923 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 38459509583 ps |
| CPU time | 38.19 seconds |
| Started | Oct 09 06:21:58 AM UTC 24 |
| Finished | Oct 09 06:22:38 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322940923 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.2322940923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3630302241 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 7878805236 ps |
| CPU time | 12.91 seconds |
| Started | Oct 09 06:21:56 AM UTC 24 |
| Finished | Oct 09 06:22:11 AM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3630302241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.adc_ctrl_stress_all_with_rand_reset.3630302241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1125895942 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 427316824 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 06:23:33 AM UTC 24 |
| Finished | Oct 09 06:23:35 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125895942 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1125895942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1603403321 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 338184539883 ps |
| CPU time | 693.28 seconds |
| Started | Oct 09 06:22:56 AM UTC 24 |
| Finished | Oct 09 06:34:38 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603403321 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.1603403321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.4191742407 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 337217797294 ps |
| CPU time | 342.21 seconds |
| Started | Oct 09 06:23:00 AM UTC 24 |
| Finished | Oct 09 06:28:47 AM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191742407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4191742407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4190387048 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 489150260021 ps |
| CPU time | 695.22 seconds |
| Started | Oct 09 06:22:26 AM UTC 24 |
| Finished | Oct 09 06:34:08 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190387048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.4190387048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.3558467344 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 487457459997 ps |
| CPU time | 294.69 seconds |
| Started | Oct 09 06:22:14 AM UTC 24 |
| Finished | Oct 09 06:27:12 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558467344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3558467344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.2736802238 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 321220379917 ps |
| CPU time | 165.21 seconds |
| Started | Oct 09 06:22:17 AM UTC 24 |
| Finished | Oct 09 06:25:04 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736802238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.2736802238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.380587952 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 183404030408 ps |
| CPU time | 559.51 seconds |
| Started | Oct 09 06:22:30 AM UTC 24 |
| Finished | Oct 09 06:31:56 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380587952 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.380587952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3300376535 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 194262616463 ps |
| CPU time | 99.33 seconds |
| Started | Oct 09 06:22:39 AM UTC 24 |
| Finished | Oct 09 06:24:20 AM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300376535 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.3300376535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2849929884 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 46308917727 ps |
| CPU time | 23.23 seconds |
| Started | Oct 09 06:23:06 AM UTC 24 |
| Finished | Oct 09 06:23:31 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849929884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2849929884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2226310453 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4274373530 ps |
| CPU time | 10.29 seconds |
| Started | Oct 09 06:23:06 AM UTC 24 |
| Finished | Oct 09 06:23:18 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226310453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2226310453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3124159568 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6017701215 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 06:22:12 AM UTC 24 |
| Finished | Oct 09 06:22:16 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124159568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3124159568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2052833898 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1546274324 ps |
| CPU time | 14.48 seconds |
| Started | Oct 09 06:23:20 AM UTC 24 |
| Finished | Oct 09 06:23:35 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2052833898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.adc_ctrl_stress_all_with_rand_reset.2052833898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3774033480 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 345264779 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 06:24:20 AM UTC 24 |
| Finished | Oct 09 06:24:24 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774033480 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3774033480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3464084402 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 165559926743 ps |
| CPU time | 134.98 seconds |
| Started | Oct 09 06:23:48 AM UTC 24 |
| Finished | Oct 09 06:26:06 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464084402 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.3464084402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.260110937 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 335801814932 ps |
| CPU time | 444.02 seconds |
| Started | Oct 09 06:23:53 AM UTC 24 |
| Finished | Oct 09 06:31:23 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260110937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.260110937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.739811423 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 323169785215 ps |
| CPU time | 211.47 seconds |
| Started | Oct 09 06:23:43 AM UTC 24 |
| Finished | Oct 09 06:27:17 AM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739811423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.739811423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3984529868 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 336115556260 ps |
| CPU time | 1030.09 seconds |
| Started | Oct 09 06:23:36 AM UTC 24 |
| Finished | Oct 09 06:40:57 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984529868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3984529868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1630898627 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 160583342870 ps |
| CPU time | 380.2 seconds |
| Started | Oct 09 06:23:36 AM UTC 24 |
| Finished | Oct 09 06:30:01 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630898627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1630898627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.222858447 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 604482018486 ps |
| CPU time | 689.24 seconds |
| Started | Oct 09 06:23:46 AM UTC 24 |
| Finished | Oct 09 06:35:23 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222858447 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.222858447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1225291552 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 111996695305 ps |
| CPU time | 614.6 seconds |
| Started | Oct 09 06:24:01 AM UTC 24 |
| Finished | Oct 09 06:34:22 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225291552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1225291552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.4119695077 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 34612858476 ps |
| CPU time | 139.98 seconds |
| Started | Oct 09 06:23:57 AM UTC 24 |
| Finished | Oct 09 06:26:19 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119695077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4119695077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.180602118 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3843183732 ps |
| CPU time | 4.49 seconds |
| Started | Oct 09 06:23:55 AM UTC 24 |
| Finished | Oct 09 06:24:00 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180602118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.180602118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1549710694 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5698494620 ps |
| CPU time | 6.4 seconds |
| Started | Oct 09 06:23:35 AM UTC 24 |
| Finished | Oct 09 06:23:42 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549710694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1549710694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.703291995 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 367280266030 ps |
| CPU time | 1119.2 seconds |
| Started | Oct 09 06:24:15 AM UTC 24 |
| Finished | Oct 09 06:43:06 AM UTC 24 |
| Peak memory | 213560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703291995 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.703291995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4150225258 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5971559528 ps |
| CPU time | 14.02 seconds |
| Started | Oct 09 06:24:05 AM UTC 24 |
| Finished | Oct 09 06:24:20 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4150225258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.adc_ctrl_stress_all_with_rand_reset.4150225258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3506603935 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 435350191 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 06:26:18 AM UTC 24 |
| Finished | Oct 09 06:26:21 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506603935 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3506603935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3757655142 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 373460795975 ps |
| CPU time | 125.49 seconds |
| Started | Oct 09 06:25:12 AM UTC 24 |
| Finished | Oct 09 06:27:19 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757655142 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3757655142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.1747206462 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 509014248122 ps |
| CPU time | 285.01 seconds |
| Started | Oct 09 06:25:29 AM UTC 24 |
| Finished | Oct 09 06:30:18 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747206462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1747206462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.843550913 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 324776021150 ps |
| CPU time | 734.99 seconds |
| Started | Oct 09 06:24:25 AM UTC 24 |
| Finished | Oct 09 06:36:48 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843550913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.843550913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.179883855 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 166567240355 ps |
| CPU time | 127.93 seconds |
| Started | Oct 09 06:24:28 AM UTC 24 |
| Finished | Oct 09 06:26:39 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179883855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.179883855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.343851120 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 328721067380 ps |
| CPU time | 730.44 seconds |
| Started | Oct 09 06:24:21 AM UTC 24 |
| Finished | Oct 09 06:36:39 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343851120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.343851120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.3686078388 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 481031722647 ps |
| CPU time | 1171.53 seconds |
| Started | Oct 09 06:24:22 AM UTC 24 |
| Finished | Oct 09 06:44:05 AM UTC 24 |
| Peak memory | 213560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686078388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.3686078388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2856537523 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 204950954904 ps |
| CPU time | 328.57 seconds |
| Started | Oct 09 06:25:06 AM UTC 24 |
| Finished | Oct 09 06:30:38 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856537523 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.2856537523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1463979730 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 91264391865 ps |
| CPU time | 534.74 seconds |
| Started | Oct 09 06:26:01 AM UTC 24 |
| Finished | Oct 09 06:35:02 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463979730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1463979730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1440992399 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 26056463420 ps |
| CPU time | 25.62 seconds |
| Started | Oct 09 06:25:38 AM UTC 24 |
| Finished | Oct 09 06:26:05 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440992399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1440992399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.556336360 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3827079938 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 06:25:33 AM UTC 24 |
| Finished | Oct 09 06:25:37 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556336360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.556336360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.319284984 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6064877498 ps |
| CPU time | 27.2 seconds |
| Started | Oct 09 06:24:21 AM UTC 24 |
| Finished | Oct 09 06:24:50 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319284984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.319284984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.474415105 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 255235432114 ps |
| CPU time | 412.58 seconds |
| Started | Oct 09 06:26:06 AM UTC 24 |
| Finished | Oct 09 06:33:04 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474415105 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.474415105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.7061181 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 16867003063 ps |
| CPU time | 10.02 seconds |
| Started | Oct 09 06:26:06 AM UTC 24 |
| Finished | Oct 09 06:26:18 AM UTC 24 |
| Peak memory | 220984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=7061181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.adc_ctrl_stress_all_with_rand_reset.7061181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.1298886443 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 494386648 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 06:27:20 AM UTC 24 |
| Finished | Oct 09 06:27:23 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298886443 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1298886443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.2185224237 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 359977112180 ps |
| CPU time | 73.66 seconds |
| Started | Oct 09 06:26:39 AM UTC 24 |
| Finished | Oct 09 06:27:54 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185224237 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.2185224237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.2476354398 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 385557821949 ps |
| CPU time | 290.67 seconds |
| Started | Oct 09 06:26:40 AM UTC 24 |
| Finished | Oct 09 06:31:34 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476354398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2476354398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3285080471 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 486422109574 ps |
| CPU time | 1461.85 seconds |
| Started | Oct 09 06:26:23 AM UTC 24 |
| Finished | Oct 09 06:50:59 AM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285080471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3285080471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3496728209 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 166473747955 ps |
| CPU time | 490.14 seconds |
| Started | Oct 09 06:26:27 AM UTC 24 |
| Finished | Oct 09 06:34:42 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496728209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.3496728209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1323182730 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 162523024861 ps |
| CPU time | 185.34 seconds |
| Started | Oct 09 06:26:19 AM UTC 24 |
| Finished | Oct 09 06:29:27 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323182730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1323182730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.3810199414 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 166423382729 ps |
| CPU time | 425.47 seconds |
| Started | Oct 09 06:26:22 AM UTC 24 |
| Finished | Oct 09 06:33:32 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810199414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.3810199414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3611043544 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 404501438785 ps |
| CPU time | 310.17 seconds |
| Started | Oct 09 06:26:35 AM UTC 24 |
| Finished | Oct 09 06:31:49 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611043544 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.3611043544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1238034217 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 90699103905 ps |
| CPU time | 381.42 seconds |
| Started | Oct 09 06:27:04 AM UTC 24 |
| Finished | Oct 09 06:33:30 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238034217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1238034217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2014851162 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 35093266607 ps |
| CPU time | 120.18 seconds |
| Started | Oct 09 06:26:47 AM UTC 24 |
| Finished | Oct 09 06:28:50 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014851162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2014851162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.103423660 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4188250546 ps |
| CPU time | 17.2 seconds |
| Started | Oct 09 06:26:45 AM UTC 24 |
| Finished | Oct 09 06:27:04 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103423660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.103423660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.30477593 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 5555270547 ps |
| CPU time | 17.86 seconds |
| Started | Oct 09 06:26:19 AM UTC 24 |
| Finished | Oct 09 06:26:38 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30477593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.30477593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3217792034 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 496789557150 ps |
| CPU time | 641.58 seconds |
| Started | Oct 09 06:27:18 AM UTC 24 |
| Finished | Oct 09 06:38:07 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217792034 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.3217792034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1925251904 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3608853573 ps |
| CPU time | 24.45 seconds |
| Started | Oct 09 06:27:13 AM UTC 24 |
| Finished | Oct 09 06:27:39 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1925251904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.adc_ctrl_stress_all_with_rand_reset.1925251904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3320712364 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 378545129 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:30 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320712364 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3320712364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2325397900 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 336228053304 ps |
| CPU time | 1000.91 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:24:22 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325397900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2325397900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.961012907 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 320288066476 ps |
| CPU time | 757.55 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:20:12 AM UTC 24 |
| Peak memory | 213428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961012907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.961012907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1565379646 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 162243374857 ps |
| CPU time | 74.35 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:08:46 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565379646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1565379646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2916559158 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 332255059496 ps |
| CPU time | 454.01 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:15:09 AM UTC 24 |
| Peak memory | 213632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916559158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.2916559158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1974705166 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 603014378411 ps |
| CPU time | 428.69 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:14:44 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974705166 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.1974705166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3436853166 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 117245162314 ps |
| CPU time | 438.57 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:14:53 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436853166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3436853166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2867379121 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 42856832903 ps |
| CPU time | 134.27 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:09:47 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867379121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2867379121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1989348194 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4164265031 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:34 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989348194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1989348194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.2506356311 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7666345817 ps |
| CPU time | 4.93 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:36 AM UTC 24 |
| Peak memory | 242840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506356311 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2506356311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.2317740491 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5786692447 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:35 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317740491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2317740491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1680596339 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8896789548 ps |
| CPU time | 19.9 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:49 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680596339 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.1680596339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3971746523 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 72702594717 ps |
| CPU time | 37.28 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:08:09 AM UTC 24 |
| Peak memory | 221012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3971746523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.adc_ctrl_stress_all_with_rand_reset.3971746523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.852604375 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 370354972 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 06:28:53 AM UTC 24 |
| Finished | Oct 09 06:28:55 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852604375 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.852604375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2498815505 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 499705291819 ps |
| CPU time | 74.43 seconds |
| Started | Oct 09 06:28:03 AM UTC 24 |
| Finished | Oct 09 06:29:19 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498815505 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.2498815505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.842135194 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 166734476013 ps |
| CPU time | 274.71 seconds |
| Started | Oct 09 06:28:38 AM UTC 24 |
| Finished | Oct 09 06:33:17 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842135194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.842135194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.1782308174 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 493354688398 ps |
| CPU time | 1342.68 seconds |
| Started | Oct 09 06:27:40 AM UTC 24 |
| Finished | Oct 09 06:50:16 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782308174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1782308174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2770464397 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 162897627273 ps |
| CPU time | 132.68 seconds |
| Started | Oct 09 06:27:44 AM UTC 24 |
| Finished | Oct 09 06:29:59 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770464397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.2770464397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.1913130040 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 323235452599 ps |
| CPU time | 282.19 seconds |
| Started | Oct 09 06:27:29 AM UTC 24 |
| Finished | Oct 09 06:32:15 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913130040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1913130040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.320577888 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 327802854641 ps |
| CPU time | 432.54 seconds |
| Started | Oct 09 06:27:35 AM UTC 24 |
| Finished | Oct 09 06:34:52 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320577888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.320577888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3071957715 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 612400216011 ps |
| CPU time | 518.36 seconds |
| Started | Oct 09 06:27:55 AM UTC 24 |
| Finished | Oct 09 06:36:39 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071957715 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.3071957715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.125405772 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 94073548856 ps |
| CPU time | 363.98 seconds |
| Started | Oct 09 06:28:49 AM UTC 24 |
| Finished | Oct 09 06:34:56 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125405772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.125405772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.3016501 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 43913610541 ps |
| CPU time | 98.28 seconds |
| Started | Oct 09 06:28:47 AM UTC 24 |
| Finished | Oct 09 06:30:28 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S EQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3016501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.2933558646 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4178696293 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 06:28:41 AM UTC 24 |
| Finished | Oct 09 06:28:47 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933558646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2933558646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.4121980945 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6095733813 ps |
| CPU time | 17.33 seconds |
| Started | Oct 09 06:27:25 AM UTC 24 |
| Finished | Oct 09 06:27:43 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121980945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4121980945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.691338275 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 340336722153 ps |
| CPU time | 893.03 seconds |
| Started | Oct 09 06:28:51 AM UTC 24 |
| Finished | Oct 09 06:43:52 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691338275 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.691338275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.920080078 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2021412299 ps |
| CPU time | 9.76 seconds |
| Started | Oct 09 06:28:51 AM UTC 24 |
| Finished | Oct 09 06:29:01 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=920080078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.920080078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.1277195488 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 571913907 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 06:30:29 AM UTC 24 |
| Finished | Oct 09 06:30:31 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277195488 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1277195488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.2031280564 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 166643709820 ps |
| CPU time | 173.73 seconds |
| Started | Oct 09 06:29:28 AM UTC 24 |
| Finished | Oct 09 06:32:25 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031280564 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.2031280564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.1054847756 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 494891602166 ps |
| CPU time | 188.25 seconds |
| Started | Oct 09 06:29:02 AM UTC 24 |
| Finished | Oct 09 06:32:13 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054847756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1054847756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3813266305 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 325188914348 ps |
| CPU time | 131.93 seconds |
| Started | Oct 09 06:29:02 AM UTC 24 |
| Finished | Oct 09 06:31:16 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813266305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.3813266305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.849667971 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 489857555375 ps |
| CPU time | 392.39 seconds |
| Started | Oct 09 06:29:02 AM UTC 24 |
| Finished | Oct 09 06:35:39 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849667971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.849667971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3831350461 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 369090887132 ps |
| CPU time | 289.09 seconds |
| Started | Oct 09 06:29:20 AM UTC 24 |
| Finished | Oct 09 06:34:13 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831350461 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.3831350461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3856544727 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 195898778909 ps |
| CPU time | 260.18 seconds |
| Started | Oct 09 06:29:28 AM UTC 24 |
| Finished | Oct 09 06:33:52 AM UTC 24 |
| Peak memory | 210668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856544727 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.3856544727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.1757957701 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 142888425257 ps |
| CPU time | 967.04 seconds |
| Started | Oct 09 06:30:10 AM UTC 24 |
| Finished | Oct 09 06:46:26 AM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757957701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1757957701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.775837733 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 42915535569 ps |
| CPU time | 20.68 seconds |
| Started | Oct 09 06:30:07 AM UTC 24 |
| Finished | Oct 09 06:30:29 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775837733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.775837733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.2988238619 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4746489321 ps |
| CPU time | 6.01 seconds |
| Started | Oct 09 06:30:02 AM UTC 24 |
| Finished | Oct 09 06:30:09 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988238619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2988238619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.437132657 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5839227625 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 06:28:56 AM UTC 24 |
| Finished | Oct 09 06:29:02 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437132657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.437132657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1752747012 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 392833310392 ps |
| CPU time | 176.76 seconds |
| Started | Oct 09 06:30:29 AM UTC 24 |
| Finished | Oct 09 06:33:29 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752747012 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.1752747012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.380038751 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 52323058783 ps |
| CPU time | 33.97 seconds |
| Started | Oct 09 06:30:19 AM UTC 24 |
| Finished | Oct 09 06:30:55 AM UTC 24 |
| Peak memory | 220980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=380038751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.380038751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.2855027803 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 329214358 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 06:31:56 AM UTC 24 |
| Finished | Oct 09 06:32:01 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855027803 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2855027803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1434565693 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 161840757240 ps |
| CPU time | 66.59 seconds |
| Started | Oct 09 06:31:17 AM UTC 24 |
| Finished | Oct 09 06:32:25 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434565693 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.1434565693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.2691768918 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 165248162123 ps |
| CPU time | 107.62 seconds |
| Started | Oct 09 06:30:46 AM UTC 24 |
| Finished | Oct 09 06:32:36 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691768918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2691768918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2754280150 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 168741075988 ps |
| CPU time | 131.74 seconds |
| Started | Oct 09 06:30:55 AM UTC 24 |
| Finished | Oct 09 06:33:09 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754280150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.2754280150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.474429532 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 485892298497 ps |
| CPU time | 448.66 seconds |
| Started | Oct 09 06:30:39 AM UTC 24 |
| Finished | Oct 09 06:38:13 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474429532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.474429532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.4164602430 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 159483125974 ps |
| CPU time | 399.49 seconds |
| Started | Oct 09 06:30:44 AM UTC 24 |
| Finished | Oct 09 06:37:29 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164602430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.4164602430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1601238846 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 210575319944 ps |
| CPU time | 177.7 seconds |
| Started | Oct 09 06:31:09 AM UTC 24 |
| Finished | Oct 09 06:34:09 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601238846 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.1601238846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.4007469240 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 73340367058 ps |
| CPU time | 354.35 seconds |
| Started | Oct 09 06:31:39 AM UTC 24 |
| Finished | Oct 09 06:37:38 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007469240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4007469240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.3388490892 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 23657300178 ps |
| CPU time | 7.18 seconds |
| Started | Oct 09 06:31:38 AM UTC 24 |
| Finished | Oct 09 06:31:46 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388490892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3388490892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.4259331927 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4765520227 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 06:31:35 AM UTC 24 |
| Finished | Oct 09 06:31:38 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259331927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4259331927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.2625143604 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6069306840 ps |
| CPU time | 10.2 seconds |
| Started | Oct 09 06:30:32 AM UTC 24 |
| Finished | Oct 09 06:30:43 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625143604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2625143604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.115707444 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 357875269994 ps |
| CPU time | 1041.1 seconds |
| Started | Oct 09 06:31:49 AM UTC 24 |
| Finished | Oct 09 06:49:21 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115707444 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.115707444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2166130954 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 16834597268 ps |
| CPU time | 21.12 seconds |
| Started | Oct 09 06:31:47 AM UTC 24 |
| Finished | Oct 09 06:32:10 AM UTC 24 |
| Peak memory | 221400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2166130954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.adc_ctrl_stress_all_with_rand_reset.2166130954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.3041254999 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 457681080 ps |
| CPU time | 2.75 seconds |
| Started | Oct 09 06:33:29 AM UTC 24 |
| Finished | Oct 09 06:33:32 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041254999 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3041254999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1139432762 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 166082391782 ps |
| CPU time | 460.64 seconds |
| Started | Oct 09 06:32:37 AM UTC 24 |
| Finished | Oct 09 06:40:23 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139432762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1139432762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.4253282763 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 164247217944 ps |
| CPU time | 175.11 seconds |
| Started | Oct 09 06:32:14 AM UTC 24 |
| Finished | Oct 09 06:35:12 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253282763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4253282763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1061242654 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 329562640633 ps |
| CPU time | 985.33 seconds |
| Started | Oct 09 06:32:16 AM UTC 24 |
| Finished | Oct 09 06:48:52 AM UTC 24 |
| Peak memory | 213276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061242654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.1061242654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.238902662 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 329526218209 ps |
| CPU time | 749.42 seconds |
| Started | Oct 09 06:32:11 AM UTC 24 |
| Finished | Oct 09 06:44:48 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238902662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.238902662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.431189034 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 333881713393 ps |
| CPU time | 493.2 seconds |
| Started | Oct 09 06:32:11 AM UTC 24 |
| Finished | Oct 09 06:40:30 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431189034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.431189034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.1530487110 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 347356163399 ps |
| CPU time | 114.57 seconds |
| Started | Oct 09 06:32:26 AM UTC 24 |
| Finished | Oct 09 06:34:23 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530487110 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.1530487110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4075000929 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 191862557048 ps |
| CPU time | 126.74 seconds |
| Started | Oct 09 06:32:26 AM UTC 24 |
| Finished | Oct 09 06:34:35 AM UTC 24 |
| Peak memory | 210660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075000929 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.4075000929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2765470092 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 35942096117 ps |
| CPU time | 58.58 seconds |
| Started | Oct 09 06:32:58 AM UTC 24 |
| Finished | Oct 09 06:33:58 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765470092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2765470092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.3824645161 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4641812682 ps |
| CPU time | 12.16 seconds |
| Started | Oct 09 06:32:44 AM UTC 24 |
| Finished | Oct 09 06:32:57 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824645161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3824645161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.3739478336 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 5969989027 ps |
| CPU time | 6.88 seconds |
| Started | Oct 09 06:32:01 AM UTC 24 |
| Finished | Oct 09 06:32:10 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739478336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3739478336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.586236447 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4383742381 ps |
| CPU time | 16.01 seconds |
| Started | Oct 09 06:33:10 AM UTC 24 |
| Finished | Oct 09 06:33:28 AM UTC 24 |
| Peak memory | 221648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=586236447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.586236447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.3366126526 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 504166235 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 06:34:23 AM UTC 24 |
| Finished | Oct 09 06:34:26 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366126526 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3366126526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2490711706 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 511193533498 ps |
| CPU time | 1507.69 seconds |
| Started | Oct 09 06:33:57 AM UTC 24 |
| Finished | Oct 09 06:59:21 AM UTC 24 |
| Peak memory | 213332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490711706 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.2490711706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.131049074 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 166418060513 ps |
| CPU time | 220.75 seconds |
| Started | Oct 09 06:33:59 AM UTC 24 |
| Finished | Oct 09 06:37:43 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131049074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.131049074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.3628974250 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 160924668766 ps |
| CPU time | 429.09 seconds |
| Started | Oct 09 06:33:34 AM UTC 24 |
| Finished | Oct 09 06:40:48 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628974250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3628974250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4010889148 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 163584586926 ps |
| CPU time | 448.17 seconds |
| Started | Oct 09 06:33:50 AM UTC 24 |
| Finished | Oct 09 06:41:23 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010889148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.4010889148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.4162791386 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 166044577346 ps |
| CPU time | 189.85 seconds |
| Started | Oct 09 06:33:31 AM UTC 24 |
| Finished | Oct 09 06:36:43 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162791386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4162791386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.1708289727 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 163050434149 ps |
| CPU time | 130.85 seconds |
| Started | Oct 09 06:33:33 AM UTC 24 |
| Finished | Oct 09 06:35:46 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708289727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.1708289727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.2285904621 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 666655280478 ps |
| CPU time | 790.7 seconds |
| Started | Oct 09 06:33:53 AM UTC 24 |
| Finished | Oct 09 06:47:12 AM UTC 24 |
| Peak memory | 213624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285904621 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.2285904621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4000560645 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 201242865579 ps |
| CPU time | 480.58 seconds |
| Started | Oct 09 06:33:54 AM UTC 24 |
| Finished | Oct 09 06:42:00 AM UTC 24 |
| Peak memory | 210668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000560645 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.4000560645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.943304313 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 67750082251 ps |
| CPU time | 296.14 seconds |
| Started | Oct 09 06:34:12 AM UTC 24 |
| Finished | Oct 09 06:39:11 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943304313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.943304313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1741623945 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 31868680559 ps |
| CPU time | 66.87 seconds |
| Started | Oct 09 06:34:10 AM UTC 24 |
| Finished | Oct 09 06:35:19 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741623945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1741623945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.3412766829 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3061090287 ps |
| CPU time | 11.85 seconds |
| Started | Oct 09 06:34:08 AM UTC 24 |
| Finished | Oct 09 06:34:21 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412766829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3412766829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.2524436888 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5876712583 ps |
| CPU time | 25.32 seconds |
| Started | Oct 09 06:33:30 AM UTC 24 |
| Finished | Oct 09 06:33:56 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524436888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2524436888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1438947352 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2715801980 ps |
| CPU time | 7.36 seconds |
| Started | Oct 09 06:34:15 AM UTC 24 |
| Finished | Oct 09 06:34:23 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1438947352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.adc_ctrl_stress_all_with_rand_reset.1438947352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2420541468 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 364625291 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:35:20 AM UTC 24 |
| Finished | Oct 09 06:35:22 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420541468 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2420541468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.1750016032 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 495919997546 ps |
| CPU time | 356.76 seconds |
| Started | Oct 09 06:34:53 AM UTC 24 |
| Finished | Oct 09 06:40:55 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750016032 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.1750016032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3382265493 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 578393437091 ps |
| CPU time | 170.97 seconds |
| Started | Oct 09 06:34:58 AM UTC 24 |
| Finished | Oct 09 06:37:51 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382265493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3382265493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.1964595066 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 159687396448 ps |
| CPU time | 41.31 seconds |
| Started | Oct 09 06:34:36 AM UTC 24 |
| Finished | Oct 09 06:35:19 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964595066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1964595066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.836489314 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 499886331009 ps |
| CPU time | 1362.89 seconds |
| Started | Oct 09 06:34:39 AM UTC 24 |
| Finished | Oct 09 06:57:36 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836489314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.836489314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1933501609 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 328871072607 ps |
| CPU time | 684.99 seconds |
| Started | Oct 09 06:34:24 AM UTC 24 |
| Finished | Oct 09 06:45:56 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933501609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1933501609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.2902738077 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 496510019140 ps |
| CPU time | 436.44 seconds |
| Started | Oct 09 06:34:27 AM UTC 24 |
| Finished | Oct 09 06:41:49 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902738077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.2902738077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1169996194 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 690385333732 ps |
| CPU time | 432.47 seconds |
| Started | Oct 09 06:34:39 AM UTC 24 |
| Finished | Oct 09 06:41:56 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169996194 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.1169996194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3453385194 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 401626057215 ps |
| CPU time | 497.54 seconds |
| Started | Oct 09 06:34:43 AM UTC 24 |
| Finished | Oct 09 06:43:07 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453385194 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.3453385194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.235679899 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 96173219665 ps |
| CPU time | 508.65 seconds |
| Started | Oct 09 06:35:14 AM UTC 24 |
| Finished | Oct 09 06:43:48 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235679899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.235679899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.3136243925 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 42410148028 ps |
| CPU time | 97.33 seconds |
| Started | Oct 09 06:35:13 AM UTC 24 |
| Finished | Oct 09 06:36:52 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136243925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3136243925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1211874739 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3885891015 ps |
| CPU time | 8.84 seconds |
| Started | Oct 09 06:35:03 AM UTC 24 |
| Finished | Oct 09 06:35:12 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211874739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1211874739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.1927782964 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5851610162 ps |
| CPU time | 13.25 seconds |
| Started | Oct 09 06:34:24 AM UTC 24 |
| Finished | Oct 09 06:34:38 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927782964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1927782964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1055791018 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 978204382398 ps |
| CPU time | 940.79 seconds |
| Started | Oct 09 06:35:20 AM UTC 24 |
| Finished | Oct 09 06:51:10 AM UTC 24 |
| Peak memory | 224004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055791018 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.1055791018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1276172772 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 65197526912 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 06:35:19 AM UTC 24 |
| Finished | Oct 09 06:35:32 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1276172772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.adc_ctrl_stress_all_with_rand_reset.1276172772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.4135359298 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 401249870 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 06:36:40 AM UTC 24 |
| Finished | Oct 09 06:36:43 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135359298 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4135359298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.3714256759 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 159529733363 ps |
| CPU time | 166.36 seconds |
| Started | Oct 09 06:35:56 AM UTC 24 |
| Finished | Oct 09 06:38:45 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714256759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3714256759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3223855209 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 487831432049 ps |
| CPU time | 382.17 seconds |
| Started | Oct 09 06:35:40 AM UTC 24 |
| Finished | Oct 09 06:42:07 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223855209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.3223855209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.1114462431 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 166203919144 ps |
| CPU time | 71.92 seconds |
| Started | Oct 09 06:35:24 AM UTC 24 |
| Finished | Oct 09 06:36:38 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114462431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1114462431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.3097070017 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 170840944950 ps |
| CPU time | 146.49 seconds |
| Started | Oct 09 06:35:24 AM UTC 24 |
| Finished | Oct 09 06:37:53 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097070017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.3097070017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.530775083 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 370964062470 ps |
| CPU time | 1060.5 seconds |
| Started | Oct 09 06:35:43 AM UTC 24 |
| Finished | Oct 09 06:53:35 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530775083 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.530775083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3369444047 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 199658598989 ps |
| CPU time | 451.08 seconds |
| Started | Oct 09 06:35:46 AM UTC 24 |
| Finished | Oct 09 06:43:22 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369444047 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.3369444047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.1829046248 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 113731848623 ps |
| CPU time | 540.62 seconds |
| Started | Oct 09 06:36:22 AM UTC 24 |
| Finished | Oct 09 06:45:28 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829046248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1829046248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.3367816351 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 40678763497 ps |
| CPU time | 121.36 seconds |
| Started | Oct 09 06:36:17 AM UTC 24 |
| Finished | Oct 09 06:38:21 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367816351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3367816351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.975847054 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 3934444134 ps |
| CPU time | 17.84 seconds |
| Started | Oct 09 06:35:57 AM UTC 24 |
| Finished | Oct 09 06:36:16 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975847054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.975847054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.1702135231 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5866861477 ps |
| CPU time | 20.69 seconds |
| Started | Oct 09 06:35:23 AM UTC 24 |
| Finished | Oct 09 06:35:45 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702135231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1702135231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.974927715 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 325845172251 ps |
| CPU time | 772.04 seconds |
| Started | Oct 09 06:36:40 AM UTC 24 |
| Finished | Oct 09 06:49:40 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974927715 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.974927715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1419558395 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 10756333988 ps |
| CPU time | 14.28 seconds |
| Started | Oct 09 06:36:38 AM UTC 24 |
| Finished | Oct 09 06:36:54 AM UTC 24 |
| Peak memory | 221064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1419558395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.adc_ctrl_stress_all_with_rand_reset.1419558395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.2179341135 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 350132165 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 06:37:51 AM UTC 24 |
| Finished | Oct 09 06:37:54 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179341135 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2179341135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.4018101661 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 159755448461 ps |
| CPU time | 103.89 seconds |
| Started | Oct 09 06:37:23 AM UTC 24 |
| Finished | Oct 09 06:39:09 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018101661 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.4018101661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.4156367588 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 516421712527 ps |
| CPU time | 1528.84 seconds |
| Started | Oct 09 06:37:28 AM UTC 24 |
| Finished | Oct 09 07:03:12 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156367588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4156367588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.2058116413 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 329991137313 ps |
| CPU time | 62.75 seconds |
| Started | Oct 09 06:36:53 AM UTC 24 |
| Finished | Oct 09 06:37:57 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058116413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2058116413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3450437673 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 167424125446 ps |
| CPU time | 476.78 seconds |
| Started | Oct 09 06:36:53 AM UTC 24 |
| Finished | Oct 09 06:44:55 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450437673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.3450437673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.136536920 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 160415695565 ps |
| CPU time | 412.38 seconds |
| Started | Oct 09 06:36:44 AM UTC 24 |
| Finished | Oct 09 06:43:42 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136536920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.136536920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.263653448 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 495773754822 ps |
| CPU time | 253.94 seconds |
| Started | Oct 09 06:36:50 AM UTC 24 |
| Finished | Oct 09 06:41:07 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263653448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.263653448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.2048846605 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 432368806016 ps |
| CPU time | 296.11 seconds |
| Started | Oct 09 06:36:55 AM UTC 24 |
| Finished | Oct 09 06:41:55 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048846605 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.2048846605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.536591142 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 198131360933 ps |
| CPU time | 101.79 seconds |
| Started | Oct 09 06:37:11 AM UTC 24 |
| Finished | Oct 09 06:38:55 AM UTC 24 |
| Peak memory | 210752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536591142 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.536591142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.1713842661 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 63152675961 ps |
| CPU time | 471.1 seconds |
| Started | Oct 09 06:37:39 AM UTC 24 |
| Finished | Oct 09 06:45:37 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713842661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1713842661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.2805206178 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 36223617000 ps |
| CPU time | 10.59 seconds |
| Started | Oct 09 06:37:36 AM UTC 24 |
| Finished | Oct 09 06:37:48 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805206178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2805206178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.1731653491 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3564257516 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 06:37:30 AM UTC 24 |
| Finished | Oct 09 06:37:36 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731653491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1731653491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.634289318 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5945182186 ps |
| CPU time | 25.3 seconds |
| Started | Oct 09 06:36:43 AM UTC 24 |
| Finished | Oct 09 06:37:10 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634289318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.634289318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.4094694887 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 329462445083 ps |
| CPU time | 314.4 seconds |
| Started | Oct 09 06:37:48 AM UTC 24 |
| Finished | Oct 09 06:43:06 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094694887 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.4094694887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3464635537 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2337012717 ps |
| CPU time | 8.65 seconds |
| Started | Oct 09 06:37:44 AM UTC 24 |
| Finished | Oct 09 06:37:54 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3464635537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.adc_ctrl_stress_all_with_rand_reset.3464635537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.159093616 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 506376949 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 06:39:21 AM UTC 24 |
| Finished | Oct 09 06:39:24 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159093616 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.159093616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.399428344 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 419944808836 ps |
| CPU time | 310.8 seconds |
| Started | Oct 09 06:38:14 AM UTC 24 |
| Finished | Oct 09 06:43:29 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399428344 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.399428344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.4131167488 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 199028980037 ps |
| CPU time | 538.08 seconds |
| Started | Oct 09 06:38:21 AM UTC 24 |
| Finished | Oct 09 06:47:26 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131167488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4131167488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.1466574124 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 161955471056 ps |
| CPU time | 285.09 seconds |
| Started | Oct 09 06:37:55 AM UTC 24 |
| Finished | Oct 09 06:42:44 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466574124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1466574124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1541143625 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 326656992814 ps |
| CPU time | 1069.92 seconds |
| Started | Oct 09 06:37:58 AM UTC 24 |
| Finished | Oct 09 06:55:59 AM UTC 24 |
| Peak memory | 213308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541143625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.1541143625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.2568967132 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 327329025515 ps |
| CPU time | 171.53 seconds |
| Started | Oct 09 06:37:54 AM UTC 24 |
| Finished | Oct 09 06:40:48 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568967132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2568967132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.2795408892 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 330992583177 ps |
| CPU time | 427.71 seconds |
| Started | Oct 09 06:37:55 AM UTC 24 |
| Finished | Oct 09 06:45:07 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795408892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.2795408892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4217149327 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 190921360681 ps |
| CPU time | 510.26 seconds |
| Started | Oct 09 06:37:58 AM UTC 24 |
| Finished | Oct 09 06:46:34 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217149327 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4217149327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3029284432 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 622028021368 ps |
| CPU time | 1767.37 seconds |
| Started | Oct 09 06:38:08 AM UTC 24 |
| Finished | Oct 09 07:07:54 AM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029284432 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.3029284432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.2679134294 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 124451957574 ps |
| CPU time | 771.52 seconds |
| Started | Oct 09 06:39:07 AM UTC 24 |
| Finished | Oct 09 06:52:08 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679134294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2679134294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.593115007 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 35674517961 ps |
| CPU time | 75.83 seconds |
| Started | Oct 09 06:38:55 AM UTC 24 |
| Finished | Oct 09 06:40:13 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593115007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.593115007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.307482199 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4153722045 ps |
| CPU time | 18.84 seconds |
| Started | Oct 09 06:38:46 AM UTC 24 |
| Finished | Oct 09 06:39:06 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307482199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.307482199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.3014440344 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 5732902720 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 06:37:53 AM UTC 24 |
| Finished | Oct 09 06:37:57 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014440344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3014440344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3599237001 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2012886422 ps |
| CPU time | 8.84 seconds |
| Started | Oct 09 06:39:09 AM UTC 24 |
| Finished | Oct 09 06:39:20 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3599237001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.adc_ctrl_stress_all_with_rand_reset.3599237001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.2739183078 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 498119264 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 06:41:21 AM UTC 24 |
| Finished | Oct 09 06:41:24 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739183078 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2739183078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.2785338025 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 349713079812 ps |
| CPU time | 252.18 seconds |
| Started | Oct 09 06:40:48 AM UTC 24 |
| Finished | Oct 09 06:45:04 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785338025 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.2785338025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.707419374 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 328231518782 ps |
| CPU time | 278.18 seconds |
| Started | Oct 09 06:40:49 AM UTC 24 |
| Finished | Oct 09 06:45:32 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707419374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.707419374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1099907194 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 506954957913 ps |
| CPU time | 796.81 seconds |
| Started | Oct 09 06:40:14 AM UTC 24 |
| Finished | Oct 09 06:53:39 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099907194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1099907194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2852198135 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 332141117896 ps |
| CPU time | 995.36 seconds |
| Started | Oct 09 06:40:24 AM UTC 24 |
| Finished | Oct 09 06:57:10 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852198135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.2852198135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.950849152 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 168834437965 ps |
| CPU time | 88.4 seconds |
| Started | Oct 09 06:39:51 AM UTC 24 |
| Finished | Oct 09 06:41:21 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950849152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.950849152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1915229344 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 500669520919 ps |
| CPU time | 1496.52 seconds |
| Started | Oct 09 06:40:03 AM UTC 24 |
| Finished | Oct 09 07:05:15 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915229344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.1915229344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.3380937360 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 383330344361 ps |
| CPU time | 596.01 seconds |
| Started | Oct 09 06:40:30 AM UTC 24 |
| Finished | Oct 09 06:50:33 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380937360 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.3380937360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3516724420 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 192881661893 ps |
| CPU time | 315.4 seconds |
| Started | Oct 09 06:40:47 AM UTC 24 |
| Finished | Oct 09 06:46:07 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516724420 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.3516724420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.3121565500 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 77063890830 ps |
| CPU time | 468.58 seconds |
| Started | Oct 09 06:40:58 AM UTC 24 |
| Finished | Oct 09 06:48:52 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121565500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3121565500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.4258140944 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 31085248918 ps |
| CPU time | 32.86 seconds |
| Started | Oct 09 06:40:56 AM UTC 24 |
| Finished | Oct 09 06:41:30 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258140944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4258140944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.2156931858 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2731279177 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 06:40:55 AM UTC 24 |
| Finished | Oct 09 06:41:02 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156931858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2156931858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.3479788524 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5708353732 ps |
| CPU time | 23.46 seconds |
| Started | Oct 09 06:39:26 AM UTC 24 |
| Finished | Oct 09 06:39:50 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479788524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3479788524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3072656440 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3199976136 ps |
| CPU time | 16.18 seconds |
| Started | Oct 09 06:41:03 AM UTC 24 |
| Finished | Oct 09 06:41:20 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3072656440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.adc_ctrl_stress_all_with_rand_reset.3072656440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2941377423 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 507222204 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:07:33 AM UTC 24 |
| Finished | Oct 09 06:07:46 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941377423 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2941377423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2563085729 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 331352031825 ps |
| CPU time | 838.22 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:21:15 AM UTC 24 |
| Peak memory | 213312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563085729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.2563085729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.857389113 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 317184285136 ps |
| CPU time | 213.14 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:11:04 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857389113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.857389113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.507572695 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 498493878246 ps |
| CPU time | 1498.67 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:32:32 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507572695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.507572695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1231410220 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 630889869439 ps |
| CPU time | 401.43 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:13:54 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231410220 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.1231410220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1906701804 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 33442397442 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 06:07:17 AM UTC 24 |
| Finished | Oct 09 06:07:42 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906701804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1906701804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.1889149400 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7781361000 ps |
| CPU time | 16.29 seconds |
| Started | Oct 09 06:07:31 AM UTC 24 |
| Finished | Oct 09 06:07:55 AM UTC 24 |
| Peak memory | 242848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889149400 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1889149400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2953367102 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6012958425 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 06:07:07 AM UTC 24 |
| Finished | Oct 09 06:07:35 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953367102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2953367102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1026160304 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 236209144679 ps |
| CPU time | 164.16 seconds |
| Started | Oct 09 06:07:31 AM UTC 24 |
| Finished | Oct 09 06:10:25 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026160304 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.1026160304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.560120916 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 347351644 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 06:42:48 AM UTC 24 |
| Finished | Oct 09 06:42:52 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560120916 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.560120916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.3692328059 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 188037378511 ps |
| CPU time | 310.28 seconds |
| Started | Oct 09 06:41:58 AM UTC 24 |
| Finished | Oct 09 06:47:12 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692328059 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.3692328059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.3033820087 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 175404995595 ps |
| CPU time | 461.89 seconds |
| Started | Oct 09 06:42:01 AM UTC 24 |
| Finished | Oct 09 06:49:48 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033820087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3033820087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.727958980 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 160246726738 ps |
| CPU time | 535.75 seconds |
| Started | Oct 09 06:41:30 AM UTC 24 |
| Finished | Oct 09 06:50:32 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727958980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.727958980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.284182933 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 479559089038 ps |
| CPU time | 423.67 seconds |
| Started | Oct 09 06:41:31 AM UTC 24 |
| Finished | Oct 09 06:48:40 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284182933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.284182933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.2209083439 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 163485023225 ps |
| CPU time | 454.59 seconds |
| Started | Oct 09 06:41:25 AM UTC 24 |
| Finished | Oct 09 06:49:05 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209083439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.2209083439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.121023652 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 371807143599 ps |
| CPU time | 338.53 seconds |
| Started | Oct 09 06:41:50 AM UTC 24 |
| Finished | Oct 09 06:47:32 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121023652 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.121023652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.4230740261 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 613213938308 ps |
| CPU time | 906.45 seconds |
| Started | Oct 09 06:41:56 AM UTC 24 |
| Finished | Oct 09 06:57:11 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230740261 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.4230740261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.1127630128 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 98560175418 ps |
| CPU time | 356.74 seconds |
| Started | Oct 09 06:42:08 AM UTC 24 |
| Finished | Oct 09 06:48:09 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127630128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1127630128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2031096783 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 22523836162 ps |
| CPU time | 83.79 seconds |
| Started | Oct 09 06:42:07 AM UTC 24 |
| Finished | Oct 09 06:43:32 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031096783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2031096783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.1583595413 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3854681482 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 06:42:03 AM UTC 24 |
| Finished | Oct 09 06:42:06 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583595413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1583595413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.2996170518 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 5644336089 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 06:41:22 AM UTC 24 |
| Finished | Oct 09 06:41:30 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996170518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2996170518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.2034205526 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 173791946392 ps |
| CPU time | 152.92 seconds |
| Started | Oct 09 06:42:44 AM UTC 24 |
| Finished | Oct 09 06:45:20 AM UTC 24 |
| Peak memory | 210660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034205526 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.2034205526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2674893108 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2514249407 ps |
| CPU time | 14.75 seconds |
| Started | Oct 09 06:42:31 AM UTC 24 |
| Finished | Oct 09 06:42:47 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2674893108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.adc_ctrl_stress_all_with_rand_reset.2674893108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.2599818361 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 435932993 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 06:44:05 AM UTC 24 |
| Finished | Oct 09 06:44:07 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599818361 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2599818361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.178361046 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 328325251677 ps |
| CPU time | 234.32 seconds |
| Started | Oct 09 06:43:33 AM UTC 24 |
| Finished | Oct 09 06:47:31 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178361046 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.178361046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.3004782122 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 179533146374 ps |
| CPU time | 27.2 seconds |
| Started | Oct 09 06:43:42 AM UTC 24 |
| Finished | Oct 09 06:44:11 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004782122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3004782122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3932388419 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 324981655045 ps |
| CPU time | 780.4 seconds |
| Started | Oct 09 06:43:08 AM UTC 24 |
| Finished | Oct 09 06:56:16 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932388419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3932388419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.32436237 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 323847490671 ps |
| CPU time | 465.22 seconds |
| Started | Oct 09 06:43:08 AM UTC 24 |
| Finished | Oct 09 06:50:58 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32436237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.32436237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.4024111811 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 496218257083 ps |
| CPU time | 404.31 seconds |
| Started | Oct 09 06:42:59 AM UTC 24 |
| Finished | Oct 09 06:49:49 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024111811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4024111811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.853649428 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 163765511010 ps |
| CPU time | 447.98 seconds |
| Started | Oct 09 06:43:07 AM UTC 24 |
| Finished | Oct 09 06:50:40 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853649428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.853649428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.3722091450 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 377182386423 ps |
| CPU time | 262.7 seconds |
| Started | Oct 09 06:43:23 AM UTC 24 |
| Finished | Oct 09 06:47:49 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722091450 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.3722091450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.829384329 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 583285889038 ps |
| CPU time | 506.02 seconds |
| Started | Oct 09 06:43:30 AM UTC 24 |
| Finished | Oct 09 06:52:02 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829384329 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.829384329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.4109202985 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 40091291402 ps |
| CPU time | 149.41 seconds |
| Started | Oct 09 06:43:49 AM UTC 24 |
| Finished | Oct 09 06:46:21 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109202985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4109202985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.809693929 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 3205767952 ps |
| CPU time | 7.38 seconds |
| Started | Oct 09 06:43:47 AM UTC 24 |
| Finished | Oct 09 06:43:56 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809693929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.809693929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.3257164430 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 6038001637 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 06:42:52 AM UTC 24 |
| Finished | Oct 09 06:42:58 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257164430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3257164430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3110651014 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 294907645417 ps |
| CPU time | 1123.87 seconds |
| Started | Oct 09 06:43:58 AM UTC 24 |
| Finished | Oct 09 07:02:53 AM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110651014 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.3110651014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2319562115 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 32652935939 ps |
| CPU time | 6.22 seconds |
| Started | Oct 09 06:43:56 AM UTC 24 |
| Finished | Oct 09 06:44:04 AM UTC 24 |
| Peak memory | 220988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2319562115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.adc_ctrl_stress_all_with_rand_reset.2319562115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.3338242587 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 533924122 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 06:45:56 AM UTC 24 |
| Finished | Oct 09 06:45:59 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338242587 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3338242587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.3378628645 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 377448575644 ps |
| CPU time | 257.29 seconds |
| Started | Oct 09 06:45:08 AM UTC 24 |
| Finished | Oct 09 06:49:29 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378628645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3378628645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.2769261823 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 490707824708 ps |
| CPU time | 1413.47 seconds |
| Started | Oct 09 06:44:20 AM UTC 24 |
| Finished | Oct 09 07:08:08 AM UTC 24 |
| Peak memory | 213308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769261823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2769261823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.999694158 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 323101032391 ps |
| CPU time | 783.5 seconds |
| Started | Oct 09 06:44:40 AM UTC 24 |
| Finished | Oct 09 06:57:52 AM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999694158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.999694158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2800653978 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 165949571808 ps |
| CPU time | 119.11 seconds |
| Started | Oct 09 06:44:08 AM UTC 24 |
| Finished | Oct 09 06:46:09 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800653978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2800653978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.1017557704 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 331203988427 ps |
| CPU time | 242.01 seconds |
| Started | Oct 09 06:44:12 AM UTC 24 |
| Finished | Oct 09 06:48:17 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017557704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.1017557704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1961504506 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 403055511825 ps |
| CPU time | 1184.82 seconds |
| Started | Oct 09 06:44:49 AM UTC 24 |
| Finished | Oct 09 07:04:46 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961504506 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.1961504506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2435885177 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 601761082140 ps |
| CPU time | 1609.76 seconds |
| Started | Oct 09 06:44:56 AM UTC 24 |
| Finished | Oct 09 07:12:02 AM UTC 24 |
| Peak memory | 213280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435885177 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.2435885177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1031578801 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 129319543161 ps |
| CPU time | 544.81 seconds |
| Started | Oct 09 06:45:33 AM UTC 24 |
| Finished | Oct 09 06:54:43 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031578801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1031578801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.4030813497 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 44222949334 ps |
| CPU time | 25.85 seconds |
| Started | Oct 09 06:45:29 AM UTC 24 |
| Finished | Oct 09 06:45:56 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030813497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4030813497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.1454314402 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2821027632 ps |
| CPU time | 13.93 seconds |
| Started | Oct 09 06:45:20 AM UTC 24 |
| Finished | Oct 09 06:45:36 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454314402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1454314402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.235425185 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 5919017405 ps |
| CPU time | 12.05 seconds |
| Started | Oct 09 06:44:06 AM UTC 24 |
| Finished | Oct 09 06:44:19 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235425185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.235425185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.694517657 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 11080899797 ps |
| CPU time | 23.56 seconds |
| Started | Oct 09 06:45:38 AM UTC 24 |
| Finished | Oct 09 06:46:03 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694517657 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.694517657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1845726722 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3391550749 ps |
| CPU time | 18.94 seconds |
| Started | Oct 09 06:45:37 AM UTC 24 |
| Finished | Oct 09 06:45:57 AM UTC 24 |
| Peak memory | 221260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1845726722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.adc_ctrl_stress_all_with_rand_reset.1845726722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.2054328345 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 331437439 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:47:26 AM UTC 24 |
| Finished | Oct 09 06:47:28 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054328345 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2054328345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.2612228005 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 553862477525 ps |
| CPU time | 1615.05 seconds |
| Started | Oct 09 06:46:22 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612228005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2612228005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.2479043759 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 162356667328 ps |
| CPU time | 509.98 seconds |
| Started | Oct 09 06:46:00 AM UTC 24 |
| Finished | Oct 09 06:54:36 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479043759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2479043759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4038671106 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 161342797203 ps |
| CPU time | 434.29 seconds |
| Started | Oct 09 06:46:03 AM UTC 24 |
| Finished | Oct 09 06:53:23 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038671106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.4038671106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1638571106 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 483726069183 ps |
| CPU time | 353.55 seconds |
| Started | Oct 09 06:45:57 AM UTC 24 |
| Finished | Oct 09 06:51:55 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638571106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1638571106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.1332204311 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 327526287153 ps |
| CPU time | 818.93 seconds |
| Started | Oct 09 06:45:58 AM UTC 24 |
| Finished | Oct 09 06:59:45 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332204311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.1332204311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1841931370 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 656291682094 ps |
| CPU time | 107.02 seconds |
| Started | Oct 09 06:46:07 AM UTC 24 |
| Finished | Oct 09 06:47:56 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841931370 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.1841931370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3139720584 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 621224204165 ps |
| CPU time | 663.76 seconds |
| Started | Oct 09 06:46:10 AM UTC 24 |
| Finished | Oct 09 06:57:22 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139720584 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.3139720584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.1789784506 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 82305560698 ps |
| CPU time | 399.88 seconds |
| Started | Oct 09 06:46:49 AM UTC 24 |
| Finished | Oct 09 06:53:34 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789784506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1789784506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3706241805 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 21839300810 ps |
| CPU time | 76.89 seconds |
| Started | Oct 09 06:46:35 AM UTC 24 |
| Finished | Oct 09 06:47:53 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706241805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3706241805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1878645335 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4460568758 ps |
| CPU time | 18.8 seconds |
| Started | Oct 09 06:46:28 AM UTC 24 |
| Finished | Oct 09 06:46:48 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878645335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1878645335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1552565012 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5686948362 ps |
| CPU time | 12.23 seconds |
| Started | Oct 09 06:45:57 AM UTC 24 |
| Finished | Oct 09 06:46:11 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552565012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1552565012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.1573772540 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 504182049112 ps |
| CPU time | 287.77 seconds |
| Started | Oct 09 06:47:13 AM UTC 24 |
| Finished | Oct 09 06:52:05 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573772540 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.1573772540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3818762915 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1966233854 ps |
| CPU time | 14.7 seconds |
| Started | Oct 09 06:47:13 AM UTC 24 |
| Finished | Oct 09 06:47:29 AM UTC 24 |
| Peak memory | 210836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3818762915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.adc_ctrl_stress_all_with_rand_reset.3818762915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.266758844 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 287700168 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 06:48:12 AM UTC 24 |
| Finished | Oct 09 06:48:16 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266758844 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.266758844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.2559618915 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 328417201951 ps |
| CPU time | 179.72 seconds |
| Started | Oct 09 06:47:50 AM UTC 24 |
| Finished | Oct 09 06:50:53 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559618915 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.2559618915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.3037009646 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 576483405129 ps |
| CPU time | 781.38 seconds |
| Started | Oct 09 06:47:54 AM UTC 24 |
| Finished | Oct 09 07:01:03 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037009646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3037009646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3148368206 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 164968597349 ps |
| CPU time | 123.97 seconds |
| Started | Oct 09 06:47:38 AM UTC 24 |
| Finished | Oct 09 06:49:44 AM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148368206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3148368206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.274585393 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 501489668907 ps |
| CPU time | 297.21 seconds |
| Started | Oct 09 06:47:30 AM UTC 24 |
| Finished | Oct 09 06:52:31 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274585393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.274585393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.392231280 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 159005154229 ps |
| CPU time | 325.51 seconds |
| Started | Oct 09 06:47:31 AM UTC 24 |
| Finished | Oct 09 06:53:01 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392231280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.392231280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.996913230 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 337937154287 ps |
| CPU time | 953.46 seconds |
| Started | Oct 09 06:47:47 AM UTC 24 |
| Finished | Oct 09 07:03:50 AM UTC 24 |
| Peak memory | 213300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996913230 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.996913230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4040669210 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 593595367556 ps |
| CPU time | 89.64 seconds |
| Started | Oct 09 06:47:50 AM UTC 24 |
| Finished | Oct 09 06:49:22 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040669210 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.4040669210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3763912297 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 105840157822 ps |
| CPU time | 525.72 seconds |
| Started | Oct 09 06:48:03 AM UTC 24 |
| Finished | Oct 09 06:56:55 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763912297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3763912297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.999276309 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 33781744384 ps |
| CPU time | 36.19 seconds |
| Started | Oct 09 06:47:58 AM UTC 24 |
| Finished | Oct 09 06:48:36 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999276309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.999276309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.3796799349 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3927764510 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 06:47:57 AM UTC 24 |
| Finished | Oct 09 06:48:02 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796799349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3796799349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.1305670432 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5815142460 ps |
| CPU time | 6.74 seconds |
| Started | Oct 09 06:47:29 AM UTC 24 |
| Finished | Oct 09 06:47:37 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305670432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1305670432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3775963456 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 35811752016 ps |
| CPU time | 76.89 seconds |
| Started | Oct 09 06:48:10 AM UTC 24 |
| Finished | Oct 09 06:49:29 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775963456 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3775963456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3750163675 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 165141220337 ps |
| CPU time | 58.25 seconds |
| Started | Oct 09 06:48:09 AM UTC 24 |
| Finished | Oct 09 06:49:09 AM UTC 24 |
| Peak memory | 221456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3750163675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.adc_ctrl_stress_all_with_rand_reset.3750163675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2360374279 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 462523151 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 06:49:30 AM UTC 24 |
| Finished | Oct 09 06:49:33 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360374279 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2360374279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.415204895 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 156170124330 ps |
| CPU time | 207.75 seconds |
| Started | Oct 09 06:49:06 AM UTC 24 |
| Finished | Oct 09 06:52:36 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415204895 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.415204895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.1338538300 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 328041013742 ps |
| CPU time | 223.93 seconds |
| Started | Oct 09 06:49:10 AM UTC 24 |
| Finished | Oct 09 06:52:57 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338538300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1338538300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.1984346631 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 161580829021 ps |
| CPU time | 495.58 seconds |
| Started | Oct 09 06:48:37 AM UTC 24 |
| Finished | Oct 09 06:56:58 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984346631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1984346631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3178255298 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 337112642809 ps |
| CPU time | 340.92 seconds |
| Started | Oct 09 06:48:41 AM UTC 24 |
| Finished | Oct 09 06:54:26 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178255298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.3178255298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2830092045 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 498521069032 ps |
| CPU time | 323.38 seconds |
| Started | Oct 09 06:48:18 AM UTC 24 |
| Finished | Oct 09 06:53:46 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830092045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2830092045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.228330122 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 501918240503 ps |
| CPU time | 1316.44 seconds |
| Started | Oct 09 06:48:26 AM UTC 24 |
| Finished | Oct 09 07:10:35 AM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228330122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.228330122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.1149352317 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 583940989897 ps |
| CPU time | 1517.85 seconds |
| Started | Oct 09 06:48:53 AM UTC 24 |
| Finished | Oct 09 07:14:27 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149352317 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.1149352317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3393661132 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 603061025161 ps |
| CPU time | 402.99 seconds |
| Started | Oct 09 06:48:53 AM UTC 24 |
| Finished | Oct 09 06:55:40 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393661132 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.3393661132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.2533404097 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 45330991436 ps |
| CPU time | 52.64 seconds |
| Started | Oct 09 06:49:22 AM UTC 24 |
| Finished | Oct 09 06:50:17 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533404097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2533404097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.2572261453 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3023482025 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 06:49:16 AM UTC 24 |
| Finished | Oct 09 06:49:21 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572261453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2572261453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.328305491 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 6031474120 ps |
| CPU time | 7.45 seconds |
| Started | Oct 09 06:48:16 AM UTC 24 |
| Finished | Oct 09 06:48:25 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328305491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.328305491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2414904520 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 291316274863 ps |
| CPU time | 847.83 seconds |
| Started | Oct 09 06:49:29 AM UTC 24 |
| Finished | Oct 09 07:03:46 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414904520 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.2414904520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1912135285 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 15710935698 ps |
| CPU time | 25.11 seconds |
| Started | Oct 09 06:49:22 AM UTC 24 |
| Finished | Oct 09 06:49:49 AM UTC 24 |
| Peak memory | 221316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1912135285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.adc_ctrl_stress_all_with_rand_reset.1912135285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3646989581 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 469816145 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 06:50:34 AM UTC 24 |
| Finished | Oct 09 06:50:38 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646989581 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3646989581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.1576415255 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 181731053909 ps |
| CPU time | 432.19 seconds |
| Started | Oct 09 06:49:50 AM UTC 24 |
| Finished | Oct 09 06:57:07 AM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576415255 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.1576415255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.2524820275 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 367088656738 ps |
| CPU time | 1045.7 seconds |
| Started | Oct 09 06:50:16 AM UTC 24 |
| Finished | Oct 09 07:07:53 AM UTC 24 |
| Peak memory | 213308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524820275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2524820275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.1521291417 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 161279040733 ps |
| CPU time | 214.9 seconds |
| Started | Oct 09 06:49:43 AM UTC 24 |
| Finished | Oct 09 06:53:21 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521291417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1521291417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2304442479 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 505986912863 ps |
| CPU time | 658.26 seconds |
| Started | Oct 09 06:49:45 AM UTC 24 |
| Finished | Oct 09 07:00:50 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304442479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.2304442479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.4273649091 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 162919086869 ps |
| CPU time | 36.94 seconds |
| Started | Oct 09 06:49:41 AM UTC 24 |
| Finished | Oct 09 06:50:19 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273649091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4273649091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.956041122 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 329898531427 ps |
| CPU time | 917.42 seconds |
| Started | Oct 09 06:49:41 AM UTC 24 |
| Finished | Oct 09 07:05:08 AM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956041122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.956041122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3950191906 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 392133634519 ps |
| CPU time | 385.2 seconds |
| Started | Oct 09 06:49:50 AM UTC 24 |
| Finished | Oct 09 06:56:20 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950191906 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.3950191906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.203021608 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 111818345851 ps |
| CPU time | 625.77 seconds |
| Started | Oct 09 06:50:32 AM UTC 24 |
| Finished | Oct 09 07:01:05 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203021608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.203021608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.394172915 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 41289263555 ps |
| CPU time | 10.36 seconds |
| Started | Oct 09 06:50:20 AM UTC 24 |
| Finished | Oct 09 06:50:32 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394172915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.394172915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.972232751 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2782841287 ps |
| CPU time | 12.69 seconds |
| Started | Oct 09 06:50:17 AM UTC 24 |
| Finished | Oct 09 06:50:31 AM UTC 24 |
| Peak memory | 210412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972232751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.972232751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.3131554012 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5889948022 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 06:49:35 AM UTC 24 |
| Finished | Oct 09 06:49:40 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131554012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3131554012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.2946348921 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 336206142245 ps |
| CPU time | 45.76 seconds |
| Started | Oct 09 06:50:33 AM UTC 24 |
| Finished | Oct 09 06:51:20 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946348921 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.2946348921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1570302337 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1413434810 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 06:50:33 AM UTC 24 |
| Finished | Oct 09 06:50:36 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1570302337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.adc_ctrl_stress_all_with_rand_reset.1570302337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.3469229790 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 316447613 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 06:52:03 AM UTC 24 |
| Finished | Oct 09 06:52:05 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469229790 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3469229790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.1367302690 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 330255191591 ps |
| CPU time | 123.3 seconds |
| Started | Oct 09 06:51:15 AM UTC 24 |
| Finished | Oct 09 06:53:21 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367302690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1367302690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.3986070411 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 162443060184 ps |
| CPU time | 287.38 seconds |
| Started | Oct 09 06:50:46 AM UTC 24 |
| Finished | Oct 09 06:55:37 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986070411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3986070411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4086726838 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 165491309005 ps |
| CPU time | 160.7 seconds |
| Started | Oct 09 06:50:53 AM UTC 24 |
| Finished | Oct 09 06:53:36 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086726838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.4086726838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.844265155 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 321119145900 ps |
| CPU time | 319.5 seconds |
| Started | Oct 09 06:50:39 AM UTC 24 |
| Finished | Oct 09 06:56:03 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844265155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.844265155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1194294135 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 328875949601 ps |
| CPU time | 893.09 seconds |
| Started | Oct 09 06:50:41 AM UTC 24 |
| Finished | Oct 09 07:05:43 AM UTC 24 |
| Peak memory | 213284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194294135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.1194294135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.664505924 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 466872225314 ps |
| CPU time | 736.6 seconds |
| Started | Oct 09 06:50:59 AM UTC 24 |
| Finished | Oct 09 07:03:24 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664505924 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.664505924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3589201379 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 201387777378 ps |
| CPU time | 711.8 seconds |
| Started | Oct 09 06:51:00 AM UTC 24 |
| Finished | Oct 09 07:03:00 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589201379 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.3589201379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.1956157237 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 105015105522 ps |
| CPU time | 558 seconds |
| Started | Oct 09 06:51:31 AM UTC 24 |
| Finished | Oct 09 07:00:55 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956157237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1956157237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.1299559978 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 35978408922 ps |
| CPU time | 33.54 seconds |
| Started | Oct 09 06:51:28 AM UTC 24 |
| Finished | Oct 09 06:52:03 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299559978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1299559978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.3214883975 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3562892751 ps |
| CPU time | 8.01 seconds |
| Started | Oct 09 06:51:21 AM UTC 24 |
| Finished | Oct 09 06:51:30 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214883975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3214883975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.1165547008 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 6188297691 ps |
| CPU time | 7.85 seconds |
| Started | Oct 09 06:50:37 AM UTC 24 |
| Finished | Oct 09 06:50:46 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165547008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1165547008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.1201369101 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 336929381382 ps |
| CPU time | 661.86 seconds |
| Started | Oct 09 06:52:03 AM UTC 24 |
| Finished | Oct 09 07:03:11 AM UTC 24 |
| Peak memory | 221328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201369101 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.1201369101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4216051867 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 50404153878 ps |
| CPU time | 34.05 seconds |
| Started | Oct 09 06:51:56 AM UTC 24 |
| Finished | Oct 09 06:52:31 AM UTC 24 |
| Peak memory | 221404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4216051867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.adc_ctrl_stress_all_with_rand_reset.4216051867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.3364435023 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 437788653 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 06:53:29 AM UTC 24 |
| Finished | Oct 09 06:53:32 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364435023 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3364435023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.829034071 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 163900011084 ps |
| CPU time | 342.03 seconds |
| Started | Oct 09 06:52:38 AM UTC 24 |
| Finished | Oct 09 06:58:24 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829034071 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.829034071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3881960884 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 376762760477 ps |
| CPU time | 1044.3 seconds |
| Started | Oct 09 06:52:58 AM UTC 24 |
| Finished | Oct 09 07:10:33 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881960884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3881960884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.3518675307 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 318483910268 ps |
| CPU time | 408.14 seconds |
| Started | Oct 09 06:52:11 AM UTC 24 |
| Finished | Oct 09 06:59:04 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518675307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3518675307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1378961299 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 161740935650 ps |
| CPU time | 374.51 seconds |
| Started | Oct 09 06:52:11 AM UTC 24 |
| Finished | Oct 09 06:58:30 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378961299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.1378961299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.4169826059 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 320678576267 ps |
| CPU time | 820.15 seconds |
| Started | Oct 09 06:52:06 AM UTC 24 |
| Finished | Oct 09 07:05:55 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169826059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4169826059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.3271467615 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 484044769583 ps |
| CPU time | 1434.88 seconds |
| Started | Oct 09 06:52:08 AM UTC 24 |
| Finished | Oct 09 07:16:18 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271467615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.3271467615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.1632674620 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 529584150782 ps |
| CPU time | 387.61 seconds |
| Started | Oct 09 06:52:33 AM UTC 24 |
| Finished | Oct 09 06:59:05 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632674620 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.1632674620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.13379072 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 592121688132 ps |
| CPU time | 314.22 seconds |
| Started | Oct 09 06:52:33 AM UTC 24 |
| Finished | Oct 09 06:57:51 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13379072 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.13379072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3197598016 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 120080048393 ps |
| CPU time | 437.13 seconds |
| Started | Oct 09 06:53:22 AM UTC 24 |
| Finished | Oct 09 07:00:44 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197598016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3197598016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.1491465089 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 41786480479 ps |
| CPU time | 155.64 seconds |
| Started | Oct 09 06:53:21 AM UTC 24 |
| Finished | Oct 09 06:55:59 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491465089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1491465089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.2156279207 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 4398716993 ps |
| CPU time | 18.89 seconds |
| Started | Oct 09 06:53:02 AM UTC 24 |
| Finished | Oct 09 06:53:22 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156279207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2156279207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1697589225 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 6020432727 ps |
| CPU time | 4.55 seconds |
| Started | Oct 09 06:52:05 AM UTC 24 |
| Finished | Oct 09 06:52:11 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697589225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1697589225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.606364499 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 32557136492 ps |
| CPU time | 39.51 seconds |
| Started | Oct 09 06:53:23 AM UTC 24 |
| Finished | Oct 09 06:54:04 AM UTC 24 |
| Peak memory | 221412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=606364499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.606364499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.4028691906 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 451888224 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 06:55:03 AM UTC 24 |
| Finished | Oct 09 06:55:05 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028691906 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4028691906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.1246323061 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 495604921300 ps |
| CPU time | 976.03 seconds |
| Started | Oct 09 06:54:05 AM UTC 24 |
| Finished | Oct 09 07:10:31 AM UTC 24 |
| Peak memory | 213332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246323061 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.1246323061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.1252592003 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 166075503608 ps |
| CPU time | 128.25 seconds |
| Started | Oct 09 06:54:27 AM UTC 24 |
| Finished | Oct 09 06:56:38 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252592003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1252592003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.1193108122 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 324789794219 ps |
| CPU time | 988.3 seconds |
| Started | Oct 09 06:53:38 AM UTC 24 |
| Finished | Oct 09 07:10:16 AM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193108122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1193108122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3094561135 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 165120043510 ps |
| CPU time | 568.28 seconds |
| Started | Oct 09 06:53:39 AM UTC 24 |
| Finished | Oct 09 07:03:13 AM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094561135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.3094561135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.1532633833 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 331073201803 ps |
| CPU time | 65.99 seconds |
| Started | Oct 09 06:53:34 AM UTC 24 |
| Finished | Oct 09 06:54:42 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532633833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1532633833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.3560868206 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 334309319601 ps |
| CPU time | 479.44 seconds |
| Started | Oct 09 06:53:36 AM UTC 24 |
| Finished | Oct 09 07:01:41 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560868206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.3560868206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.3854138086 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 188631210753 ps |
| CPU time | 377.6 seconds |
| Started | Oct 09 06:53:40 AM UTC 24 |
| Finished | Oct 09 07:00:02 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854138086 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.3854138086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1806502585 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 393891152840 ps |
| CPU time | 125.57 seconds |
| Started | Oct 09 06:53:47 AM UTC 24 |
| Finished | Oct 09 06:55:55 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806502585 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.1806502585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.3274377144 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 82137452216 ps |
| CPU time | 349.44 seconds |
| Started | Oct 09 06:54:43 AM UTC 24 |
| Finished | Oct 09 07:00:37 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274377144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3274377144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3755846530 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 32228353372 ps |
| CPU time | 70.87 seconds |
| Started | Oct 09 06:54:43 AM UTC 24 |
| Finished | Oct 09 06:55:56 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755846530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3755846530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.1412376482 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3802479933 ps |
| CPU time | 9.83 seconds |
| Started | Oct 09 06:54:37 AM UTC 24 |
| Finished | Oct 09 06:54:48 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412376482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1412376482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.293238220 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5795997403 ps |
| CPU time | 4.65 seconds |
| Started | Oct 09 06:53:32 AM UTC 24 |
| Finished | Oct 09 06:53:38 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293238220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.293238220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.3000651359 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 296463172669 ps |
| CPU time | 500.74 seconds |
| Started | Oct 09 06:54:54 AM UTC 24 |
| Finished | Oct 09 07:03:19 AM UTC 24 |
| Peak memory | 221204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000651359 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.3000651359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1392788335 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 11020922116 ps |
| CPU time | 10.94 seconds |
| Started | Oct 09 06:54:49 AM UTC 24 |
| Finished | Oct 09 06:55:02 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1392788335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.adc_ctrl_stress_all_with_rand_reset.1392788335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1258735090 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 457992731 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 06:07:44 AM UTC 24 |
| Finished | Oct 09 06:07:46 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258735090 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1258735090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.337449792 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 186397134616 ps |
| CPU time | 299.17 seconds |
| Started | Oct 09 06:07:37 AM UTC 24 |
| Finished | Oct 09 06:12:43 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337449792 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.337449792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.3522250982 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 160430143225 ps |
| CPU time | 377.84 seconds |
| Started | Oct 09 06:07:36 AM UTC 24 |
| Finished | Oct 09 06:14:01 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522250982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3522250982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.447692584 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 163510178578 ps |
| CPU time | 283.75 seconds |
| Started | Oct 09 06:07:36 AM UTC 24 |
| Finished | Oct 09 06:12:26 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447692584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.447692584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3243447619 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 332265293959 ps |
| CPU time | 192.38 seconds |
| Started | Oct 09 06:07:36 AM UTC 24 |
| Finished | Oct 09 06:10:54 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243447619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3243447619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3313290580 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 615887932287 ps |
| CPU time | 1770.99 seconds |
| Started | Oct 09 06:07:37 AM UTC 24 |
| Finished | Oct 09 06:37:28 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313290580 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.3313290580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3806218254 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 94691217626 ps |
| CPU time | 611.97 seconds |
| Started | Oct 09 06:07:43 AM UTC 24 |
| Finished | Oct 09 06:18:02 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806218254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3806218254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.3374718778 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 34532300991 ps |
| CPU time | 45.14 seconds |
| Started | Oct 09 06:07:41 AM UTC 24 |
| Finished | Oct 09 06:08:35 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374718778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3374718778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2879004327 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4822651983 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 06:07:39 AM UTC 24 |
| Finished | Oct 09 06:07:44 AM UTC 24 |
| Peak memory | 210520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879004327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2879004327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.2960901222 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7908524021 ps |
| CPU time | 9.09 seconds |
| Started | Oct 09 06:07:43 AM UTC 24 |
| Finished | Oct 09 06:07:54 AM UTC 24 |
| Peak memory | 242776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960901222 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2960901222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2679766749 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5808467679 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 06:07:35 AM UTC 24 |
| Finished | Oct 09 06:07:56 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679766749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2679766749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.1545274558 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 372221557 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 06:56:37 AM UTC 24 |
| Finished | Oct 09 06:56:40 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545274558 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1545274558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.3397294733 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 528354289937 ps |
| CPU time | 475.92 seconds |
| Started | Oct 09 06:55:59 AM UTC 24 |
| Finished | Oct 09 07:04:01 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397294733 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.3397294733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.3101220622 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 176333889667 ps |
| CPU time | 615.51 seconds |
| Started | Oct 09 06:56:00 AM UTC 24 |
| Finished | Oct 09 07:06:23 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101220622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3101220622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.1253895014 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 164567441906 ps |
| CPU time | 400.68 seconds |
| Started | Oct 09 06:55:38 AM UTC 24 |
| Finished | Oct 09 07:02:23 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253895014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1253895014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2328394936 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 323846315027 ps |
| CPU time | 266.03 seconds |
| Started | Oct 09 06:55:41 AM UTC 24 |
| Finished | Oct 09 07:00:11 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328394936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.2328394936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3717487330 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 159410042976 ps |
| CPU time | 115.46 seconds |
| Started | Oct 09 06:55:10 AM UTC 24 |
| Finished | Oct 09 06:57:08 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717487330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3717487330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2348765523 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 165269387760 ps |
| CPU time | 39.3 seconds |
| Started | Oct 09 06:55:37 AM UTC 24 |
| Finished | Oct 09 06:56:18 AM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348765523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.2348765523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1992760471 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 236272247690 ps |
| CPU time | 405.3 seconds |
| Started | Oct 09 06:55:55 AM UTC 24 |
| Finished | Oct 09 07:02:45 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992760471 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.1992760471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3365913307 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 209997128192 ps |
| CPU time | 611.65 seconds |
| Started | Oct 09 06:55:57 AM UTC 24 |
| Finished | Oct 09 07:06:16 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365913307 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.3365913307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.1788374745 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 92982315330 ps |
| CPU time | 632.03 seconds |
| Started | Oct 09 06:56:17 AM UTC 24 |
| Finished | Oct 09 07:06:56 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788374745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1788374745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.3639971760 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 32451789365 ps |
| CPU time | 23.7 seconds |
| Started | Oct 09 06:56:12 AM UTC 24 |
| Finished | Oct 09 06:56:37 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639971760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3639971760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.400698056 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4758799922 ps |
| CPU time | 6.23 seconds |
| Started | Oct 09 06:56:04 AM UTC 24 |
| Finished | Oct 09 06:56:11 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400698056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.400698056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.612961968 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5830567174 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 06:55:06 AM UTC 24 |
| Finished | Oct 09 06:55:09 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612961968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.612961968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3699392535 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 317253408894 ps |
| CPU time | 691.13 seconds |
| Started | Oct 09 06:56:21 AM UTC 24 |
| Finished | Oct 09 07:08:00 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699392535 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.3699392535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.922079069 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 67469206089 ps |
| CPU time | 31.4 seconds |
| Started | Oct 09 06:56:19 AM UTC 24 |
| Finished | Oct 09 06:56:52 AM UTC 24 |
| Peak memory | 223068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=922079069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.922079069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.3893907253 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 473804530 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 06:57:51 AM UTC 24 |
| Finished | Oct 09 06:57:54 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893907253 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3893907253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.2896429040 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 162395811728 ps |
| CPU time | 45.57 seconds |
| Started | Oct 09 06:57:09 AM UTC 24 |
| Finished | Oct 09 06:57:56 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896429040 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.2896429040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.2844650269 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 170784629399 ps |
| CPU time | 451.18 seconds |
| Started | Oct 09 06:57:11 AM UTC 24 |
| Finished | Oct 09 07:04:47 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844650269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2844650269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.1048292602 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 165418939563 ps |
| CPU time | 636.19 seconds |
| Started | Oct 09 06:56:52 AM UTC 24 |
| Finished | Oct 09 07:07:37 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048292602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1048292602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2618848645 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 494771498540 ps |
| CPU time | 668.54 seconds |
| Started | Oct 09 06:56:55 AM UTC 24 |
| Finished | Oct 09 07:08:11 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618848645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.2618848645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.1724096471 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 162324147218 ps |
| CPU time | 407.4 seconds |
| Started | Oct 09 06:56:41 AM UTC 24 |
| Finished | Oct 09 07:03:33 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724096471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1724096471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.2244548259 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 481801087964 ps |
| CPU time | 1274.37 seconds |
| Started | Oct 09 06:56:48 AM UTC 24 |
| Finished | Oct 09 07:18:16 AM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244548259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.2244548259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.651384539 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 169774534112 ps |
| CPU time | 506.21 seconds |
| Started | Oct 09 06:56:59 AM UTC 24 |
| Finished | Oct 09 07:05:31 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651384539 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.651384539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1708260534 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 404657901233 ps |
| CPU time | 1124.6 seconds |
| Started | Oct 09 06:57:08 AM UTC 24 |
| Finished | Oct 09 07:16:04 AM UTC 24 |
| Peak memory | 213552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708260534 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1708260534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.3758009135 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 137681778299 ps |
| CPU time | 696.32 seconds |
| Started | Oct 09 06:57:25 AM UTC 24 |
| Finished | Oct 09 07:09:09 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758009135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3758009135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.926811305 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 38947069086 ps |
| CPU time | 23.53 seconds |
| Started | Oct 09 06:57:23 AM UTC 24 |
| Finished | Oct 09 06:57:48 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926811305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.926811305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.292476038 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4810750401 ps |
| CPU time | 11.11 seconds |
| Started | Oct 09 06:57:12 AM UTC 24 |
| Finished | Oct 09 06:57:24 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292476038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.292476038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.4211880500 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 5755296505 ps |
| CPU time | 8.26 seconds |
| Started | Oct 09 06:56:38 AM UTC 24 |
| Finished | Oct 09 06:56:48 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211880500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4211880500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.952547443 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 198662080403 ps |
| CPU time | 640.89 seconds |
| Started | Oct 09 06:57:48 AM UTC 24 |
| Finished | Oct 09 07:08:36 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952547443 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.952547443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3587953453 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 440683352372 ps |
| CPU time | 171.7 seconds |
| Started | Oct 09 06:57:36 AM UTC 24 |
| Finished | Oct 09 07:00:31 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3587953453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.adc_ctrl_stress_all_with_rand_reset.3587953453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.2192303665 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 403325425 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:00:31 AM UTC 24 |
| Finished | Oct 09 07:00:33 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192303665 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2192303665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.3595700735 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 368899338510 ps |
| CPU time | 203.58 seconds |
| Started | Oct 09 06:59:05 AM UTC 24 |
| Finished | Oct 09 07:02:32 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595700735 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.3595700735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2888292278 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 499578382450 ps |
| CPU time | 341.77 seconds |
| Started | Oct 09 06:58:05 AM UTC 24 |
| Finished | Oct 09 07:03:51 AM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888292278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2888292278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3713125793 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 339055482207 ps |
| CPU time | 919.17 seconds |
| Started | Oct 09 06:58:26 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 213272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713125793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3713125793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.3846222186 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 503102072195 ps |
| CPU time | 802.44 seconds |
| Started | Oct 09 06:57:55 AM UTC 24 |
| Finished | Oct 09 07:11:26 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846222186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3846222186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.3375472015 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 497861713585 ps |
| CPU time | 329.13 seconds |
| Started | Oct 09 06:57:57 AM UTC 24 |
| Finished | Oct 09 07:03:30 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375472015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.3375472015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3657100781 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 575100600987 ps |
| CPU time | 1589.77 seconds |
| Started | Oct 09 06:58:31 AM UTC 24 |
| Finished | Oct 09 07:25:17 AM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657100781 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3657100781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1248766571 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 393354258870 ps |
| CPU time | 620.73 seconds |
| Started | Oct 09 06:59:05 AM UTC 24 |
| Finished | Oct 09 07:09:33 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248766571 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.1248766571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.2004569006 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 73485424235 ps |
| CPU time | 344.39 seconds |
| Started | Oct 09 07:00:09 AM UTC 24 |
| Finished | Oct 09 07:05:57 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004569006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2004569006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.2286941736 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 43175869405 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 07:00:09 AM UTC 24 |
| Finished | Oct 09 07:00:21 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286941736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2286941736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.4004385061 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4147999143 ps |
| CPU time | 20 seconds |
| Started | Oct 09 06:59:46 AM UTC 24 |
| Finished | Oct 09 07:00:08 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004385061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4004385061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.861622471 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5754957453 ps |
| CPU time | 10.71 seconds |
| Started | Oct 09 06:57:52 AM UTC 24 |
| Finished | Oct 09 06:58:04 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861622471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.861622471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.1628509538 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3096357893925 ps |
| CPU time | 4946.5 seconds |
| Started | Oct 09 07:00:22 AM UTC 24 |
| Finished | Oct 09 08:23:41 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628509538 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.1628509538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1639448010 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 39840041783 ps |
| CPU time | 19.41 seconds |
| Started | Oct 09 07:00:12 AM UTC 24 |
| Finished | Oct 09 07:00:32 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1639448010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.adc_ctrl_stress_all_with_rand_reset.1639448010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.1510758512 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 496050562 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 07:02:32 AM UTC 24 |
| Finished | Oct 09 07:02:37 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510758512 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1510758512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.399040652 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 490668280177 ps |
| CPU time | 389.82 seconds |
| Started | Oct 09 07:01:04 AM UTC 24 |
| Finished | Oct 09 07:07:38 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399040652 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.399040652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1930205779 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 366958420582 ps |
| CPU time | 596.38 seconds |
| Started | Oct 09 07:01:06 AM UTC 24 |
| Finished | Oct 09 07:11:09 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930205779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1930205779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.4262639166 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 328607158407 ps |
| CPU time | 144.89 seconds |
| Started | Oct 09 07:00:44 AM UTC 24 |
| Finished | Oct 09 07:03:12 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262639166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4262639166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1501842078 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 160406822250 ps |
| CPU time | 141.17 seconds |
| Started | Oct 09 07:00:51 AM UTC 24 |
| Finished | Oct 09 07:03:15 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501842078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.1501842078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.4138326383 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 324019156749 ps |
| CPU time | 237.07 seconds |
| Started | Oct 09 07:00:34 AM UTC 24 |
| Finished | Oct 09 07:04:34 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138326383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4138326383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.220388479 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 169515429116 ps |
| CPU time | 418.17 seconds |
| Started | Oct 09 07:00:38 AM UTC 24 |
| Finished | Oct 09 07:07:41 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220388479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.220388479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.3194870952 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 175603726661 ps |
| CPU time | 591.02 seconds |
| Started | Oct 09 07:00:56 AM UTC 24 |
| Finished | Oct 09 07:10:54 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194870952 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.3194870952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1871183528 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 210928620939 ps |
| CPU time | 334.52 seconds |
| Started | Oct 09 07:01:03 AM UTC 24 |
| Finished | Oct 09 07:06:41 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871183528 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.1871183528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.3126415923 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 112895376372 ps |
| CPU time | 502.51 seconds |
| Started | Oct 09 07:02:09 AM UTC 24 |
| Finished | Oct 09 07:10:36 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126415923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3126415923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.1068146876 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 33089538155 ps |
| CPU time | 69.12 seconds |
| Started | Oct 09 07:01:48 AM UTC 24 |
| Finished | Oct 09 07:02:59 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068146876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1068146876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.3281202017 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4837903989 ps |
| CPU time | 3.88 seconds |
| Started | Oct 09 07:01:42 AM UTC 24 |
| Finished | Oct 09 07:01:47 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281202017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3281202017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.4193740708 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5930283588 ps |
| CPU time | 27.02 seconds |
| Started | Oct 09 07:00:33 AM UTC 24 |
| Finished | Oct 09 07:01:01 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193740708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4193740708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.2115748791 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 245009715446 ps |
| CPU time | 723.13 seconds |
| Started | Oct 09 07:02:24 AM UTC 24 |
| Finished | Oct 09 07:14:35 AM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115748791 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.2115748791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.450948169 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 20117137787 ps |
| CPU time | 13.51 seconds |
| Started | Oct 09 07:02:18 AM UTC 24 |
| Finished | Oct 09 07:02:33 AM UTC 24 |
| Peak memory | 221056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=450948169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.450948169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.2208567782 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 391857903 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 07:03:31 AM UTC 24 |
| Finished | Oct 09 07:03:33 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208567782 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2208567782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.1394595919 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 504959207632 ps |
| CPU time | 1229.12 seconds |
| Started | Oct 09 07:03:13 AM UTC 24 |
| Finished | Oct 09 07:23:55 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394595919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1394595919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.1248779877 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 491926994714 ps |
| CPU time | 1302.78 seconds |
| Started | Oct 09 07:02:47 AM UTC 24 |
| Finished | Oct 09 07:24:43 AM UTC 24 |
| Peak memory | 213332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248779877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1248779877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2743378581 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 160977816278 ps |
| CPU time | 569.56 seconds |
| Started | Oct 09 07:02:54 AM UTC 24 |
| Finished | Oct 09 07:12:30 AM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743378581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.2743378581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.3237129451 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 328592108357 ps |
| CPU time | 182.74 seconds |
| Started | Oct 09 07:02:43 AM UTC 24 |
| Finished | Oct 09 07:05:48 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237129451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.3237129451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.567034505 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 165072893531 ps |
| CPU time | 416.3 seconds |
| Started | Oct 09 07:03:00 AM UTC 24 |
| Finished | Oct 09 07:10:01 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567034505 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.567034505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.496851843 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 199382581125 ps |
| CPU time | 126 seconds |
| Started | Oct 09 07:03:01 AM UTC 24 |
| Finished | Oct 09 07:05:09 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496851843 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.496851843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.3137331933 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 100638855628 ps |
| CPU time | 646.74 seconds |
| Started | Oct 09 07:03:15 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137331933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3137331933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.878913592 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 37841596203 ps |
| CPU time | 100.76 seconds |
| Started | Oct 09 07:03:14 AM UTC 24 |
| Finished | Oct 09 07:04:57 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878913592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.878913592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1298708129 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4788274249 ps |
| CPU time | 22.78 seconds |
| Started | Oct 09 07:03:13 AM UTC 24 |
| Finished | Oct 09 07:03:37 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298708129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1298708129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.321248822 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5643950484 ps |
| CPU time | 7.57 seconds |
| Started | Oct 09 07:02:33 AM UTC 24 |
| Finished | Oct 09 07:02:42 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321248822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.321248822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3582717471 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 193712592515 ps |
| CPU time | 164.64 seconds |
| Started | Oct 09 07:03:26 AM UTC 24 |
| Finished | Oct 09 07:06:13 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582717471 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.3582717471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3573115736 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4308488713 ps |
| CPU time | 24.6 seconds |
| Started | Oct 09 07:03:20 AM UTC 24 |
| Finished | Oct 09 07:03:47 AM UTC 24 |
| Peak memory | 221720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3573115736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.adc_ctrl_stress_all_with_rand_reset.3573115736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.1622753605 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 317563815 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 07:04:58 AM UTC 24 |
| Finished | Oct 09 07:05:00 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622753605 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1622753605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.1805012627 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 510791826101 ps |
| CPU time | 1073.33 seconds |
| Started | Oct 09 07:04:02 AM UTC 24 |
| Finished | Oct 09 07:22:07 AM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805012627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1805012627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.318588639 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 325964705195 ps |
| CPU time | 158.1 seconds |
| Started | Oct 09 07:03:47 AM UTC 24 |
| Finished | Oct 09 07:06:28 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318588639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.318588639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.593015117 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 492111195805 ps |
| CPU time | 1398.38 seconds |
| Started | Oct 09 07:03:47 AM UTC 24 |
| Finished | Oct 09 07:27:20 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593015117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.593015117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.3644062101 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 478102561667 ps |
| CPU time | 1320.82 seconds |
| Started | Oct 09 07:03:34 AM UTC 24 |
| Finished | Oct 09 07:25:48 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644062101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3644062101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.734421951 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 322572129606 ps |
| CPU time | 417.81 seconds |
| Started | Oct 09 07:03:38 AM UTC 24 |
| Finished | Oct 09 07:10:41 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734421951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.734421951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.266848885 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 357648679236 ps |
| CPU time | 676 seconds |
| Started | Oct 09 07:03:51 AM UTC 24 |
| Finished | Oct 09 07:15:14 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266848885 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.266848885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2575050130 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 593043549173 ps |
| CPU time | 437.78 seconds |
| Started | Oct 09 07:03:52 AM UTC 24 |
| Finished | Oct 09 07:11:16 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575050130 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2575050130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1449643873 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 111012516856 ps |
| CPU time | 524.14 seconds |
| Started | Oct 09 07:04:48 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449643873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1449643873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.3545170733 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 43225602566 ps |
| CPU time | 11.51 seconds |
| Started | Oct 09 07:04:46 AM UTC 24 |
| Finished | Oct 09 07:04:59 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545170733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3545170733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.3227648186 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3729061148 ps |
| CPU time | 16.35 seconds |
| Started | Oct 09 07:04:35 AM UTC 24 |
| Finished | Oct 09 07:04:53 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227648186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3227648186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.3227686066 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5574060289 ps |
| CPU time | 24.98 seconds |
| Started | Oct 09 07:03:34 AM UTC 24 |
| Finished | Oct 09 07:04:00 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227686066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3227686066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.2471305167 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 548424613664 ps |
| CPU time | 286 seconds |
| Started | Oct 09 07:04:58 AM UTC 24 |
| Finished | Oct 09 07:09:48 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471305167 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.2471305167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.840891597 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 7812816093 ps |
| CPU time | 11.81 seconds |
| Started | Oct 09 07:04:54 AM UTC 24 |
| Finished | Oct 09 07:05:07 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=840891597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.840891597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.2216950934 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 390665592 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 07:06:14 AM UTC 24 |
| Finished | Oct 09 07:06:16 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216950934 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2216950934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.2820729418 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 334315845651 ps |
| CPU time | 835.67 seconds |
| Started | Oct 09 07:05:31 AM UTC 24 |
| Finished | Oct 09 07:19:37 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820729418 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.2820729418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.3675397128 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 162488197707 ps |
| CPU time | 108.07 seconds |
| Started | Oct 09 07:05:08 AM UTC 24 |
| Finished | Oct 09 07:06:58 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675397128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3675397128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1204293550 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 332349793567 ps |
| CPU time | 171.67 seconds |
| Started | Oct 09 07:05:10 AM UTC 24 |
| Finished | Oct 09 07:08:05 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204293550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.1204293550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.1182543481 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 329376998669 ps |
| CPU time | 419.62 seconds |
| Started | Oct 09 07:05:01 AM UTC 24 |
| Finished | Oct 09 07:12:05 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182543481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1182543481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3709935843 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 491774346878 ps |
| CPU time | 1295.63 seconds |
| Started | Oct 09 07:05:07 AM UTC 24 |
| Finished | Oct 09 07:26:56 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709935843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.3709935843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.27910463 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 357517038454 ps |
| CPU time | 103.49 seconds |
| Started | Oct 09 07:05:15 AM UTC 24 |
| Finished | Oct 09 07:07:01 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27910463 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.27910463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3026892374 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 403624017379 ps |
| CPU time | 580.6 seconds |
| Started | Oct 09 07:05:15 AM UTC 24 |
| Finished | Oct 09 07:15:02 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026892374 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.3026892374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.586749413 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 120060994735 ps |
| CPU time | 823.48 seconds |
| Started | Oct 09 07:05:57 AM UTC 24 |
| Finished | Oct 09 07:19:50 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586749413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.586749413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.16899096 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 40389880033 ps |
| CPU time | 40.68 seconds |
| Started | Oct 09 07:05:56 AM UTC 24 |
| Finished | Oct 09 07:06:38 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16899096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.16899096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.3298115189 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4816424134 ps |
| CPU time | 5.67 seconds |
| Started | Oct 09 07:05:49 AM UTC 24 |
| Finished | Oct 09 07:05:55 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298115189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3298115189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.4157061847 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5653066726 ps |
| CPU time | 13.52 seconds |
| Started | Oct 09 07:05:00 AM UTC 24 |
| Finished | Oct 09 07:05:15 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157061847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4157061847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.2114692205 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 86540023166 ps |
| CPU time | 420.47 seconds |
| Started | Oct 09 07:06:00 AM UTC 24 |
| Finished | Oct 09 07:13:05 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114692205 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.2114692205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3702293564 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 19661400933 ps |
| CPU time | 44.68 seconds |
| Started | Oct 09 07:05:58 AM UTC 24 |
| Finished | Oct 09 07:06:44 AM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3702293564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.adc_ctrl_stress_all_with_rand_reset.3702293564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.411725945 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 443264754 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 07:07:42 AM UTC 24 |
| Finished | Oct 09 07:07:44 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411725945 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.411725945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.795301951 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 174031747813 ps |
| CPU time | 261.85 seconds |
| Started | Oct 09 07:06:45 AM UTC 24 |
| Finished | Oct 09 07:11:10 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795301951 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.795301951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.3495314813 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 512734715645 ps |
| CPU time | 529.57 seconds |
| Started | Oct 09 07:06:57 AM UTC 24 |
| Finished | Oct 09 07:15:53 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495314813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3495314813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.3217307206 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 327689938200 ps |
| CPU time | 172.74 seconds |
| Started | Oct 09 07:06:28 AM UTC 24 |
| Finished | Oct 09 07:09:24 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217307206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3217307206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3287138439 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 161367948877 ps |
| CPU time | 300.58 seconds |
| Started | Oct 09 07:06:30 AM UTC 24 |
| Finished | Oct 09 07:11:35 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287138439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.3287138439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.2444882433 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 162310334537 ps |
| CPU time | 168.52 seconds |
| Started | Oct 09 07:06:17 AM UTC 24 |
| Finished | Oct 09 07:09:08 AM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444882433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2444882433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.362677291 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 162543090365 ps |
| CPU time | 356.56 seconds |
| Started | Oct 09 07:06:24 AM UTC 24 |
| Finished | Oct 09 07:12:25 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362677291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.362677291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.2566081369 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 403694993720 ps |
| CPU time | 573.94 seconds |
| Started | Oct 09 07:06:38 AM UTC 24 |
| Finished | Oct 09 07:16:19 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566081369 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.2566081369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1915875563 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 604300917049 ps |
| CPU time | 1701.94 seconds |
| Started | Oct 09 07:06:43 AM UTC 24 |
| Finished | Oct 09 07:35:23 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915875563 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.1915875563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.3241186921 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 102179628653 ps |
| CPU time | 579.25 seconds |
| Started | Oct 09 07:07:04 AM UTC 24 |
| Finished | Oct 09 07:16:50 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241186921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3241186921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.3920972783 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 42356008138 ps |
| CPU time | 40.85 seconds |
| Started | Oct 09 07:07:02 AM UTC 24 |
| Finished | Oct 09 07:07:45 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920972783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3920972783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.680710431 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2696675859 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 07:06:59 AM UTC 24 |
| Finished | Oct 09 07:07:04 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680710431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.680710431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.3103150153 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5777227966 ps |
| CPU time | 12.76 seconds |
| Started | Oct 09 07:06:16 AM UTC 24 |
| Finished | Oct 09 07:06:30 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103150153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3103150153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.230488967 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 333916463142 ps |
| CPU time | 316.66 seconds |
| Started | Oct 09 07:07:39 AM UTC 24 |
| Finished | Oct 09 07:13:00 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230488967 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.230488967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.890782968 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1835596931 ps |
| CPU time | 10.13 seconds |
| Started | Oct 09 07:07:37 AM UTC 24 |
| Finished | Oct 09 07:07:48 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=890782968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.890782968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.554109038 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 323863973 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 07:09:22 AM UTC 24 |
| Finished | Oct 09 07:09:24 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554109038 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.554109038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.3796887630 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 485634610801 ps |
| CPU time | 308.12 seconds |
| Started | Oct 09 07:08:09 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796887630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3796887630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.2886705726 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 496153036873 ps |
| CPU time | 1290.5 seconds |
| Started | Oct 09 07:07:53 AM UTC 24 |
| Finished | Oct 09 07:29:36 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886705726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2886705726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.82022756 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 166651141846 ps |
| CPU time | 215.7 seconds |
| Started | Oct 09 07:07:54 AM UTC 24 |
| Finished | Oct 09 07:11:33 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82022756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.82022756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.1471190640 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 325537238536 ps |
| CPU time | 204.27 seconds |
| Started | Oct 09 07:07:45 AM UTC 24 |
| Finished | Oct 09 07:11:13 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471190640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1471190640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.2654445645 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 495585736336 ps |
| CPU time | 529.81 seconds |
| Started | Oct 09 07:07:49 AM UTC 24 |
| Finished | Oct 09 07:16:45 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654445645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.2654445645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3958319093 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 613924353470 ps |
| CPU time | 1350.07 seconds |
| Started | Oct 09 07:08:01 AM UTC 24 |
| Finished | Oct 09 07:30:45 AM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958319093 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3958319093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.543290548 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 64904424489 ps |
| CPU time | 339.4 seconds |
| Started | Oct 09 07:08:37 AM UTC 24 |
| Finished | Oct 09 07:14:21 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543290548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.543290548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.2982108920 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 33440777803 ps |
| CPU time | 70.75 seconds |
| Started | Oct 09 07:08:27 AM UTC 24 |
| Finished | Oct 09 07:09:40 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982108920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2982108920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.929300225 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3322329047 ps |
| CPU time | 13.03 seconds |
| Started | Oct 09 07:08:12 AM UTC 24 |
| Finished | Oct 09 07:08:26 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929300225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.929300225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.4110324970 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5794814402 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 07:07:45 AM UTC 24 |
| Finished | Oct 09 07:07:52 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110324970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4110324970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.206634797 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 34788734202 ps |
| CPU time | 9.72 seconds |
| Started | Oct 09 07:09:09 AM UTC 24 |
| Finished | Oct 09 07:09:20 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206634797 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.206634797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1955105350 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5787844392 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 07:09:09 AM UTC 24 |
| Finished | Oct 09 07:09:23 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1955105350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.adc_ctrl_stress_all_with_rand_reset.1955105350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.14655789 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 452708975 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 07:10:46 AM UTC 24 |
| Finished | Oct 09 07:10:49 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14655789 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.14655789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.3278764929 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 356461511082 ps |
| CPU time | 299.86 seconds |
| Started | Oct 09 07:10:02 AM UTC 24 |
| Finished | Oct 09 07:15:06 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278764929 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.3278764929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.3060902832 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 371486629417 ps |
| CPU time | 777.75 seconds |
| Started | Oct 09 07:10:17 AM UTC 24 |
| Finished | Oct 09 07:23:23 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060902832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3060902832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.3625716849 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 479258820196 ps |
| CPU time | 1087.08 seconds |
| Started | Oct 09 07:09:34 AM UTC 24 |
| Finished | Oct 09 07:27:53 AM UTC 24 |
| Peak memory | 213376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625716849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3625716849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2175812562 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 332856052135 ps |
| CPU time | 233.8 seconds |
| Started | Oct 09 07:09:37 AM UTC 24 |
| Finished | Oct 09 07:13:34 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175812562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2175812562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.1181321228 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 163803268512 ps |
| CPU time | 105.77 seconds |
| Started | Oct 09 07:09:25 AM UTC 24 |
| Finished | Oct 09 07:11:12 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181321228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1181321228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.793976647 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 329766556362 ps |
| CPU time | 237.83 seconds |
| Started | Oct 09 07:09:25 AM UTC 24 |
| Finished | Oct 09 07:13:26 AM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793976647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.793976647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.801660604 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 178205040639 ps |
| CPU time | 262.07 seconds |
| Started | Oct 09 07:09:41 AM UTC 24 |
| Finished | Oct 09 07:14:07 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801660604 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.801660604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1785744963 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 204764073258 ps |
| CPU time | 552.32 seconds |
| Started | Oct 09 07:09:48 AM UTC 24 |
| Finished | Oct 09 07:19:07 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785744963 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.1785744963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.3394935769 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 77370332580 ps |
| CPU time | 413.18 seconds |
| Started | Oct 09 07:10:37 AM UTC 24 |
| Finished | Oct 09 07:17:34 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394935769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3394935769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.173247773 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 23459715064 ps |
| CPU time | 14.93 seconds |
| Started | Oct 09 07:10:33 AM UTC 24 |
| Finished | Oct 09 07:10:50 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173247773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.173247773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.618002511 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5099754506 ps |
| CPU time | 11.45 seconds |
| Started | Oct 09 07:10:32 AM UTC 24 |
| Finished | Oct 09 07:10:45 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618002511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.618002511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.1579216331 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 6092506078 ps |
| CPU time | 11.42 seconds |
| Started | Oct 09 07:09:24 AM UTC 24 |
| Finished | Oct 09 07:09:36 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579216331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1579216331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1413267893 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 381536938899 ps |
| CPU time | 240.98 seconds |
| Started | Oct 09 07:10:42 AM UTC 24 |
| Finished | Oct 09 07:14:46 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413267893 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1413267893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.355864576 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2518929703 ps |
| CPU time | 29.91 seconds |
| Started | Oct 09 07:10:37 AM UTC 24 |
| Finished | Oct 09 07:11:08 AM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=355864576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.355864576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.93986340 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 521992556 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 06:07:54 AM UTC 24 |
| Finished | Oct 09 06:07:57 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93986340 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.93986340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2765775828 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 164243318571 ps |
| CPU time | 59.91 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:08:58 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765775828 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.2765775828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.607379145 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 337133149597 ps |
| CPU time | 226.95 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:11:43 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607379145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.607379145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2276029456 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 168418145763 ps |
| CPU time | 508.05 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:16:23 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276029456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2276029456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3811831155 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 162905790906 ps |
| CPU time | 56.84 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:08:51 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811831155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.3811831155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.1166551416 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 161122973998 ps |
| CPU time | 116.46 seconds |
| Started | Oct 09 06:07:44 AM UTC 24 |
| Finished | Oct 09 06:09:52 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166551416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1166551416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.517700059 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 161847957619 ps |
| CPU time | 450.85 seconds |
| Started | Oct 09 06:07:44 AM UTC 24 |
| Finished | Oct 09 06:15:30 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517700059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.517700059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3318754348 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 196494132990 ps |
| CPU time | 150.1 seconds |
| Started | Oct 09 06:07:46 AM UTC 24 |
| Finished | Oct 09 06:10:25 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318754348 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.3318754348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.614795305 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 38129975435 ps |
| CPU time | 59.22 seconds |
| Started | Oct 09 06:07:48 AM UTC 24 |
| Finished | Oct 09 06:08:57 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614795305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.614795305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.1809276868 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4072183996 ps |
| CPU time | 5.56 seconds |
| Started | Oct 09 06:07:48 AM UTC 24 |
| Finished | Oct 09 06:07:55 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809276868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1809276868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.816825813 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5841738131 ps |
| CPU time | 12.96 seconds |
| Started | Oct 09 06:07:44 AM UTC 24 |
| Finished | Oct 09 06:07:58 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816825813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.816825813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.1069120932 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 131377495368 ps |
| CPU time | 790.8 seconds |
| Started | Oct 09 06:07:54 AM UTC 24 |
| Finished | Oct 09 06:21:14 AM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069120932 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.1069120932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3931632528 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 474602862 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 06:08:48 AM UTC 24 |
| Finished | Oct 09 06:08:50 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931632528 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3931632528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3156592298 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 338371428937 ps |
| CPU time | 1091.94 seconds |
| Started | Oct 09 06:07:59 AM UTC 24 |
| Finished | Oct 09 06:26:22 AM UTC 24 |
| Peak memory | 213304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156592298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3156592298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3334513252 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 163434295339 ps |
| CPU time | 140.04 seconds |
| Started | Oct 09 06:07:59 AM UTC 24 |
| Finished | Oct 09 06:10:21 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334513252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.3334513252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.163421716 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 160880753443 ps |
| CPU time | 136.9 seconds |
| Started | Oct 09 06:07:56 AM UTC 24 |
| Finished | Oct 09 06:10:16 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163421716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.163421716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1505236555 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 485706198025 ps |
| CPU time | 1377.68 seconds |
| Started | Oct 09 06:07:56 AM UTC 24 |
| Finished | Oct 09 06:31:08 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505236555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.1505236555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2658701026 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 527307611215 ps |
| CPU time | 166.31 seconds |
| Started | Oct 09 06:07:59 AM UTC 24 |
| Finished | Oct 09 06:10:48 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658701026 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2658701026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4245938229 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 624747322385 ps |
| CPU time | 240.09 seconds |
| Started | Oct 09 06:08:03 AM UTC 24 |
| Finished | Oct 09 06:12:06 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245938229 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.4245938229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2133187409 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 118551341199 ps |
| CPU time | 590.45 seconds |
| Started | Oct 09 06:08:31 AM UTC 24 |
| Finished | Oct 09 06:18:28 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133187409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2133187409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3016202628 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 25739515643 ps |
| CPU time | 96.97 seconds |
| Started | Oct 09 06:08:31 AM UTC 24 |
| Finished | Oct 09 06:10:10 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016202628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3016202628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3878090519 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3482620440 ps |
| CPU time | 5.49 seconds |
| Started | Oct 09 06:08:23 AM UTC 24 |
| Finished | Oct 09 06:08:30 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878090519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3878090519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2117645282 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5696797313 ps |
| CPU time | 23.28 seconds |
| Started | Oct 09 06:07:56 AM UTC 24 |
| Finished | Oct 09 06:08:21 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117645282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2117645282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3496449213 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 280248547606 ps |
| CPU time | 896.36 seconds |
| Started | Oct 09 06:08:48 AM UTC 24 |
| Finished | Oct 09 06:23:53 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496449213 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.3496449213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.285708294 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 16129514669 ps |
| CPU time | 19.84 seconds |
| Started | Oct 09 06:08:37 AM UTC 24 |
| Finished | Oct 09 06:08:59 AM UTC 24 |
| Peak memory | 221272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=285708294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.285708294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.427188498 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 406311764 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 06:10:11 AM UTC 24 |
| Finished | Oct 09 06:10:14 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427188498 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.427188498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1713467740 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 160350643606 ps |
| CPU time | 442.77 seconds |
| Started | Oct 09 06:09:01 AM UTC 24 |
| Finished | Oct 09 06:16:29 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713467740 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.1713467740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.30785426 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 330837619534 ps |
| CPU time | 581.19 seconds |
| Started | Oct 09 06:09:42 AM UTC 24 |
| Finished | Oct 09 06:19:31 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30785426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.30785426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1451768119 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 322997665698 ps |
| CPU time | 265.25 seconds |
| Started | Oct 09 06:08:53 AM UTC 24 |
| Finished | Oct 09 06:13:22 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451768119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1451768119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3299594198 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 332386041109 ps |
| CPU time | 1121.06 seconds |
| Started | Oct 09 06:08:58 AM UTC 24 |
| Finished | Oct 09 06:27:51 AM UTC 24 |
| Peak memory | 213348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299594198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.3299594198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.492595291 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 163006401058 ps |
| CPU time | 192.06 seconds |
| Started | Oct 09 06:08:52 AM UTC 24 |
| Finished | Oct 09 06:12:07 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492595291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.492595291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2358343363 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 327946409285 ps |
| CPU time | 668.17 seconds |
| Started | Oct 09 06:08:52 AM UTC 24 |
| Finished | Oct 09 06:20:07 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358343363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.2358343363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3988062229 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 186891926587 ps |
| CPU time | 81.83 seconds |
| Started | Oct 09 06:08:59 AM UTC 24 |
| Finished | Oct 09 06:10:23 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988062229 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.3988062229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.839767420 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 80956006946 ps |
| CPU time | 438.79 seconds |
| Started | Oct 09 06:09:53 AM UTC 24 |
| Finished | Oct 09 06:17:17 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839767420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.839767420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3475171363 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 26127462077 ps |
| CPU time | 30.31 seconds |
| Started | Oct 09 06:09:48 AM UTC 24 |
| Finished | Oct 09 06:10:19 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475171363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3475171363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.2645951349 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3084142032 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 06:09:47 AM UTC 24 |
| Finished | Oct 09 06:09:52 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645951349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2645951349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.1676349409 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5747038996 ps |
| CPU time | 8.5 seconds |
| Started | Oct 09 06:08:51 AM UTC 24 |
| Finished | Oct 09 06:09:00 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676349409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1676349409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.242789579 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 68645417710 ps |
| CPU time | 234.73 seconds |
| Started | Oct 09 06:09:55 AM UTC 24 |
| Finished | Oct 09 06:13:53 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242789579 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.242789579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1632652972 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2064332514 ps |
| CPU time | 20.55 seconds |
| Started | Oct 09 06:09:53 AM UTC 24 |
| Finished | Oct 09 06:10:15 AM UTC 24 |
| Peak memory | 220976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1632652972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.adc_ctrl_stress_all_with_rand_reset.1632652972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.3821450568 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 466465140 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 06:11:05 AM UTC 24 |
| Finished | Oct 09 06:11:08 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821450568 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3821450568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2280608891 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 169412557714 ps |
| CPU time | 526.82 seconds |
| Started | Oct 09 06:10:26 AM UTC 24 |
| Finished | Oct 09 06:19:19 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280608891 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.2280608891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2051134755 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 168560943496 ps |
| CPU time | 98.68 seconds |
| Started | Oct 09 06:10:16 AM UTC 24 |
| Finished | Oct 09 06:11:57 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051134755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2051134755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.355107774 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 332847768228 ps |
| CPU time | 297.49 seconds |
| Started | Oct 09 06:10:20 AM UTC 24 |
| Finished | Oct 09 06:15:22 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355107774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.355107774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.3790838079 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 493954753749 ps |
| CPU time | 317.53 seconds |
| Started | Oct 09 06:10:15 AM UTC 24 |
| Finished | Oct 09 06:15:37 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790838079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3790838079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3670700224 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 165181205438 ps |
| CPU time | 539.97 seconds |
| Started | Oct 09 06:10:16 AM UTC 24 |
| Finished | Oct 09 06:19:23 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670700224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.3670700224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3107316412 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 340849791522 ps |
| CPU time | 381.3 seconds |
| Started | Oct 09 06:10:21 AM UTC 24 |
| Finished | Oct 09 06:16:48 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107316412 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.3107316412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1883972090 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 396263492690 ps |
| CPU time | 371.03 seconds |
| Started | Oct 09 06:10:23 AM UTC 24 |
| Finished | Oct 09 06:16:39 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883972090 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1883972090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2010488435 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 118508782732 ps |
| CPU time | 567.14 seconds |
| Started | Oct 09 06:10:45 AM UTC 24 |
| Finished | Oct 09 06:20:18 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010488435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2010488435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.571978785 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 38134947732 ps |
| CPU time | 76.82 seconds |
| Started | Oct 09 06:10:43 AM UTC 24 |
| Finished | Oct 09 06:12:01 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571978785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.571978785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.120157174 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3379550079 ps |
| CPU time | 13.51 seconds |
| Started | Oct 09 06:10:29 AM UTC 24 |
| Finished | Oct 09 06:10:44 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120157174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.120157174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3440843601 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5948534443 ps |
| CPU time | 25.75 seconds |
| Started | Oct 09 06:10:15 AM UTC 24 |
| Finished | Oct 09 06:10:42 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440843601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3440843601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3404667669 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 254903752139 ps |
| CPU time | 712.2 seconds |
| Started | Oct 09 06:10:55 AM UTC 24 |
| Finished | Oct 09 06:22:55 AM UTC 24 |
| Peak memory | 221208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404667669 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.3404667669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.2169660024 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 298014781 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 06:12:49 AM UTC 24 |
| Finished | Oct 09 06:12:52 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169660024 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2169660024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.839711228 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 355662656725 ps |
| CPU time | 315.62 seconds |
| Started | Oct 09 06:12:06 AM UTC 24 |
| Finished | Oct 09 06:17:26 AM UTC 24 |
| Peak memory | 210752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839711228 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.839711228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2607287133 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 165272195055 ps |
| CPU time | 544.03 seconds |
| Started | Oct 09 06:11:45 AM UTC 24 |
| Finished | Oct 09 06:20:56 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607287133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2607287133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3223071351 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 484549608275 ps |
| CPU time | 333.61 seconds |
| Started | Oct 09 06:11:53 AM UTC 24 |
| Finished | Oct 09 06:17:31 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223071351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.3223071351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1591323785 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 490683728256 ps |
| CPU time | 337.67 seconds |
| Started | Oct 09 06:11:09 AM UTC 24 |
| Finished | Oct 09 06:16:51 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591323785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1591323785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.3226914786 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 336367460581 ps |
| CPU time | 290.05 seconds |
| Started | Oct 09 06:11:27 AM UTC 24 |
| Finished | Oct 09 06:16:21 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226914786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.3226914786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2441388122 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 537385268583 ps |
| CPU time | 710.18 seconds |
| Started | Oct 09 06:11:58 AM UTC 24 |
| Finished | Oct 09 06:23:56 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441388122 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.2441388122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2487827153 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 601261436833 ps |
| CPU time | 1533.71 seconds |
| Started | Oct 09 06:12:02 AM UTC 24 |
| Finished | Oct 09 06:37:50 AM UTC 24 |
| Peak memory | 213348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487827153 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.2487827153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3052568929 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 139232744584 ps |
| CPU time | 848.48 seconds |
| Started | Oct 09 06:12:27 AM UTC 24 |
| Finished | Oct 09 06:26:44 AM UTC 24 |
| Peak memory | 213700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052568929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3052568929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.2932321870 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 46720524998 ps |
| CPU time | 195.73 seconds |
| Started | Oct 09 06:12:26 AM UTC 24 |
| Finished | Oct 09 06:15:45 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932321870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2932321870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2534358823 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3802712333 ps |
| CPU time | 15.83 seconds |
| Started | Oct 09 06:12:08 AM UTC 24 |
| Finished | Oct 09 06:12:25 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534358823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2534358823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.331354669 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 5766389524 ps |
| CPU time | 16.39 seconds |
| Started | Oct 09 06:11:08 AM UTC 24 |
| Finished | Oct 09 06:11:26 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331354669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.331354669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3490940881 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 25568612670 ps |
| CPU time | 19.98 seconds |
| Started | Oct 09 06:12:44 AM UTC 24 |
| Finished | Oct 09 06:13:06 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490940881 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.3490940881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.951885196 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 111017056846 ps |
| CPU time | 11.12 seconds |
| Started | Oct 09 06:12:37 AM UTC 24 |
| Finished | Oct 09 06:12:50 AM UTC 24 |
| Peak memory | 221056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=951885196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.951885196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest |
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