T445 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3471507646 |
|
|
Feb 08 10:29:55 AM UTC 25 |
Feb 08 10:50:44 AM UTC 25 |
492019597383 ps |
T247 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.1756561491 |
|
|
Feb 08 10:43:15 AM UTC 25 |
Feb 08 10:50:45 AM UTC 25 |
528346422014 ps |
T446 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.1921334093 |
|
|
Feb 08 10:50:43 AM UTC 25 |
Feb 08 10:50:53 AM UTC 25 |
3458254631 ps |
T245 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1195312232 |
|
|
Feb 08 10:25:46 AM UTC 25 |
Feb 08 10:51:00 AM UTC 25 |
525169991428 ps |
T447 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2611784154 |
|
|
Feb 08 10:48:05 AM UTC 25 |
Feb 08 10:51:02 AM UTC 25 |
166440550227 ps |
T448 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.1651101740 |
|
|
Feb 08 10:51:03 AM UTC 25 |
Feb 08 10:51:06 AM UTC 25 |
514446211 ps |
T449 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.2037872690 |
|
|
Feb 08 10:45:54 AM UTC 25 |
Feb 08 10:51:18 AM UTC 25 |
327602355007 ps |
T291 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.57043325 |
|
|
Feb 08 10:39:32 AM UTC 25 |
Feb 08 10:51:22 AM UTC 25 |
518999038778 ps |
T450 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.1215903014 |
|
|
Feb 08 10:51:07 AM UTC 25 |
Feb 08 10:51:22 AM UTC 25 |
5654615093 ps |
T451 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2119068448 |
|
|
Feb 08 10:38:03 AM UTC 25 |
Feb 08 10:51:28 AM UTC 25 |
483871540420 ps |
T88 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.859942667 |
|
|
Feb 08 10:50:54 AM UTC 25 |
Feb 08 10:51:31 AM UTC 25 |
15934951198 ps |
T452 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.217566644 |
|
|
Feb 08 10:23:59 AM UTC 25 |
Feb 08 10:51:34 AM UTC 25 |
499251016457 ps |
T326 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.4123786448 |
|
|
Feb 08 10:45:43 AM UTC 25 |
Feb 08 10:51:40 AM UTC 25 |
229342416383 ps |
T453 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.3117983724 |
|
|
Feb 08 10:41:18 AM UTC 25 |
Feb 08 10:51:51 AM UTC 25 |
212066535041 ps |
T286 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.1437247693 |
|
|
Feb 08 10:48:30 AM UTC 25 |
Feb 08 10:51:56 AM UTC 25 |
350557931370 ps |
T454 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.915058764 |
|
|
Feb 08 10:46:19 AM UTC 25 |
Feb 08 10:52:09 AM UTC 25 |
202290707750 ps |
T296 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.887455096 |
|
|
Feb 08 10:37:03 AM UTC 25 |
Feb 08 10:52:12 AM UTC 25 |
387514288344 ps |
T455 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.1627353305 |
|
|
Feb 08 10:51:57 AM UTC 25 |
Feb 08 10:52:13 AM UTC 25 |
2836146559 ps |
T248 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2870378823 |
|
|
Feb 08 10:34:01 AM UTC 25 |
Feb 08 10:52:22 AM UTC 25 |
329388167736 ps |
T456 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.2589751420 |
|
|
Feb 08 10:50:45 AM UTC 25 |
Feb 08 10:52:31 AM UTC 25 |
39726508900 ps |
T259 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1142580728 |
|
|
Feb 08 10:45:37 AM UTC 25 |
Feb 08 10:52:32 AM UTC 25 |
768544103747 ps |
T457 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.3047538032 |
|
|
Feb 08 10:52:31 AM UTC 25 |
Feb 08 10:52:35 AM UTC 25 |
366077362 ps |
T258 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1810014803 |
|
|
Feb 08 10:45:55 AM UTC 25 |
Feb 08 10:52:40 AM UTC 25 |
494202273195 ps |
T458 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.134361669 |
|
|
Feb 08 10:52:33 AM UTC 25 |
Feb 08 10:52:41 AM UTC 25 |
5956221312 ps |
T32 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.939441320 |
|
|
Feb 08 10:48:56 AM UTC 25 |
Feb 08 10:52:56 AM UTC 25 |
50660109513 ps |
T459 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.1768157800 |
|
|
Feb 08 10:52:10 AM UTC 25 |
Feb 08 10:53:00 AM UTC 25 |
42345014161 ps |
T460 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3211133142 |
|
|
Feb 08 10:48:01 AM UTC 25 |
Feb 08 10:53:09 AM UTC 25 |
165792056680 ps |
T461 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.298187328 |
|
|
Feb 08 10:51:22 AM UTC 25 |
Feb 08 10:53:14 AM UTC 25 |
489931198454 ps |
T46 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3179613303 |
|
|
Feb 08 10:20:05 AM UTC 25 |
Feb 08 10:53:15 AM UTC 25 |
525200587833 ps |
T462 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.1322687570 |
|
|
Feb 08 10:51:23 AM UTC 25 |
Feb 08 10:53:31 AM UTC 25 |
165488729134 ps |
T89 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3818419144 |
|
|
Feb 08 10:47:00 AM UTC 25 |
Feb 08 10:53:34 AM UTC 25 |
549768503329 ps |
T463 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1551258486 |
|
|
Feb 08 10:53:32 AM UTC 25 |
Feb 08 10:53:37 AM UTC 25 |
3321585721 ps |
T341 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3719092931 |
|
|
Feb 08 10:44:30 AM UTC 25 |
Feb 08 10:53:43 AM UTC 25 |
163813094551 ps |
T464 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.3330300250 |
|
|
Feb 08 10:53:35 AM UTC 25 |
Feb 08 10:53:59 AM UTC 25 |
27196005922 ps |
T267 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1713766957 |
|
|
Feb 08 10:51:41 AM UTC 25 |
Feb 08 10:54:01 AM UTC 25 |
164268510224 ps |
T465 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.2249447659 |
|
|
Feb 08 10:54:02 AM UTC 25 |
Feb 08 10:54:05 AM UTC 25 |
383105373 ps |
T466 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.659959322 |
|
|
Feb 08 10:54:06 AM UTC 25 |
Feb 08 10:54:18 AM UTC 25 |
5582794666 ps |
T246 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3063435877 |
|
|
Feb 08 10:29:59 AM UTC 25 |
Feb 08 10:54:21 AM UTC 25 |
521326517146 ps |
T467 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.2040743990 |
|
|
Feb 08 10:53:59 AM UTC 25 |
Feb 08 10:54:23 AM UTC 25 |
8978431570 ps |
T235 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.747401529 |
|
|
Feb 08 10:50:42 AM UTC 25 |
Feb 08 10:54:25 AM UTC 25 |
352703740111 ps |
T362 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.779694315 |
|
|
Feb 08 10:46:50 AM UTC 25 |
Feb 08 10:54:31 AM UTC 25 |
92392284015 ps |
T64 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1972229213 |
|
|
Feb 08 10:26:35 AM UTC 25 |
Feb 08 10:54:32 AM UTC 25 |
1559102842198 ps |
T274 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.1581465163 |
|
|
Feb 08 10:49:09 AM UTC 25 |
Feb 08 10:54:45 AM UTC 25 |
500539877673 ps |
T45 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2332148780 |
|
|
Feb 08 10:53:44 AM UTC 25 |
Feb 08 10:54:52 AM UTC 25 |
209585208028 ps |
T468 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4125233538 |
|
|
Feb 08 10:32:46 AM UTC 25 |
Feb 08 10:54:56 AM UTC 25 |
495352856042 ps |
T469 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.2752018692 |
|
|
Feb 08 10:54:57 AM UTC 25 |
Feb 08 10:55:21 AM UTC 25 |
4851227709 ps |
T288 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2926178792 |
|
|
Feb 08 10:35:29 AM UTC 25 |
Feb 08 10:55:22 AM UTC 25 |
339683623785 ps |
T470 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4207612013 |
|
|
Feb 08 10:38:20 AM UTC 25 |
Feb 08 10:55:32 AM UTC 25 |
404870836103 ps |
T176 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3842224270 |
|
|
Feb 08 10:44:59 AM UTC 25 |
Feb 08 10:55:46 AM UTC 25 |
519112193300 ps |
T47 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3262194403 |
|
|
Feb 08 10:23:35 AM UTC 25 |
Feb 08 10:55:46 AM UTC 25 |
489544655766 ps |
T290 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2924408324 |
|
|
Feb 08 10:53:15 AM UTC 25 |
Feb 08 10:55:48 AM UTC 25 |
162844122478 ps |
T471 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.440094093 |
|
|
Feb 08 10:55:47 AM UTC 25 |
Feb 08 10:55:50 AM UTC 25 |
507916440 ps |
T197 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.1797370946 |
|
|
Feb 08 10:46:29 AM UTC 25 |
Feb 08 10:55:54 AM UTC 25 |
529959121624 ps |
T340 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3064063884 |
|
|
Feb 08 10:51:01 AM UTC 25 |
Feb 08 10:56:00 AM UTC 25 |
169865670541 ps |
T472 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1606990378 |
|
|
Feb 08 10:51:35 AM UTC 25 |
Feb 08 10:56:00 AM UTC 25 |
606451857033 ps |
T473 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.1645227686 |
|
|
Feb 08 10:52:41 AM UTC 25 |
Feb 08 10:56:02 AM UTC 25 |
484282306483 ps |
T299 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.196769148 |
|
|
Feb 08 10:35:58 AM UTC 25 |
Feb 08 10:56:08 AM UTC 25 |
534987090305 ps |
T474 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.3071981259 |
|
|
Feb 08 10:43:29 AM UTC 25 |
Feb 08 10:56:12 AM UTC 25 |
108240973227 ps |
T475 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.3710280239 |
|
|
Feb 08 10:55:48 AM UTC 25 |
Feb 08 10:56:17 AM UTC 25 |
5657410051 ps |
T318 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.1923062148 |
|
|
Feb 08 10:48:22 AM UTC 25 |
Feb 08 10:56:35 AM UTC 25 |
380556013262 ps |
T476 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.922933606 |
|
|
Feb 08 10:56:36 AM UTC 25 |
Feb 08 10:56:42 AM UTC 25 |
3031217586 ps |
T477 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2001533255 |
|
|
Feb 08 10:55:22 AM UTC 25 |
Feb 08 10:56:53 AM UTC 25 |
46224719590 ps |
T478 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4078277654 |
|
|
Feb 08 10:51:29 AM UTC 25 |
Feb 08 10:56:54 AM UTC 25 |
316257806859 ps |
T479 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3818637685 |
|
|
Feb 08 10:56:00 AM UTC 25 |
Feb 08 10:57:02 AM UTC 25 |
167952959979 ps |
T212 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1772540623 |
|
|
Feb 08 10:48:55 AM UTC 25 |
Feb 08 10:57:08 AM UTC 25 |
96738115484 ps |
T480 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.2533220673 |
|
|
Feb 08 10:49:46 AM UTC 25 |
Feb 08 10:57:11 AM UTC 25 |
331607429453 ps |
T481 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.3993831172 |
|
|
Feb 08 10:57:09 AM UTC 25 |
Feb 08 10:57:12 AM UTC 25 |
332173059 ps |
T482 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3511278407 |
|
|
Feb 08 10:45:30 AM UTC 25 |
Feb 08 10:57:16 AM UTC 25 |
108403341975 ps |
T483 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2133629125 |
|
|
Feb 08 10:54:26 AM UTC 25 |
Feb 08 10:57:16 AM UTC 25 |
326958356871 ps |
T484 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.960411981 |
|
|
Feb 08 10:51:18 AM UTC 25 |
Feb 08 10:57:16 AM UTC 25 |
322985331947 ps |
T485 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1877986516 |
|
|
Feb 08 10:54:23 AM UTC 25 |
Feb 08 10:57:18 AM UTC 25 |
164687483779 ps |
T335 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1996416661 |
|
|
Feb 08 10:51:52 AM UTC 25 |
Feb 08 10:57:22 AM UTC 25 |
174647607942 ps |
T486 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1873540915 |
|
|
Feb 08 10:56:43 AM UTC 25 |
Feb 08 10:57:35 AM UTC 25 |
31771755454 ps |
T164 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1012662791 |
|
|
Feb 08 10:40:10 AM UTC 25 |
Feb 08 10:57:36 AM UTC 25 |
372013667728 ps |
T487 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.25436139 |
|
|
Feb 08 10:56:09 AM UTC 25 |
Feb 08 10:57:39 AM UTC 25 |
208237528529 ps |
T488 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.3304111456 |
|
|
Feb 08 10:57:11 AM UTC 25 |
Feb 08 10:57:42 AM UTC 25 |
6075025489 ps |
T333 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2946396623 |
|
|
Feb 08 10:50:12 AM UTC 25 |
Feb 08 10:57:50 AM UTC 25 |
224398581882 ps |
T489 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.1998437375 |
|
|
Feb 08 10:49:52 AM UTC 25 |
Feb 08 10:57:55 AM UTC 25 |
167766323878 ps |
T490 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1984263136 |
|
|
Feb 08 10:57:40 AM UTC 25 |
Feb 08 10:58:03 AM UTC 25 |
4592340802 ps |
T491 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2388511961 |
|
|
Feb 08 10:57:43 AM UTC 25 |
Feb 08 10:58:22 AM UTC 25 |
36883257473 ps |
T492 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2663866731 |
|
|
Feb 08 10:58:23 AM UTC 25 |
Feb 08 10:58:26 AM UTC 25 |
411960017 ps |
T309 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1753865120 |
|
|
Feb 08 10:46:21 AM UTC 25 |
Feb 08 10:58:28 AM UTC 25 |
345475918873 ps |
T493 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.1940901001 |
|
|
Feb 08 10:51:33 AM UTC 25 |
Feb 08 10:58:31 AM UTC 25 |
348075607390 ps |
T494 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.510789600 |
|
|
Feb 08 10:53:01 AM UTC 25 |
Feb 08 10:58:34 AM UTC 25 |
578661084114 ps |
T495 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.3831525102 |
|
|
Feb 08 10:58:26 AM UTC 25 |
Feb 08 10:58:35 AM UTC 25 |
6022904692 ps |
T263 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1054072182 |
|
|
Feb 08 10:50:29 AM UTC 25 |
Feb 08 10:58:39 AM UTC 25 |
507228264691 ps |
T496 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.761533463 |
|
|
Feb 08 10:52:56 AM UTC 25 |
Feb 08 10:58:49 AM UTC 25 |
333987483432 ps |
T264 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.2243028946 |
|
|
Feb 08 10:54:32 AM UTC 25 |
Feb 08 10:58:55 AM UTC 25 |
525538983381 ps |
T209 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.2213852839 |
|
|
Feb 08 10:53:38 AM UTC 25 |
Feb 08 10:58:56 AM UTC 25 |
61812292475 ps |
T198 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.3986500501 |
|
|
Feb 08 10:56:18 AM UTC 25 |
Feb 08 10:59:09 AM UTC 25 |
341490797635 ps |
T497 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.2354695827 |
|
|
Feb 08 10:56:04 AM UTC 25 |
Feb 08 10:59:20 AM UTC 25 |
169639541706 ps |
T498 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1780015437 |
|
|
Feb 08 10:59:10 AM UTC 25 |
Feb 08 10:59:24 AM UTC 25 |
4997811789 ps |
T215 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2317651522 |
|
|
Feb 08 10:37:28 AM UTC 25 |
Feb 08 10:59:33 AM UTC 25 |
253771612548 ps |
T199 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.3621837557 |
|
|
Feb 08 10:56:00 AM UTC 25 |
Feb 08 10:59:36 AM UTC 25 |
167433536550 ps |
T499 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3558892761 |
|
|
Feb 08 10:56:55 AM UTC 25 |
Feb 08 10:59:40 AM UTC 25 |
68757878861 ps |
T500 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.3535834649 |
|
|
Feb 08 10:59:40 AM UTC 25 |
Feb 08 10:59:43 AM UTC 25 |
503748031 ps |
T501 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.3748302256 |
|
|
Feb 08 10:58:32 AM UTC 25 |
Feb 08 10:59:44 AM UTC 25 |
165950397717 ps |
T502 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.3519996969 |
|
|
Feb 08 10:59:43 AM UTC 25 |
Feb 08 10:59:49 AM UTC 25 |
6117605408 ps |
T503 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3421242900 |
|
|
Feb 08 10:58:36 AM UTC 25 |
Feb 08 11:00:00 AM UTC 25 |
324892427485 ps |
T262 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.1263852282 |
|
|
Feb 08 10:45:04 AM UTC 25 |
Feb 08 11:00:04 AM UTC 25 |
349502292021 ps |
T348 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.4070211985 |
|
|
Feb 08 10:43:37 AM UTC 25 |
Feb 08 11:00:12 AM UTC 25 |
320421272335 ps |
T504 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.343375104 |
|
|
Feb 08 10:50:24 AM UTC 25 |
Feb 08 11:00:15 AM UTC 25 |
616695134625 ps |
T505 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.1907230970 |
|
|
Feb 08 10:57:37 AM UTC 25 |
Feb 08 11:00:25 AM UTC 25 |
188317041884 ps |
T300 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1734910192 |
|
|
Feb 08 10:56:14 AM UTC 25 |
Feb 08 11:00:41 AM UTC 25 |
344853821507 ps |
T331 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1724992645 |
|
|
Feb 08 10:54:53 AM UTC 25 |
Feb 08 11:00:41 AM UTC 25 |
492341389456 ps |
T48 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1648720145 |
|
|
Feb 08 10:58:04 AM UTC 25 |
Feb 08 11:00:45 AM UTC 25 |
202004519432 ps |
T506 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.221119782 |
|
|
Feb 08 10:59:21 AM UTC 25 |
Feb 08 11:00:46 AM UTC 25 |
21535018453 ps |
T278 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2059649818 |
|
|
Feb 08 10:36:43 AM UTC 25 |
Feb 08 11:00:46 AM UTC 25 |
538412571637 ps |
T507 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.1284557503 |
|
|
Feb 08 10:57:37 AM UTC 25 |
Feb 08 11:00:47 AM UTC 25 |
196043472083 ps |
T508 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.630948477 |
|
|
Feb 08 10:59:50 AM UTC 25 |
Feb 08 11:00:48 AM UTC 25 |
166318987245 ps |
T509 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.3509649994 |
|
|
Feb 08 11:00:43 AM UTC 25 |
Feb 08 11:00:50 AM UTC 25 |
4277519577 ps |
T510 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.1316643697 |
|
|
Feb 08 11:00:49 AM UTC 25 |
Feb 08 11:00:52 AM UTC 25 |
619931631 ps |
T511 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.1201116669 |
|
|
Feb 08 11:00:47 AM UTC 25 |
Feb 08 11:01:06 AM UTC 25 |
21413111277 ps |
T512 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.3601523580 |
|
|
Feb 08 11:00:51 AM UTC 25 |
Feb 08 11:01:09 AM UTC 25 |
6024683294 ps |
T33 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.567491568 |
|
|
Feb 08 10:57:56 AM UTC 25 |
Feb 08 11:01:12 AM UTC 25 |
114892347600 ps |
T513 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1498779946 |
|
|
Feb 08 10:53:16 AM UTC 25 |
Feb 08 11:01:15 AM UTC 25 |
178693653485 ps |
T514 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1810067865 |
|
|
Feb 08 11:00:35 AM UTC 25 |
Feb 08 11:01:26 AM UTC 25 |
201512222277 ps |
T171 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.3511123023 |
|
|
Feb 08 10:42:27 AM UTC 25 |
Feb 08 11:01:28 AM UTC 25 |
370002300251 ps |
T172 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.3386450374 |
|
|
Feb 08 10:57:16 AM UTC 25 |
Feb 08 11:01:32 AM UTC 25 |
167741520380 ps |
T515 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.540436144 |
|
|
Feb 08 11:01:33 AM UTC 25 |
Feb 08 11:01:38 AM UTC 25 |
3574794271 ps |
T516 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2985422657 |
|
|
Feb 08 10:52:12 AM UTC 25 |
Feb 08 11:01:49 AM UTC 25 |
72558771944 ps |
T100 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.121492091 |
|
|
Feb 08 10:59:34 AM UTC 25 |
Feb 08 11:01:59 AM UTC 25 |
176112993026 ps |
T517 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.4102375729 |
|
|
Feb 08 11:01:39 AM UTC 25 |
Feb 08 11:02:00 AM UTC 25 |
35954632060 ps |
T518 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.280798721 |
|
|
Feb 08 10:59:37 AM UTC 25 |
Feb 08 11:02:02 AM UTC 25 |
327021709269 ps |
T519 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1730109033 |
|
|
Feb 08 11:02:03 AM UTC 25 |
Feb 08 11:02:06 AM UTC 25 |
361017552 ps |
T520 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2474357382 |
|
|
Feb 08 10:53:10 AM UTC 25 |
Feb 08 11:02:09 AM UTC 25 |
203219145470 ps |
T521 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.1286128657 |
|
|
Feb 08 11:02:06 AM UTC 25 |
Feb 08 11:02:22 AM UTC 25 |
5707205688 ps |
T522 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1139727079 |
|
|
Feb 08 10:38:01 AM UTC 25 |
Feb 08 11:02:23 AM UTC 25 |
488698444151 ps |
T523 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2820107770 |
|
|
Feb 08 10:55:55 AM UTC 25 |
Feb 08 11:02:28 AM UTC 25 |
162622522469 ps |
T224 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.4197973247 |
|
|
Feb 08 10:41:33 AM UTC 25 |
Feb 08 11:02:31 AM UTC 25 |
487617832792 ps |
T524 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.437686858 |
|
|
Feb 08 10:54:33 AM UTC 25 |
Feb 08 11:02:32 AM UTC 25 |
202878719219 ps |
T219 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2212314254 |
|
|
Feb 08 10:38:06 AM UTC 25 |
Feb 08 11:02:35 AM UTC 25 |
504169154921 ps |
T525 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.574101708 |
|
|
Feb 08 10:52:14 AM UTC 25 |
Feb 08 11:02:54 AM UTC 25 |
219649733908 ps |
T34 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1031742660 |
|
|
Feb 08 11:01:59 AM UTC 25 |
Feb 08 11:02:58 AM UTC 25 |
70568961457 ps |
T526 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.75209190 |
|
|
Feb 08 11:00:43 AM UTC 25 |
Feb 08 11:03:00 AM UTC 25 |
168719401846 ps |
T527 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.1617496575 |
|
|
Feb 08 11:02:59 AM UTC 25 |
Feb 08 11:03:03 AM UTC 25 |
4535736335 ps |
T528 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.863095953 |
|
|
Feb 08 10:58:57 AM UTC 25 |
Feb 08 11:03:28 AM UTC 25 |
188823522342 ps |
T529 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.4292415578 |
|
|
Feb 08 11:03:01 AM UTC 25 |
Feb 08 11:03:28 AM UTC 25 |
23734890321 ps |
T530 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3643546322 |
|
|
Feb 08 11:00:35 AM UTC 25 |
Feb 08 11:03:44 AM UTC 25 |
196132880578 ps |
T307 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.1332971820 |
|
|
Feb 08 11:01:27 AM UTC 25 |
Feb 08 11:03:46 AM UTC 25 |
527728855728 ps |
T531 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.835471398 |
|
|
Feb 08 11:03:45 AM UTC 25 |
Feb 08 11:03:48 AM UTC 25 |
461131441 ps |
T342 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.1561020750 |
|
|
Feb 08 10:52:41 AM UTC 25 |
Feb 08 11:03:50 AM UTC 25 |
330168704414 ps |
T310 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3813785720 |
|
|
Feb 08 10:27:49 AM UTC 25 |
Feb 08 11:03:51 AM UTC 25 |
463265987229 ps |
T532 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.1285915428 |
|
|
Feb 08 11:03:47 AM UTC 25 |
Feb 08 11:04:16 AM UTC 25 |
5627899719 ps |
T533 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1150337939 |
|
|
Feb 08 10:40:08 AM UTC 25 |
Feb 08 11:04:20 AM UTC 25 |
492873399336 ps |
T534 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1676436747 |
|
|
Feb 08 10:57:16 AM UTC 25 |
Feb 08 11:04:24 AM UTC 25 |
166168370480 ps |
T295 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1478844070 |
|
|
Feb 08 11:01:13 AM UTC 25 |
Feb 08 11:04:30 AM UTC 25 |
190764858361 ps |
T535 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1635122940 |
|
|
Feb 08 10:57:19 AM UTC 25 |
Feb 08 11:05:00 AM UTC 25 |
166835369094 ps |
T536 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.45582641 |
|
|
Feb 08 10:49:21 AM UTC 25 |
Feb 08 11:05:03 AM UTC 25 |
328503579037 ps |
T537 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.2173782978 |
|
|
Feb 08 11:05:04 AM UTC 25 |
Feb 08 11:05:29 AM UTC 25 |
5356051511 ps |
T265 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3211138262 |
|
|
Feb 08 11:04:21 AM UTC 25 |
Feb 08 11:05:36 AM UTC 25 |
177550988498 ps |
T358 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2529021382 |
|
|
Feb 08 10:56:54 AM UTC 25 |
Feb 08 11:05:36 AM UTC 25 |
118781445965 ps |
T538 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.2332166311 |
|
|
Feb 08 11:02:32 AM UTC 25 |
Feb 08 11:05:40 AM UTC 25 |
364947919727 ps |
T539 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2287502021 |
|
|
Feb 08 11:05:29 AM UTC 25 |
Feb 08 11:06:14 AM UTC 25 |
45599845002 ps |
T540 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.989574272 |
|
|
Feb 08 11:06:14 AM UTC 25 |
Feb 08 11:06:18 AM UTC 25 |
445061395 ps |
T541 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1857547249 |
|
|
Feb 08 11:00:33 AM UTC 25 |
Feb 08 11:06:18 AM UTC 25 |
353321973381 ps |
T231 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.846664164 |
|
|
Feb 08 10:57:03 AM UTC 25 |
Feb 08 11:06:19 AM UTC 25 |
192245957748 ps |
T287 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.293284387 |
|
|
Feb 08 10:58:40 AM UTC 25 |
Feb 08 11:06:21 AM UTC 25 |
355435644390 ps |
T542 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.458307175 |
|
|
Feb 08 10:58:34 AM UTC 25 |
Feb 08 11:06:23 AM UTC 25 |
165565774682 ps |
T543 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.4065298970 |
|
|
Feb 08 11:06:18 AM UTC 25 |
Feb 08 11:06:28 AM UTC 25 |
6110799682 ps |
T544 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1398797102 |
|
|
Feb 08 10:44:18 AM UTC 25 |
Feb 08 11:06:34 AM UTC 25 |
492886791173 ps |
T545 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.445032488 |
|
|
Feb 08 11:00:47 AM UTC 25 |
Feb 08 11:06:45 AM UTC 25 |
83492111175 ps |
T314 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.2990534177 |
|
|
Feb 08 10:58:29 AM UTC 25 |
Feb 08 11:06:49 AM UTC 25 |
494848771751 ps |
T546 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3661296687 |
|
|
Feb 08 11:02:55 AM UTC 25 |
Feb 08 11:07:08 AM UTC 25 |
347571111226 ps |
T547 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.2570565173 |
|
|
Feb 08 10:52:36 AM UTC 25 |
Feb 08 11:07:11 AM UTC 25 |
327279325534 ps |
T548 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.3562902599 |
|
|
Feb 08 11:06:19 AM UTC 25 |
Feb 08 11:07:12 AM UTC 25 |
162771482379 ps |
T549 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1086752236 |
|
|
Feb 08 10:57:16 AM UTC 25 |
Feb 08 11:07:13 AM UTC 25 |
164988686800 ps |
T550 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2497592632 |
|
|
Feb 08 10:52:23 AM UTC 25 |
Feb 08 11:07:15 AM UTC 25 |
567901294329 ps |
T551 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.2976029929 |
|
|
Feb 08 11:01:11 AM UTC 25 |
Feb 08 11:07:22 AM UTC 25 |
331372315192 ps |
T552 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1540030797 |
|
|
Feb 08 11:07:23 AM UTC 25 |
Feb 08 11:07:27 AM UTC 25 |
503963593 ps |
T553 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.66960584 |
|
|
Feb 08 11:07:09 AM UTC 25 |
Feb 08 11:07:28 AM UTC 25 |
3874382424 ps |
T554 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.1238507281 |
|
|
Feb 08 11:07:27 AM UTC 25 |
Feb 08 11:07:38 AM UTC 25 |
5877929957 ps |
T555 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.676798331 |
|
|
Feb 08 11:07:12 AM UTC 25 |
Feb 08 11:07:39 AM UTC 25 |
28603578466 ps |
T556 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.3270322358 |
|
|
Feb 08 10:54:18 AM UTC 25 |
Feb 08 11:07:40 AM UTC 25 |
325116296379 ps |
T557 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.826655708 |
|
|
Feb 08 11:05:01 AM UTC 25 |
Feb 08 11:07:51 AM UTC 25 |
164227894514 ps |
T558 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.4214541749 |
|
|
Feb 08 11:04:25 AM UTC 25 |
Feb 08 11:08:03 AM UTC 25 |
214240289032 ps |
T297 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3865377586 |
|
|
Feb 08 10:54:46 AM UTC 25 |
Feb 08 11:08:18 AM UTC 25 |
512665966109 ps |
T220 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3564240552 |
|
|
Feb 08 11:03:29 AM UTC 25 |
Feb 08 11:08:24 AM UTC 25 |
370506978817 ps |
T559 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3428833542 |
|
|
Feb 08 11:04:18 AM UTC 25 |
Feb 08 11:08:28 AM UTC 25 |
162386452371 ps |
T560 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.86040430 |
|
|
Feb 08 10:50:46 AM UTC 25 |
Feb 08 11:08:42 AM UTC 25 |
141875062416 ps |
T303 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3775769302 |
|
|
Feb 08 11:02:09 AM UTC 25 |
Feb 08 11:08:49 AM UTC 25 |
494094907116 ps |
T561 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.3863693049 |
|
|
Feb 08 11:08:29 AM UTC 25 |
Feb 08 11:08:50 AM UTC 25 |
5324741508 ps |
T216 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.2609950234 |
|
|
Feb 08 10:57:51 AM UTC 25 |
Feb 08 11:08:52 AM UTC 25 |
107840235986 ps |
T562 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1089925642 |
|
|
Feb 08 11:08:53 AM UTC 25 |
Feb 08 11:09:01 AM UTC 25 |
16510933054 ps |
T328 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.451111052 |
|
|
Feb 08 11:05:40 AM UTC 25 |
Feb 08 11:09:04 AM UTC 25 |
667620458979 ps |
T563 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.4239585340 |
|
|
Feb 08 11:09:02 AM UTC 25 |
Feb 08 11:09:04 AM UTC 25 |
446551465 ps |
T35 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4097496427 |
|
|
Feb 08 11:05:36 AM UTC 25 |
Feb 08 11:09:18 AM UTC 25 |
94320290390 ps |
T564 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.1367504903 |
|
|
Feb 08 11:00:49 AM UTC 25 |
Feb 08 11:09:36 AM UTC 25 |
200575072062 ps |
T565 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1819933160 |
|
|
Feb 08 11:09:05 AM UTC 25 |
Feb 08 11:09:37 AM UTC 25 |
5893400305 ps |
T566 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.82174561 |
|
|
Feb 08 11:08:43 AM UTC 25 |
Feb 08 11:09:49 AM UTC 25 |
28863661616 ps |
T567 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1090930161 |
|
|
Feb 08 11:01:12 AM UTC 25 |
Feb 08 11:09:56 AM UTC 25 |
488293567998 ps |
T568 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2381345733 |
|
|
Feb 08 10:59:45 AM UTC 25 |
Feb 08 11:09:58 AM UTC 25 |
328950920660 ps |
T569 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4219362400 |
|
|
Feb 08 11:01:16 AM UTC 25 |
Feb 08 11:10:01 AM UTC 25 |
601394100135 ps |
T570 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.747081295 |
|
|
Feb 08 11:02:24 AM UTC 25 |
Feb 08 11:10:34 AM UTC 25 |
161230713409 ps |
T571 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3554078922 |
|
|
Feb 08 11:02:33 AM UTC 25 |
Feb 08 11:10:37 AM UTC 25 |
193311981268 ps |
T572 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.2802292616 |
|
|
Feb 08 11:10:35 AM UTC 25 |
Feb 08 11:10:39 AM UTC 25 |
3223302130 ps |
T177 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.772861343 |
|
|
Feb 08 11:06:29 AM UTC 25 |
Feb 08 11:10:40 AM UTC 25 |
423499417796 ps |
T573 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.1771507580 |
|
|
Feb 08 11:01:50 AM UTC 25 |
Feb 08 11:10:42 AM UTC 25 |
124959118093 ps |
T218 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.619672181 |
|
|
Feb 08 10:55:23 AM UTC 25 |
Feb 08 11:10:58 AM UTC 25 |
137657350164 ps |
T574 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.1363992475 |
|
|
Feb 08 11:10:59 AM UTC 25 |
Feb 08 11:11:03 AM UTC 25 |
292143395 ps |
T575 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2895121310 |
|
|
Feb 08 11:06:35 AM UTC 25 |
Feb 08 11:11:03 AM UTC 25 |
396716265804 ps |
T576 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.4149155920 |
|
|
Feb 08 11:11:04 AM UTC 25 |
Feb 08 11:11:10 AM UTC 25 |
6185170342 ps |
T577 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.449157358 |
|
|
Feb 08 11:10:38 AM UTC 25 |
Feb 08 11:11:17 AM UTC 25 |
35304549755 ps |
T578 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.812635897 |
|
|
Feb 08 11:07:38 AM UTC 25 |
Feb 08 11:11:22 AM UTC 25 |
324856304987 ps |
T213 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2015397987 |
|
|
Feb 08 10:55:33 AM UTC 25 |
Feb 08 11:11:27 AM UTC 25 |
1353912767974 ps |
T579 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.2697001796 |
|
|
Feb 08 11:03:03 AM UTC 25 |
Feb 08 11:11:32 AM UTC 25 |
69824335782 ps |
T580 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2377145574 |
|
|
Feb 08 11:08:20 AM UTC 25 |
Feb 08 11:11:33 AM UTC 25 |
551528257372 ps |
T581 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3486951542 |
|
|
Feb 08 11:10:02 AM UTC 25 |
Feb 08 11:11:38 AM UTC 25 |
338039505812 ps |
T582 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.1360507734 |
|
|
Feb 08 11:09:18 AM UTC 25 |
Feb 08 11:12:03 AM UTC 25 |
167346740144 ps |
T583 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.1423529211 |
|
|
Feb 08 11:12:05 AM UTC 25 |
Feb 08 11:12:11 AM UTC 25 |
4127258625 ps |
T584 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3519355853 |
|
|
Feb 08 10:57:22 AM UTC 25 |
Feb 08 11:12:13 AM UTC 25 |
617208199836 ps |
T194 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1834509617 |
|
|
Feb 08 11:09:59 AM UTC 25 |
Feb 08 11:12:16 AM UTC 25 |
511477053831 ps |
T322 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.1949405440 |
|
|
Feb 08 11:01:29 AM UTC 25 |
Feb 08 11:12:29 AM UTC 25 |
323461707556 ps |
T330 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.1258789212 |
|
|
Feb 08 11:09:37 AM UTC 25 |
Feb 08 11:12:37 AM UTC 25 |
162920285388 ps |
T585 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.798745207 |
|
|
Feb 08 11:05:36 AM UTC 25 |
Feb 08 11:12:41 AM UTC 25 |
68782222579 ps |
T586 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.160721083 |
|
|
Feb 08 11:12:38 AM UTC 25 |
Feb 08 11:12:41 AM UTC 25 |
387536012 ps |
T587 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1507965044 |
|
|
Feb 08 11:03:50 AM UTC 25 |
Feb 08 11:12:57 AM UTC 25 |
160331858708 ps |
T588 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.415467124 |
|
|
Feb 08 11:12:41 AM UTC 25 |
Feb 08 11:13:07 AM UTC 25 |
6021568094 ps |
T327 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.3098374877 |
|
|
Feb 08 10:47:16 AM UTC 25 |
Feb 08 11:13:10 AM UTC 25 |
557399160245 ps |
T589 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2895604603 |
|
|
Feb 08 11:12:12 AM UTC 25 |
Feb 08 11:13:22 AM UTC 25 |
32655483384 ps |
T590 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.668006187 |
|
|
Feb 08 10:48:18 AM UTC 25 |
Feb 08 11:13:26 AM UTC 25 |
598751102701 ps |
T591 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.266482359 |
|
|
Feb 08 10:54:21 AM UTC 25 |
Feb 08 11:13:31 AM UTC 25 |
488860775942 ps |
T592 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2659612991 |
|
|
Feb 08 11:07:40 AM UTC 25 |
Feb 08 11:13:36 AM UTC 25 |
165664786679 ps |
T593 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.1425368875 |
|
|
Feb 08 11:06:21 AM UTC 25 |
Feb 08 11:13:38 AM UTC 25 |
162891955941 ps |
T594 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.847856520 |
|
|
Feb 08 11:00:53 AM UTC 25 |
Feb 08 11:13:44 AM UTC 25 |
489177786245 ps |
T595 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.1523320103 |
|
|
Feb 08 11:13:40 AM UTC 25 |
Feb 08 11:13:45 AM UTC 25 |
3094704332 ps |
T596 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3615774675 |
|
|
Feb 08 11:02:29 AM UTC 25 |
Feb 08 11:13:50 AM UTC 25 |
334190308467 ps |
T321 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4028331960 |
|
|
Feb 08 11:10:41 AM UTC 25 |
Feb 08 11:13:51 AM UTC 25 |
194525996102 ps |
T597 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.58573595 |
|
|
Feb 08 10:59:25 AM UTC 25 |
Feb 08 11:14:00 AM UTC 25 |
114466380199 ps |
T598 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.1165579990 |
|
|
Feb 08 11:14:01 AM UTC 25 |
Feb 08 11:14:04 AM UTC 25 |
307457535 ps |
T109 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3994754438 |
|
|
Feb 08 11:00:47 AM UTC 25 |
Feb 08 11:14:05 AM UTC 25 |
165692044388 ps |
T178 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.1136142683 |
|
|
Feb 08 11:11:39 AM UTC 25 |
Feb 08 11:14:06 AM UTC 25 |
492136067228 ps |
T599 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.584347142 |
|
|
Feb 08 11:04:31 AM UTC 25 |
Feb 08 11:14:11 AM UTC 25 |
176421095174 ps |
T600 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3155138954 |
|
|
Feb 08 10:44:45 AM UTC 25 |
Feb 08 11:14:27 AM UTC 25 |
597355767122 ps |
T279 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.878627183 |
|
|
Feb 08 11:00:00 AM UTC 25 |
Feb 08 11:14:28 AM UTC 25 |
325661763841 ps |
T601 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.15152118 |
|
|
Feb 08 11:14:05 AM UTC 25 |
Feb 08 11:14:36 AM UTC 25 |
6108811005 ps |
T602 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.3580975373 |
|
|
Feb 08 11:02:36 AM UTC 25 |
Feb 08 11:14:37 AM UTC 25 |
164878666237 ps |
T603 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2027585910 |
|
|
Feb 08 10:48:14 AM UTC 25 |
Feb 08 11:14:43 AM UTC 25 |
482359111618 ps |
T604 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.4122049894 |
|
|
Feb 08 11:13:45 AM UTC 25 |
Feb 08 11:14:55 AM UTC 25 |
24912283935 ps |
T605 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3984505612 |
|
|
Feb 08 11:11:23 AM UTC 25 |
Feb 08 11:15:03 AM UTC 25 |
480900554505 ps |
T606 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.242294771 |
|
|
Feb 08 11:14:56 AM UTC 25 |
Feb 08 11:15:04 AM UTC 25 |
5201320145 ps |
T607 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.267577144 |
|
|
Feb 08 11:11:11 AM UTC 25 |
Feb 08 11:15:09 AM UTC 25 |
163598650713 ps |
T608 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.3910326113 |
|
|
Feb 08 11:14:06 AM UTC 25 |
Feb 08 11:15:19 AM UTC 25 |
159377987434 ps |
T609 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1227680838 |
|
|
Feb 08 11:06:25 AM UTC 25 |
Feb 08 11:15:25 AM UTC 25 |
170048855433 ps |
T260 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1354563746 |
|
|
Feb 08 10:48:13 AM UTC 25 |
Feb 08 11:15:27 AM UTC 25 |
481344691581 ps |
T251 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1743219553 |
|
|
Feb 08 11:06:46 AM UTC 25 |
Feb 08 11:15:27 AM UTC 25 |
426465263642 ps |
T610 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2051554106 |
|
|
Feb 08 11:15:04 AM UTC 25 |
Feb 08 11:15:28 AM UTC 25 |
23127656926 ps |
T611 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.171633460 |
|
|
Feb 08 11:15:26 AM UTC 25 |
Feb 08 11:15:30 AM UTC 25 |
339714568 ps |
T233 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3634941669 |
|
|
Feb 08 11:06:22 AM UTC 25 |
Feb 08 11:15:31 AM UTC 25 |
159178823311 ps |
T612 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.1773282315 |
|
|
Feb 08 11:15:28 AM UTC 25 |
Feb 08 11:15:36 AM UTC 25 |
6001840212 ps |