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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.64


Total test records in report: 918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T799 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.400593658 Feb 08 11:31:21 AM UTC 25 Feb 08 11:54:28 AM UTC 25 486925774656 ps
T252 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2693208085 Feb 08 11:32:02 AM UTC 25 Feb 08 12:01:43 PM UTC 25 558533124920 ps
T800 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3855089979 Feb 08 11:30:30 AM UTC 25 Feb 08 12:03:07 PM UTC 25 620408712654 ps
T75 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.368408014 Feb 08 11:34:30 AM UTC 25 Feb 08 11:34:38 AM UTC 25 521794005 ps
T801 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1503560207 Feb 08 11:34:38 AM UTC 25 Feb 08 11:34:41 AM UTC 25 438861390 ps
T110 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3408227608 Feb 08 11:34:41 AM UTC 25 Feb 08 11:34:45 AM UTC 25 1163181457 ps
T72 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3181106977 Feb 08 11:34:33 AM UTC 25 Feb 08 11:34:47 AM UTC 25 4778332416 ps
T122 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3856593751 Feb 08 11:34:46 AM UTC 25 Feb 08 11:34:51 AM UTC 25 362321756 ps
T111 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4275962744 Feb 08 11:34:51 AM UTC 25 Feb 08 11:34:56 AM UTC 25 551323309 ps
T76 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1034985249 Feb 08 11:34:59 AM UTC 25 Feb 08 11:35:03 AM UTC 25 449733490 ps
T67 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3083870203 Feb 08 11:34:57 AM UTC 25 Feb 08 11:35:05 AM UTC 25 2197222571 ps
T79 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.375016844 Feb 08 11:35:00 AM UTC 25 Feb 08 11:35:05 AM UTC 25 533530222 ps
T802 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1454296406 Feb 08 11:35:05 AM UTC 25 Feb 08 11:35:08 AM UTC 25 492975515 ps
T127 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1158813466 Feb 08 11:35:06 AM UTC 25 Feb 08 11:35:09 AM UTC 25 504858431 ps
T128 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2697747577 Feb 08 11:35:06 AM UTC 25 Feb 08 11:35:11 AM UTC 25 742965953 ps
T129 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2117146713 Feb 08 11:35:09 AM UTC 25 Feb 08 11:35:14 AM UTC 25 1287219865 ps
T83 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.932984534 Feb 08 11:35:12 AM UTC 25 Feb 08 11:35:15 AM UTC 25 565961230 ps
T80 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2262287580 Feb 08 11:35:15 AM UTC 25 Feb 08 11:35:19 AM UTC 25 543412511 ps
T73 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.574925675 Feb 08 11:35:04 AM UTC 25 Feb 08 11:35:19 AM UTC 25 4469167018 ps
T68 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3843151505 Feb 08 11:35:10 AM UTC 25 Feb 08 11:35:21 AM UTC 25 1935989514 ps
T74 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.994322345 Feb 08 11:35:15 AM UTC 25 Feb 08 11:35:21 AM UTC 25 5755776180 ps
T803 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3662498572 Feb 08 11:35:19 AM UTC 25 Feb 08 11:35:22 AM UTC 25 454669650 ps
T112 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1407663959 Feb 08 11:35:20 AM UTC 25 Feb 08 11:35:24 AM UTC 25 1058177689 ps
T123 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1295591031 Feb 08 11:35:21 AM UTC 25 Feb 08 11:35:24 AM UTC 25 582818447 ps
T113 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.85292226 Feb 08 11:35:23 AM UTC 25 Feb 08 11:35:28 AM UTC 25 445168278 ps
T90 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1618653670 Feb 08 11:35:25 AM UTC 25 Feb 08 11:35:30 AM UTC 25 448330533 ps
T69 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3932108857 Feb 08 11:34:47 AM UTC 25 Feb 08 11:35:32 AM UTC 25 35224152187 ps
T124 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1558416835 Feb 08 11:35:24 AM UTC 25 Feb 08 11:35:33 AM UTC 25 2147372666 ps
T804 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3433818091 Feb 08 11:35:31 AM UTC 25 Feb 08 11:35:33 AM UTC 25 325339814 ps
T82 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.852186120 Feb 08 11:35:28 AM UTC 25 Feb 08 11:35:33 AM UTC 25 311450740 ps
T805 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2827551439 Feb 08 11:35:33 AM UTC 25 Feb 08 11:35:37 AM UTC 25 766409997 ps
T114 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.967071125 Feb 08 11:35:34 AM UTC 25 Feb 08 11:35:37 AM UTC 25 492535200 ps
T77 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.931408452 Feb 08 11:35:29 AM UTC 25 Feb 08 11:35:37 AM UTC 25 4463571961 ps
T115 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3969811653 Feb 08 11:35:34 AM UTC 25 Feb 08 11:35:38 AM UTC 25 670979357 ps
T108 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1339705391 Feb 08 11:35:35 AM UTC 25 Feb 08 11:35:40 AM UTC 25 528371240 ps
T806 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1903510943 Feb 08 11:35:38 AM UTC 25 Feb 08 11:35:41 AM UTC 25 389667099 ps
T116 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.21784392 Feb 08 11:35:38 AM UTC 25 Feb 08 11:35:41 AM UTC 25 960421545 ps
T125 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3219024020 Feb 08 11:35:38 AM UTC 25 Feb 08 11:35:41 AM UTC 25 315313619 ps
T70 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4094614724 Feb 08 11:35:35 AM UTC 25 Feb 08 11:35:42 AM UTC 25 2416967322 ps
T84 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1250080670 Feb 08 11:35:37 AM UTC 25 Feb 08 11:35:42 AM UTC 25 410789207 ps
T807 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3253146555 Feb 08 11:35:42 AM UTC 25 Feb 08 11:35:46 AM UTC 25 561121478 ps
T117 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1898291154 Feb 08 11:35:40 AM UTC 25 Feb 08 11:35:46 AM UTC 25 815740418 ps
T81 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.175133623 Feb 08 11:35:42 AM UTC 25 Feb 08 11:35:47 AM UTC 25 362338693 ps
T808 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.4179530693 Feb 08 11:35:42 AM UTC 25 Feb 08 11:35:47 AM UTC 25 530356965 ps
T86 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1542288620 Feb 08 11:35:42 AM UTC 25 Feb 08 11:35:48 AM UTC 25 828300903 ps
T809 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.328480380 Feb 08 11:35:47 AM UTC 25 Feb 08 11:35:50 AM UTC 25 429616421 ps
T71 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3077991182 Feb 08 11:35:41 AM UTC 25 Feb 08 11:35:51 AM UTC 25 4300416499 ps
T810 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1385656592 Feb 08 11:35:49 AM UTC 25 Feb 08 11:35:52 AM UTC 25 497717353 ps
T126 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3307075829 Feb 08 11:35:49 AM UTC 25 Feb 08 11:35:53 AM UTC 25 392073074 ps
T85 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3608584109 Feb 08 11:35:47 AM UTC 25 Feb 08 11:35:53 AM UTC 25 503535484 ps
T811 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1017942177 Feb 08 11:35:51 AM UTC 25 Feb 08 11:35:55 AM UTC 25 709142159 ps
T812 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3464458421 Feb 08 11:35:51 AM UTC 25 Feb 08 11:35:56 AM UTC 25 489671413 ps
T813 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1975378251 Feb 08 11:35:53 AM UTC 25 Feb 08 11:35:56 AM UTC 25 506431077 ps
T118 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2818601801 Feb 08 11:35:54 AM UTC 25 Feb 08 11:35:57 AM UTC 25 611401891 ps
T814 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4180606644 Feb 08 11:35:22 AM UTC 25 Feb 08 11:35:58 AM UTC 25 26380168504 ps
T815 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1776008414 Feb 08 11:35:54 AM UTC 25 Feb 08 11:35:58 AM UTC 25 4741948142 ps
T816 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2697641443 Feb 08 11:35:56 AM UTC 25 Feb 08 11:35:59 AM UTC 25 421834113 ps
T352 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4028151757 Feb 08 11:35:42 AM UTC 25 Feb 08 11:36:00 AM UTC 25 8636153207 ps
T817 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3334901158 Feb 08 11:35:56 AM UTC 25 Feb 08 11:36:00 AM UTC 25 759203523 ps
T818 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4040615903 Feb 08 11:35:43 AM UTC 25 Feb 08 11:36:00 AM UTC 25 5194404464 ps
T78 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1836424974 Feb 08 11:35:38 AM UTC 25 Feb 08 11:36:01 AM UTC 25 7823890894 ps
T819 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3651512143 Feb 08 11:35:52 AM UTC 25 Feb 08 11:36:01 AM UTC 25 4814416427 ps
T820 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.253082431 Feb 08 11:35:58 AM UTC 25 Feb 08 11:36:02 AM UTC 25 313779626 ps
T821 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2884035965 Feb 08 11:35:07 AM UTC 25 Feb 08 11:36:04 AM UTC 25 26074985275 ps
T120 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.260938602 Feb 08 11:35:58 AM UTC 25 Feb 08 11:36:04 AM UTC 25 527878984 ps
T822 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.566084735 Feb 08 11:36:02 AM UTC 25 Feb 08 11:36:05 AM UTC 25 559136623 ps
T823 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3690843981 Feb 08 11:36:00 AM UTC 25 Feb 08 11:36:05 AM UTC 25 347614271 ps
T824 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2139135009 Feb 08 11:36:02 AM UTC 25 Feb 08 11:36:06 AM UTC 25 437036169 ps
T825 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2450399179 Feb 08 11:36:03 AM UTC 25 Feb 08 11:36:06 AM UTC 25 489095358 ps
T826 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4224342146 Feb 08 11:36:00 AM UTC 25 Feb 08 11:36:06 AM UTC 25 367499654 ps
T827 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3601896866 Feb 08 11:36:05 AM UTC 25 Feb 08 11:36:08 AM UTC 25 298530501 ps
T828 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3534582882 Feb 08 11:36:03 AM UTC 25 Feb 08 11:36:09 AM UTC 25 594152038 ps
T829 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3175898170 Feb 08 11:35:59 AM UTC 25 Feb 08 11:36:10 AM UTC 25 2527458867 ps
T830 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3801586755 Feb 08 11:36:07 AM UTC 25 Feb 08 11:36:10 AM UTC 25 498184751 ps
T119 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3015989235 Feb 08 11:36:06 AM UTC 25 Feb 08 11:36:10 AM UTC 25 352196442 ps
T831 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3508489314 Feb 08 11:36:06 AM UTC 25 Feb 08 11:36:11 AM UTC 25 503893205 ps
T832 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.872626820 Feb 08 11:36:09 AM UTC 25 Feb 08 11:36:13 AM UTC 25 380539117 ps
T833 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4182165928 Feb 08 11:36:07 AM UTC 25 Feb 08 11:36:13 AM UTC 25 4467504046 ps
T834 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3087574642 Feb 08 11:36:06 AM UTC 25 Feb 08 11:36:13 AM UTC 25 2651125006 ps
T835 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4027905157 Feb 08 11:36:07 AM UTC 25 Feb 08 11:36:14 AM UTC 25 396244022 ps
T836 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1884427277 Feb 08 11:35:57 AM UTC 25 Feb 08 11:36:14 AM UTC 25 4073991762 ps
T837 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2865217110 Feb 08 11:36:12 AM UTC 25 Feb 08 11:36:16 AM UTC 25 425609290 ps
T353 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2800566397 Feb 08 11:36:01 AM UTC 25 Feb 08 11:36:16 AM UTC 25 8229295512 ps
T838 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3275732306 Feb 08 11:36:11 AM UTC 25 Feb 08 11:36:16 AM UTC 25 417194799 ps
T839 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2044604949 Feb 08 11:36:13 AM UTC 25 Feb 08 11:36:16 AM UTC 25 429706528 ps
T840 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2108688915 Feb 08 11:36:11 AM UTC 25 Feb 08 11:36:17 AM UTC 25 447080131 ps
T841 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1284331279 Feb 08 11:36:13 AM UTC 25 Feb 08 11:36:18 AM UTC 25 4415913730 ps
T842 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.859910785 Feb 08 11:36:13 AM UTC 25 Feb 08 11:36:18 AM UTC 25 369643368 ps
T843 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1503258050 Feb 08 11:36:15 AM UTC 25 Feb 08 11:36:19 AM UTC 25 560799721 ps
T844 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1424992821 Feb 08 11:36:17 AM UTC 25 Feb 08 11:36:20 AM UTC 25 447278643 ps
T845 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3863528822 Feb 08 11:36:11 AM UTC 25 Feb 08 11:36:21 AM UTC 25 4533464728 ps
T846 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.549261660 Feb 08 11:36:02 AM UTC 25 Feb 08 11:36:21 AM UTC 25 4526221909 ps
T847 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2995173462 Feb 08 11:36:17 AM UTC 25 Feb 08 11:36:21 AM UTC 25 477854949 ps
T848 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3709328761 Feb 08 11:36:17 AM UTC 25 Feb 08 11:36:21 AM UTC 25 390198137 ps
T849 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2755400431 Feb 08 11:35:48 AM UTC 25 Feb 08 11:36:22 AM UTC 25 8991931516 ps
T850 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.3917523398 Feb 08 11:36:19 AM UTC 25 Feb 08 11:36:22 AM UTC 25 338143618 ps
T851 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3289090320 Feb 08 11:36:18 AM UTC 25 Feb 08 11:36:22 AM UTC 25 394018996 ps
T852 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3828871008 Feb 08 11:35:49 AM UTC 25 Feb 08 11:36:22 AM UTC 25 4908978654 ps
T853 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1186966455 Feb 08 11:36:20 AM UTC 25 Feb 08 11:36:23 AM UTC 25 488857863 ps
T854 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1533409603 Feb 08 11:36:21 AM UTC 25 Feb 08 11:36:25 AM UTC 25 420576699 ps
T855 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2278559160 Feb 08 11:36:17 AM UTC 25 Feb 08 11:36:27 AM UTC 25 2073326191 ps
T856 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.424279674 Feb 08 11:36:22 AM UTC 25 Feb 08 11:36:27 AM UTC 25 348986032 ps
T857 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1022948100 Feb 08 11:36:23 AM UTC 25 Feb 08 11:36:27 AM UTC 25 454470488 ps
T858 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3074599558 Feb 08 11:36:22 AM UTC 25 Feb 08 11:36:27 AM UTC 25 407607153 ps
T859 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2245630822 Feb 08 11:36:21 AM UTC 25 Feb 08 11:36:27 AM UTC 25 2909683374 ps
T860 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.474326531 Feb 08 11:36:10 AM UTC 25 Feb 08 11:36:27 AM UTC 25 5343772739 ps
T861 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1081047225 Feb 08 11:36:15 AM UTC 25 Feb 08 11:36:28 AM UTC 25 4651335832 ps
T862 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.3168119121 Feb 08 11:36:26 AM UTC 25 Feb 08 11:36:29 AM UTC 25 471116908 ps
T863 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2737345264 Feb 08 11:36:26 AM UTC 25 Feb 08 11:36:29 AM UTC 25 365441755 ps
T354 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2574007133 Feb 08 11:36:05 AM UTC 25 Feb 08 11:36:29 AM UTC 25 8483034496 ps
T864 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2667231971 Feb 08 11:36:23 AM UTC 25 Feb 08 11:36:30 AM UTC 25 481064769 ps
T865 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2474271748 Feb 08 11:36:22 AM UTC 25 Feb 08 11:36:30 AM UTC 25 496202924 ps
T866 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2027624238 Feb 08 11:36:28 AM UTC 25 Feb 08 11:36:31 AM UTC 25 625352562 ps
T867 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3554900972 Feb 08 11:36:28 AM UTC 25 Feb 08 11:36:32 AM UTC 25 3047036276 ps
T868 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3627518440 Feb 08 11:36:29 AM UTC 25 Feb 08 11:36:32 AM UTC 25 412910153 ps
T355 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1969746654 Feb 08 11:36:22 AM UTC 25 Feb 08 11:36:33 AM UTC 25 8629548303 ps
T869 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3035110007 Feb 08 11:36:28 AM UTC 25 Feb 08 11:36:33 AM UTC 25 505643982 ps
T870 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.18675848 Feb 08 11:36:31 AM UTC 25 Feb 08 11:36:34 AM UTC 25 577723248 ps
T871 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.669231316 Feb 08 11:36:29 AM UTC 25 Feb 08 11:36:34 AM UTC 25 365759159 ps
T872 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3403418451 Feb 08 11:36:24 AM UTC 25 Feb 08 11:36:34 AM UTC 25 8239535724 ps
T873 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1540652474 Feb 08 11:36:29 AM UTC 25 Feb 08 11:36:34 AM UTC 25 2278703331 ps
T874 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.931984338 Feb 08 11:36:30 AM UTC 25 Feb 08 11:36:35 AM UTC 25 546640601 ps
T875 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1001527516 Feb 08 11:36:30 AM UTC 25 Feb 08 11:36:35 AM UTC 25 542945811 ps
T876 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2810192473 Feb 08 11:36:19 AM UTC 25 Feb 08 11:36:35 AM UTC 25 4380595290 ps
T121 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3605611343 Feb 08 11:36:31 AM UTC 25 Feb 08 11:36:35 AM UTC 25 471390426 ps
T877 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2960849933 Feb 08 11:36:33 AM UTC 25 Feb 08 11:36:37 AM UTC 25 636811389 ps
T356 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1095551680 Feb 08 11:36:28 AM UTC 25 Feb 08 11:36:38 AM UTC 25 4498125338 ps
T878 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1352717315 Feb 08 11:36:33 AM UTC 25 Feb 08 11:36:38 AM UTC 25 713224176 ps
T879 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3878851117 Feb 08 11:36:43 AM UTC 25 Feb 08 11:36:46 AM UTC 25 484744978 ps
T880 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2212860686 Feb 08 11:36:34 AM UTC 25 Feb 08 11:36:38 AM UTC 25 422225155 ps
T881 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4039079707 Feb 08 11:36:32 AM UTC 25 Feb 08 11:36:38 AM UTC 25 2932890283 ps
T882 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1413694725 Feb 08 11:36:36 AM UTC 25 Feb 08 11:36:39 AM UTC 25 411843177 ps
T883 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2486206493 Feb 08 11:36:36 AM UTC 25 Feb 08 11:36:39 AM UTC 25 466984498 ps
T884 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3530463052 Feb 08 11:36:30 AM UTC 25 Feb 08 11:36:39 AM UTC 25 4139595686 ps
T885 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2922827817 Feb 08 11:36:37 AM UTC 25 Feb 08 11:36:40 AM UTC 25 501084438 ps
T886 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2586106170 Feb 08 11:36:37 AM UTC 25 Feb 08 11:36:40 AM UTC 25 518697279 ps
T887 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4150041648 Feb 08 11:36:35 AM UTC 25 Feb 08 11:36:40 AM UTC 25 339284292 ps
T888 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3606566646 Feb 08 11:36:23 AM UTC 25 Feb 08 11:36:40 AM UTC 25 2273351719 ps
T889 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.433079720 Feb 08 11:36:35 AM UTC 25 Feb 08 11:36:40 AM UTC 25 2933202605 ps
T890 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2706714730 Feb 08 11:36:36 AM UTC 25 Feb 08 11:36:41 AM UTC 25 536721902 ps
T891 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.36906834 Feb 08 11:36:38 AM UTC 25 Feb 08 11:36:41 AM UTC 25 373944576 ps
T892 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2742944089 Feb 08 11:36:36 AM UTC 25 Feb 08 11:36:41 AM UTC 25 518354247 ps
T893 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.572947664 Feb 08 11:36:38 AM UTC 25 Feb 08 11:36:41 AM UTC 25 305000262 ps
T894 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.320626456 Feb 08 11:35:34 AM UTC 25 Feb 08 11:36:42 AM UTC 25 26022268602 ps
T895 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2664084664 Feb 08 11:36:39 AM UTC 25 Feb 08 11:36:42 AM UTC 25 534373128 ps
T896 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.580027783 Feb 08 11:36:39 AM UTC 25 Feb 08 11:36:43 AM UTC 25 362956798 ps
T897 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.3409328122 Feb 08 11:36:39 AM UTC 25 Feb 08 11:36:43 AM UTC 25 321778966 ps
T898 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2981276526 Feb 08 11:36:39 AM UTC 25 Feb 08 11:36:43 AM UTC 25 359529446 ps
T899 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.452698582 Feb 08 11:36:40 AM UTC 25 Feb 08 11:36:43 AM UTC 25 366116192 ps
T900 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1256609466 Feb 08 11:36:40 AM UTC 25 Feb 08 11:36:43 AM UTC 25 456363740 ps
T901 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4214032602 Feb 08 11:36:40 AM UTC 25 Feb 08 11:36:43 AM UTC 25 434282797 ps
T902 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1942472968 Feb 08 11:36:40 AM UTC 25 Feb 08 11:36:44 AM UTC 25 396760303 ps
T903 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.1129304650 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:44 AM UTC 25 485145188 ps
T904 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2918053348 Feb 08 11:36:40 AM UTC 25 Feb 08 11:36:44 AM UTC 25 507961415 ps
T905 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2552315345 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:44 AM UTC 25 363944461 ps
T906 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3162069404 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:45 AM UTC 25 476975694 ps
T907 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.3515395580 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:45 AM UTC 25 282225342 ps
T908 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.299180612 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:45 AM UTC 25 404733003 ps
T909 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3663143084 Feb 08 11:36:41 AM UTC 25 Feb 08 11:36:46 AM UTC 25 465752750 ps
T910 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.39941537 Feb 08 11:36:43 AM UTC 25 Feb 08 11:36:46 AM UTC 25 482260065 ps
T911 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2409097174 Feb 08 11:36:43 AM UTC 25 Feb 08 11:36:46 AM UTC 25 407818226 ps
T912 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1122887559 Feb 08 11:36:43 AM UTC 25 Feb 08 11:36:46 AM UTC 25 538740690 ps
T913 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1087909474 Feb 08 11:36:43 AM UTC 25 Feb 08 11:36:46 AM UTC 25 432466863 ps
T914 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.20877436 Feb 08 11:36:44 AM UTC 25 Feb 08 11:36:47 AM UTC 25 353980653 ps
T915 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1963241908 Feb 08 11:36:44 AM UTC 25 Feb 08 11:36:47 AM UTC 25 444825944 ps
T916 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.2547885766 Feb 08 11:36:44 AM UTC 25 Feb 08 11:36:48 AM UTC 25 315899255 ps
T917 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.685271432 Feb 08 11:36:34 AM UTC 25 Feb 08 11:36:52 AM UTC 25 4466147752 ps
T918 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2974247515 Feb 08 11:35:39 AM UTC 25 Feb 08 11:38:04 AM UTC 25 37885433280 ps

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.4206121879
Short name T6
Test name
Test status
Simulation time 28966160650 ps
CPU time 15.82 seconds
Started Feb 08 10:20:01 AM UTC 25
Finished Feb 08 10:20:19 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206121879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4206121879
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.967905407
Short name T12
Test name
Test status
Simulation time 506520519689 ps
CPU time 120.59 seconds
Started Feb 08 10:19:59 AM UTC 25
Finished Feb 08 10:22:02 AM UTC 25
Peak memory 211784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967905407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.967905407
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1770326234
Short name T18
Test name
Test status
Simulation time 403110430197 ps
CPU time 186.91 seconds
Started Feb 08 10:20:30 AM UTC 25
Finished Feb 08 10:23:41 AM UTC 25
Peak memory 222228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1770326234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_al
l_with_rand_reset.1770326234
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3478389074
Short name T7
Test name
Test status
Simulation time 6048983127 ps
CPU time 7.94 seconds
Started Feb 08 10:20:16 AM UTC 25
Finished Feb 08 10:20:25 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478389074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3478389074
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.261900392
Short name T161
Test name
Test status
Simulation time 528457352244 ps
CPU time 259.78 seconds
Started Feb 08 10:34:25 AM UTC 25
Finished Feb 08 10:38:48 AM UTC 25
Peak memory 228340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=261900392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_al
l_with_rand_reset.261900392
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.640173734
Short name T29
Test name
Test status
Simulation time 387731069884 ps
CPU time 266.81 seconds
Started Feb 08 10:22:03 AM UTC 25
Finished Feb 08 10:26:34 AM UTC 25
Peak memory 221796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=640173734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all
_with_rand_reset.640173734
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.1756561491
Short name T247
Test name
Test status
Simulation time 528346422014 ps
CPU time 443.88 seconds
Started Feb 08 10:43:15 AM UTC 25
Finished Feb 08 10:50:45 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756561491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1756561491
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3013445242
Short name T134
Test name
Test status
Simulation time 495804097339 ps
CPU time 488.99 seconds
Started Feb 08 10:21:05 AM UTC 25
Finished Feb 08 10:29:21 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013445242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3013445242
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1972229213
Short name T64
Test name
Test status
Simulation time 1559102842198 ps
CPU time 1659.19 seconds
Started Feb 08 10:26:35 AM UTC 25
Finished Feb 08 10:54:32 AM UTC 25
Peak memory 225416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972229213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.1972229213
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.145727322
Short name T168
Test name
Test status
Simulation time 527080064850 ps
CPU time 274.4 seconds
Started Feb 08 10:35:50 AM UTC 25
Finished Feb 08 10:40:28 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145727322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.145727322
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.368408014
Short name T75
Test name
Test status
Simulation time 521794005 ps
CPU time 5.86 seconds
Started Feb 08 11:34:30 AM UTC 25
Finished Feb 08 11:34:38 AM UTC 25
Peak memory 227864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368408014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.368408014
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.3672547812
Short name T163
Test name
Test status
Simulation time 538098131689 ps
CPU time 1497.25 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:45:05 AM UTC 25
Peak memory 212632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672547812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3672547812
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.2822548319
Short name T22
Test name
Test status
Simulation time 8202111953 ps
CPU time 26.55 seconds
Started Feb 08 10:19:53 AM UTC 25
Finished Feb 08 10:20:22 AM UTC 25
Peak memory 243960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822548319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2822548319
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1727717077
Short name T253
Test name
Test status
Simulation time 542935025311 ps
CPU time 372.21 seconds
Started Feb 08 10:40:43 AM UTC 25
Finished Feb 08 10:47:00 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727717077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.1727717077
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1695062879
Short name T165
Test name
Test status
Simulation time 496847577047 ps
CPU time 201.57 seconds
Started Feb 08 10:36:21 AM UTC 25
Finished Feb 08 10:39:47 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695062879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1695062879
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1665221808
Short name T16
Test name
Test status
Simulation time 204321792292 ps
CPU time 182.46 seconds
Started Feb 08 10:20:23 AM UTC 25
Finished Feb 08 10:23:29 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665221808 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.1665221808
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2603931543
Short name T239
Test name
Test status
Simulation time 590502239974 ps
CPU time 390.88 seconds
Started Feb 08 10:31:26 AM UTC 25
Finished Feb 08 10:38:02 AM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603931543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.2603931543
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.196769148
Short name T299
Test name
Test status
Simulation time 534987090305 ps
CPU time 1197.92 seconds
Started Feb 08 10:35:58 AM UTC 25
Finished Feb 08 10:56:08 AM UTC 25
Peak memory 212864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196769148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.196769148
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2082107938
Short name T52
Test name
Test status
Simulation time 134319928142 ps
CPU time 105.3 seconds
Started Feb 08 10:30:45 AM UTC 25
Finished Feb 08 10:32:33 AM UTC 25
Peak memory 221984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2082107938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_al
l_with_rand_reset.2082107938
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1927381499
Short name T145
Test name
Test status
Simulation time 481669519669 ps
CPU time 430.1 seconds
Started Feb 08 10:33:49 AM UTC 25
Finished Feb 08 10:41:05 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927381499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1927381499
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3932108857
Short name T69
Test name
Test status
Simulation time 35224152187 ps
CPU time 42.68 seconds
Started Feb 08 11:34:47 AM UTC 25
Finished Feb 08 11:35:32 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932108857 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.3932108857
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3071105230
Short name T49
Test name
Test status
Simulation time 323675276866 ps
CPU time 362.79 seconds
Started Feb 08 10:20:02 AM UTC 25
Finished Feb 08 10:26:10 AM UTC 25
Peak memory 221764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3071105230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_al
l_with_rand_reset.3071105230
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3190497788
Short name T131
Test name
Test status
Simulation time 307519272015 ps
CPU time 81.35 seconds
Started Feb 08 10:36:09 AM UTC 25
Finished Feb 08 10:37:32 AM UTC 25
Peak memory 221776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3190497788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_a
ll_with_rand_reset.3190497788
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2734349725
Short name T30
Test name
Test status
Simulation time 157019280458 ps
CPU time 213.14 seconds
Started Feb 08 10:23:32 AM UTC 25
Finished Feb 08 10:27:09 AM UTC 25
Peak memory 228164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2734349725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_al
l_with_rand_reset.2734349725
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2015397987
Short name T213
Test name
Test status
Simulation time 1353912767974 ps
CPU time 944.86 seconds
Started Feb 08 10:55:33 AM UTC 25
Finished Feb 08 11:11:27 AM UTC 25
Peak memory 223380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2015397987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_a
ll_with_rand_reset.2015397987
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2148766634
Short name T269
Test name
Test status
Simulation time 487002011076 ps
CPU time 857.88 seconds
Started Feb 08 10:23:49 AM UTC 25
Finished Feb 08 10:38:17 AM UTC 25
Peak memory 212676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148766634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2148766634
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2867659249
Short name T272
Test name
Test status
Simulation time 537674719174 ps
CPU time 716.82 seconds
Started Feb 08 11:07:52 AM UTC 25
Finished Feb 08 11:19:56 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867659249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.2867659249
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1142580728
Short name T259
Test name
Test status
Simulation time 768544103747 ps
CPU time 409.79 seconds
Started Feb 08 10:45:37 AM UTC 25
Finished Feb 08 10:52:32 AM UTC 25
Peak memory 222028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1142580728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_a
ll_with_rand_reset.1142580728
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.1192100474
Short name T315
Test name
Test status
Simulation time 561661739085 ps
CPU time 1539.81 seconds
Started Feb 08 11:03:29 AM UTC 25
Finished Feb 08 11:29:25 AM UTC 25
Peak memory 212924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192100474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.1192100474
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3831093125
Short name T305
Test name
Test status
Simulation time 347230047001 ps
CPU time 138.82 seconds
Started Feb 08 11:22:13 AM UTC 25
Finished Feb 08 11:24:35 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831093125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.3831093125
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3186017340
Short name T1
Test name
Test status
Simulation time 523070790 ps
CPU time 3.5 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:20:00 AM UTC 25
Peak memory 211404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186017340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3186017340
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2059649818
Short name T278
Test name
Test status
Simulation time 538412571637 ps
CPU time 1428.45 seconds
Started Feb 08 10:36:43 AM UTC 25
Finished Feb 08 11:00:46 AM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059649818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.2059649818
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1836424974
Short name T78
Test name
Test status
Simulation time 7823890894 ps
CPU time 20.93 seconds
Started Feb 08 11:35:38 AM UTC 25
Finished Feb 08 11:36:01 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836424974 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.1836424974
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.410555339
Short name T50
Test name
Test status
Simulation time 114676395509 ps
CPU time 126.8 seconds
Started Feb 08 10:24:55 AM UTC 25
Finished Feb 08 10:27:04 AM UTC 25
Peak memory 211856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=410555339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all
_with_rand_reset.410555339
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2798005814
Short name T17
Test name
Test status
Simulation time 332764438321 ps
CPU time 216.75 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:23:32 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798005814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.2798005814
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3818419144
Short name T89
Test name
Test status
Simulation time 549768503329 ps
CPU time 388.73 seconds
Started Feb 08 10:47:00 AM UTC 25
Finished Feb 08 10:53:34 AM UTC 25
Peak memory 228252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3818419144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_a
ll_with_rand_reset.3818419144
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1810014803
Short name T258
Test name
Test status
Simulation time 494202273195 ps
CPU time 400.28 seconds
Started Feb 08 10:45:55 AM UTC 25
Finished Feb 08 10:52:40 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810014803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1810014803
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1152799640
Short name T60
Test name
Test status
Simulation time 94815510914 ps
CPU time 517.76 seconds
Started Feb 08 10:22:00 AM UTC 25
Finished Feb 08 10:30:44 AM UTC 25
Peak memory 212028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152799640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1152799640
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.772861343
Short name T177
Test name
Test status
Simulation time 423499417796 ps
CPU time 247.59 seconds
Started Feb 08 11:06:29 AM UTC 25
Finished Feb 08 11:10:40 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772861343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.772861343
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4275962744
Short name T111
Test name
Test status
Simulation time 551323309 ps
CPU time 3.39 seconds
Started Feb 08 11:34:51 AM UTC 25
Finished Feb 08 11:34:56 AM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275962744 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.4275962744
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.887455096
Short name T296
Test name
Test status
Simulation time 387514288344 ps
CPU time 897.9 seconds
Started Feb 08 10:37:03 AM UTC 25
Finished Feb 08 10:52:12 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887455096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.887455096
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.263350239
Short name T221
Test name
Test status
Simulation time 374839875214 ps
CPU time 530.53 seconds
Started Feb 08 11:27:49 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 222108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=263350239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_al
l_with_rand_reset.263350239
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1838674090
Short name T139
Test name
Test status
Simulation time 177162227840 ps
CPU time 222.16 seconds
Started Feb 08 10:31:21 AM UTC 25
Finished Feb 08 10:35:07 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838674090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.1838674090
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3865377586
Short name T297
Test name
Test status
Simulation time 512665966109 ps
CPU time 802.68 seconds
Started Feb 08 10:54:46 AM UTC 25
Finished Feb 08 11:08:18 AM UTC 25
Peak memory 211716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865377586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.3865377586
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.4265908206
Short name T338
Test name
Test status
Simulation time 170197570719 ps
CPU time 493.48 seconds
Started Feb 08 11:20:54 AM UTC 25
Finished Feb 08 11:29:14 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265908206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4265908206
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1926895884
Short name T200
Test name
Test status
Simulation time 507884633248 ps
CPU time 270.57 seconds
Started Feb 08 11:23:32 AM UTC 25
Finished Feb 08 11:28:07 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926895884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.1926895884
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2212314254
Short name T219
Test name
Test status
Simulation time 504169154921 ps
CPU time 1454.06 seconds
Started Feb 08 10:38:06 AM UTC 25
Finished Feb 08 11:02:35 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212314254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2212314254
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2693208085
Short name T252
Test name
Test status
Simulation time 558533124920 ps
CPU time 1762.7 seconds
Started Feb 08 11:32:02 AM UTC 25
Finished Feb 08 12:01:43 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693208085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2693208085
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3856593751
Short name T122
Test name
Test status
Simulation time 362321756 ps
CPU time 2.87 seconds
Started Feb 08 11:34:46 AM UTC 25
Finished Feb 08 11:34:51 AM UTC 25
Peak memory 211108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856593751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3856593751
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.655292033
Short name T189
Test name
Test status
Simulation time 18055766664 ps
CPU time 69.49 seconds
Started Feb 08 10:39:31 AM UTC 25
Finished Feb 08 10:40:42 AM UTC 25
Peak memory 221700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=655292033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_al
l_with_rand_reset.655292033
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.293284387
Short name T287
Test name
Test status
Simulation time 355435644390 ps
CPU time 454.6 seconds
Started Feb 08 10:58:40 AM UTC 25
Finished Feb 08 11:06:21 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293284387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.293284387
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3314882274
Short name T336
Test name
Test status
Simulation time 327658458052 ps
CPU time 802.62 seconds
Started Feb 08 11:13:32 AM UTC 25
Finished Feb 08 11:27:03 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314882274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.3314882274
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4028331960
Short name T321
Test name
Test status
Simulation time 194525996102 ps
CPU time 186.57 seconds
Started Feb 08 11:10:41 AM UTC 25
Finished Feb 08 11:13:51 AM UTC 25
Peak memory 222104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4028331960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_a
ll_with_rand_reset.4028331960
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3941541152
Short name T319
Test name
Test status
Simulation time 62879273355 ps
CPU time 119.41 seconds
Started Feb 08 11:32:21 AM UTC 25
Finished Feb 08 11:34:23 AM UTC 25
Peak memory 228248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3941541152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_a
ll_with_rand_reset.3941541152
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1195312232
Short name T245
Test name
Test status
Simulation time 525169991428 ps
CPU time 1497.37 seconds
Started Feb 08 10:25:46 AM UTC 25
Finished Feb 08 10:51:00 AM UTC 25
Peak memory 212596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195312232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.1195312232
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1219600265
Short name T187
Test name
Test status
Simulation time 332074938113 ps
CPU time 316.33 seconds
Started Feb 08 10:34:47 AM UTC 25
Finished Feb 08 10:40:08 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219600265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.1219600265
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.2784885436
Short name T320
Test name
Test status
Simulation time 336686228106 ps
CPU time 328.91 seconds
Started Feb 08 11:24:42 AM UTC 25
Finished Feb 08 11:30:16 AM UTC 25
Peak memory 211592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784885436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2784885436
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.935999169
Short name T302
Test name
Test status
Simulation time 533762336380 ps
CPU time 871.96 seconds
Started Feb 08 11:33:44 AM UTC 25
Finished Feb 08 11:48:26 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935999169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.935999169
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3578472922
Short name T206
Test name
Test status
Simulation time 66700664583 ps
CPU time 344.4 seconds
Started Feb 08 10:26:28 AM UTC 25
Finished Feb 08 10:32:17 AM UTC 25
Peak memory 211400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578472922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3578472922
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.375016844
Short name T79
Test name
Test status
Simulation time 533530222 ps
CPU time 3.5 seconds
Started Feb 08 11:35:00 AM UTC 25
Finished Feb 08 11:35:05 AM UTC 25
Peak memory 221616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375016844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.375016844
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.523515669
Short name T20
Test name
Test status
Simulation time 178690123611 ps
CPU time 228.77 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:23:44 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523515669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.523515669
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1240590086
Short name T156
Test name
Test status
Simulation time 330924632480 ps
CPU time 261.37 seconds
Started Feb 08 10:31:43 AM UTC 25
Finished Feb 08 10:36:08 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240590086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1240590086
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1054072182
Short name T263
Test name
Test status
Simulation time 507228264691 ps
CPU time 483.74 seconds
Started Feb 08 10:50:29 AM UTC 25
Finished Feb 08 10:58:39 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054072182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.1054072182
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1296488023
Short name T170
Test name
Test status
Simulation time 513095555352 ps
CPU time 1623.99 seconds
Started Feb 08 10:20:55 AM UTC 25
Finished Feb 08 10:48:17 AM UTC 25
Peak memory 212684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296488023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.1296488023
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3634941669
Short name T233
Test name
Test status
Simulation time 159178823311 ps
CPU time 542.05 seconds
Started Feb 08 11:06:22 AM UTC 25
Finished Feb 08 11:15:31 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634941669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3634941669
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.231363993
Short name T142
Test name
Test status
Simulation time 497716387662 ps
CPU time 385.74 seconds
Started Feb 08 10:25:27 AM UTC 25
Finished Feb 08 10:31:58 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231363993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.231363993
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3181106977
Short name T72
Test name
Test status
Simulation time 4778332416 ps
CPU time 12.2 seconds
Started Feb 08 11:34:33 AM UTC 25
Finished Feb 08 11:34:47 AM UTC 25
Peak memory 211460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181106977 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.3181106977
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1202373769
Short name T102
Test name
Test status
Simulation time 69946061028 ps
CPU time 654.45 seconds
Started Feb 08 10:19:52 AM UTC 25
Finished Feb 08 10:30:55 AM UTC 25
Peak memory 213200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202373769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1202373769
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2870378823
Short name T248
Test name
Test status
Simulation time 329388167736 ps
CPU time 1089.4 seconds
Started Feb 08 10:34:01 AM UTC 25
Finished Feb 08 10:52:22 AM UTC 25
Peak memory 212608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870378823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2870378823
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2317651522
Short name T215
Test name
Test status
Simulation time 253771612548 ps
CPU time 1310.62 seconds
Started Feb 08 10:37:28 AM UTC 25
Finished Feb 08 10:59:33 AM UTC 25
Peak memory 222984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317651522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.2317651522
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.3633420832
Short name T329
Test name
Test status
Simulation time 345061481013 ps
CPU time 345.62 seconds
Started Feb 08 11:13:38 AM UTC 25
Finished Feb 08 11:19:28 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633420832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3633420832
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.673710532
Short name T280
Test name
Test status
Simulation time 323706576308 ps
CPU time 266.31 seconds
Started Feb 08 11:13:08 AM UTC 25
Finished Feb 08 11:17:39 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673710532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.673710532
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.66694086
Short name T204
Test name
Test status
Simulation time 101470893921 ps
CPU time 351.54 seconds
Started Feb 08 11:16:12 AM UTC 25
Finished Feb 08 11:22:08 AM UTC 25
Peak memory 222236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=66694086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
_with_rand_reset.66694086
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.138917955
Short name T332
Test name
Test status
Simulation time 371099538271 ps
CPU time 241.03 seconds
Started Feb 08 11:23:33 AM UTC 25
Finished Feb 08 11:27:38 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138917955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.138917955
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1907649773
Short name T311
Test name
Test status
Simulation time 45430525658 ps
CPU time 183.3 seconds
Started Feb 08 11:31:00 AM UTC 25
Finished Feb 08 11:34:06 AM UTC 25
Peak memory 222240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1907649773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_a
ll_with_rand_reset.1907649773
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1969746654
Short name T355
Test name
Test status
Simulation time 8629548303 ps
CPU time 8.66 seconds
Started Feb 08 11:36:22 AM UTC 25
Finished Feb 08 11:36:33 AM UTC 25
Peak memory 211456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969746654 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.1969746654
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3682644705
Short name T9
Test name
Test status
Simulation time 170004431043 ps
CPU time 57.81 seconds
Started Feb 08 10:19:50 AM UTC 25
Finished Feb 08 10:20:50 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682644705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3682644705
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3007132781
Short name T208
Test name
Test status
Simulation time 95237116076 ps
CPU time 724.2 seconds
Started Feb 08 10:32:05 AM UTC 25
Finished Feb 08 10:44:18 AM UTC 25
Peak memory 211972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007132781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3007132781
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.572564731
Short name T357
Test name
Test status
Simulation time 123709504416 ps
CPU time 710.65 seconds
Started Feb 08 10:34:19 AM UTC 25
Finished Feb 08 10:46:18 AM UTC 25
Peak memory 211980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572564731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.572564731
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.1797370946
Short name T197
Test name
Test status
Simulation time 529959121624 ps
CPU time 557.88 seconds
Started Feb 08 10:46:29 AM UTC 25
Finished Feb 08 10:55:54 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797370946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1797370946
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.846664164
Short name T231
Test name
Test status
Simulation time 192245957748 ps
CPU time 549.1 seconds
Started Feb 08 10:57:03 AM UTC 25
Finished Feb 08 11:06:19 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846664164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.846664164
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.567491568
Short name T33
Test name
Test status
Simulation time 114892347600 ps
CPU time 192.76 seconds
Started Feb 08 10:57:56 AM UTC 25
Finished Feb 08 11:01:12 AM UTC 25
Peak memory 222032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=567491568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_al
l_with_rand_reset.567491568
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3803408614
Short name T361
Test name
Test status
Simulation time 104197674792 ps
CPU time 459.8 seconds
Started Feb 08 11:16:09 AM UTC 25
Finished Feb 08 11:23:54 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803408614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3803408614
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.420841345
Short name T211
Test name
Test status
Simulation time 498092778769 ps
CPU time 1031.6 seconds
Started Feb 08 11:17:41 AM UTC 25
Finished Feb 08 11:35:04 AM UTC 25
Peak memory 213004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420841345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.420841345
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.4270735091
Short name T169
Test name
Test status
Simulation time 545888078903 ps
CPU time 1146.49 seconds
Started Feb 08 10:23:08 AM UTC 25
Finished Feb 08 10:42:27 AM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270735091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.4270735091
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3394218250
Short name T339
Test name
Test status
Simulation time 215195594759 ps
CPU time 139.92 seconds
Started Feb 08 11:27:04 AM UTC 25
Finished Feb 08 11:29:27 AM UTC 25
Peak memory 211508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394218250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.3394218250
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3408227608
Short name T110
Test name
Test status
Simulation time 1163181457 ps
CPU time 2.55 seconds
Started Feb 08 11:34:41 AM UTC 25
Finished Feb 08 11:34:45 AM UTC 25
Peak memory 211116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408227608 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.3408227608
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1034985249
Short name T76
Test name
Test status
Simulation time 449733490 ps
CPU time 1.91 seconds
Started Feb 08 11:34:59 AM UTC 25
Finished Feb 08 11:35:03 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10349
85249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_res
et.1034985249
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1503560207
Short name T801
Test name
Test status
Simulation time 438861390 ps
CPU time 1.4 seconds
Started Feb 08 11:34:38 AM UTC 25
Finished Feb 08 11:34:41 AM UTC 25
Peak memory 210140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503560207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1503560207
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3083870203
Short name T67
Test name
Test status
Simulation time 2197222571 ps
CPU time 5.82 seconds
Started Feb 08 11:34:57 AM UTC 25
Finished Feb 08 11:35:05 AM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083870203 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.3083870203
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2117146713
Short name T129
Test name
Test status
Simulation time 1287219865 ps
CPU time 3.93 seconds
Started Feb 08 11:35:09 AM UTC 25
Finished Feb 08 11:35:14 AM UTC 25
Peak memory 211404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117146713 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.2117146713
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2884035965
Short name T821
Test name
Test status
Simulation time 26074985275 ps
CPU time 54.98 seconds
Started Feb 08 11:35:07 AM UTC 25
Finished Feb 08 11:36:04 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884035965 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.2884035965
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2697747577
Short name T128
Test name
Test status
Simulation time 742965953 ps
CPU time 4.4 seconds
Started Feb 08 11:35:06 AM UTC 25
Finished Feb 08 11:35:11 AM UTC 25
Peak memory 211192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697747577 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.2697747577
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.932984534
Short name T83
Test name
Test status
Simulation time 565961230 ps
CPU time 1.39 seconds
Started Feb 08 11:35:12 AM UTC 25
Finished Feb 08 11:35:15 AM UTC 25
Peak memory 210016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93298
4534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.932984534
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1158813466
Short name T127
Test name
Test status
Simulation time 504858431 ps
CPU time 2.14 seconds
Started Feb 08 11:35:06 AM UTC 25
Finished Feb 08 11:35:09 AM UTC 25
Peak memory 211176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158813466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1158813466
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1454296406
Short name T802
Test name
Test status
Simulation time 492975515 ps
CPU time 1.52 seconds
Started Feb 08 11:35:05 AM UTC 25
Finished Feb 08 11:35:08 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454296406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1454296406
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3843151505
Short name T68
Test name
Test status
Simulation time 1935989514 ps
CPU time 9.28 seconds
Started Feb 08 11:35:10 AM UTC 25
Finished Feb 08 11:35:21 AM UTC 25
Peak memory 211184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843151505 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.3843151505
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.574925675
Short name T73
Test name
Test status
Simulation time 4469167018 ps
CPU time 14.29 seconds
Started Feb 08 11:35:04 AM UTC 25
Finished Feb 08 11:35:19 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574925675 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.574925675
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3508489314
Short name T831
Test name
Test status
Simulation time 503893205 ps
CPU time 3.72 seconds
Started Feb 08 11:36:06 AM UTC 25
Finished Feb 08 11:36:11 AM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35084
89314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_re
set.3508489314
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3015989235
Short name T119
Test name
Test status
Simulation time 352196442 ps
CPU time 2.76 seconds
Started Feb 08 11:36:06 AM UTC 25
Finished Feb 08 11:36:10 AM UTC 25
Peak memory 211108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015989235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3015989235
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3601896866
Short name T827
Test name
Test status
Simulation time 298530501 ps
CPU time 2 seconds
Started Feb 08 11:36:05 AM UTC 25
Finished Feb 08 11:36:08 AM UTC 25
Peak memory 209980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601896866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3601896866
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3087574642
Short name T834
Test name
Test status
Simulation time 2651125006 ps
CPU time 5.28 seconds
Started Feb 08 11:36:06 AM UTC 25
Finished Feb 08 11:36:13 AM UTC 25
Peak memory 211248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087574642 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.3087574642
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3534582882
Short name T828
Test name
Test status
Simulation time 594152038 ps
CPU time 4.72 seconds
Started Feb 08 11:36:03 AM UTC 25
Finished Feb 08 11:36:09 AM UTC 25
Peak memory 227476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534582882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3534582882
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2574007133
Short name T354
Test name
Test status
Simulation time 8483034496 ps
CPU time 22.78 seconds
Started Feb 08 11:36:05 AM UTC 25
Finished Feb 08 11:36:29 AM UTC 25
Peak memory 211360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574007133 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.2574007133
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3275732306
Short name T838
Test name
Test status
Simulation time 417194799 ps
CPU time 3.14 seconds
Started Feb 08 11:36:11 AM UTC 25
Finished Feb 08 11:36:16 AM UTC 25
Peak memory 211224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32757
32306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_re
set.3275732306
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.872626820
Short name T832
Test name
Test status
Simulation time 380539117 ps
CPU time 2 seconds
Started Feb 08 11:36:09 AM UTC 25
Finished Feb 08 11:36:13 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872626820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_t
est +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.872626820
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3801586755
Short name T830
Test name
Test status
Simulation time 498184751 ps
CPU time 1.57 seconds
Started Feb 08 11:36:07 AM UTC 25
Finished Feb 08 11:36:10 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801586755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3801586755
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.474326531
Short name T860
Test name
Test status
Simulation time 5343772739 ps
CPU time 15.66 seconds
Started Feb 08 11:36:10 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 211468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474326531 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.474326531
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4027905157
Short name T835
Test name
Test status
Simulation time 396244022 ps
CPU time 4.92 seconds
Started Feb 08 11:36:07 AM UTC 25
Finished Feb 08 11:36:14 AM UTC 25
Peak memory 211392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027905157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4027905157
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4182165928
Short name T833
Test name
Test status
Simulation time 4467504046 ps
CPU time 4.05 seconds
Started Feb 08 11:36:07 AM UTC 25
Finished Feb 08 11:36:13 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182165928 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.4182165928
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2044604949
Short name T839
Test name
Test status
Simulation time 429706528 ps
CPU time 1.25 seconds
Started Feb 08 11:36:13 AM UTC 25
Finished Feb 08 11:36:16 AM UTC 25
Peak memory 209664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20446
04949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_re
set.2044604949
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.859910785
Short name T842
Test name
Test status
Simulation time 369643368 ps
CPU time 2.92 seconds
Started Feb 08 11:36:13 AM UTC 25
Finished Feb 08 11:36:18 AM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859910785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_t
est +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.859910785
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2865217110
Short name T837
Test name
Test status
Simulation time 425609290 ps
CPU time 1.99 seconds
Started Feb 08 11:36:12 AM UTC 25
Finished Feb 08 11:36:16 AM UTC 25
Peak memory 210196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865217110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2865217110
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1284331279
Short name T841
Test name
Test status
Simulation time 4415913730 ps
CPU time 2.78 seconds
Started Feb 08 11:36:13 AM UTC 25
Finished Feb 08 11:36:18 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284331279 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.1284331279
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2108688915
Short name T840
Test name
Test status
Simulation time 447080131 ps
CPU time 4.58 seconds
Started Feb 08 11:36:11 AM UTC 25
Finished Feb 08 11:36:17 AM UTC 25
Peak memory 227508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108688915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2108688915
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3863528822
Short name T845
Test name
Test status
Simulation time 4533464728 ps
CPU time 7.71 seconds
Started Feb 08 11:36:11 AM UTC 25
Finished Feb 08 11:36:21 AM UTC 25
Peak memory 211376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863528822 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.3863528822
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3709328761
Short name T848
Test name
Test status
Simulation time 390198137 ps
CPU time 3.1 seconds
Started Feb 08 11:36:17 AM UTC 25
Finished Feb 08 11:36:21 AM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37093
28761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_re
set.3709328761
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1424992821
Short name T844
Test name
Test status
Simulation time 447278643 ps
CPU time 1.51 seconds
Started Feb 08 11:36:17 AM UTC 25
Finished Feb 08 11:36:20 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424992821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1424992821
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2995173462
Short name T847
Test name
Test status
Simulation time 477854949 ps
CPU time 3.32 seconds
Started Feb 08 11:36:17 AM UTC 25
Finished Feb 08 11:36:21 AM UTC 25
Peak memory 211056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995173462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2995173462
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2278559160
Short name T855
Test name
Test status
Simulation time 2073326191 ps
CPU time 8.38 seconds
Started Feb 08 11:36:17 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278559160 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.2278559160
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1503258050
Short name T843
Test name
Test status
Simulation time 560799721 ps
CPU time 2.64 seconds
Started Feb 08 11:36:15 AM UTC 25
Finished Feb 08 11:36:19 AM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503258050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1503258050
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1081047225
Short name T861
Test name
Test status
Simulation time 4651335832 ps
CPU time 12 seconds
Started Feb 08 11:36:15 AM UTC 25
Finished Feb 08 11:36:28 AM UTC 25
Peak memory 211604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081047225 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.1081047225
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1533409603
Short name T854
Test name
Test status
Simulation time 420576699 ps
CPU time 1.69 seconds
Started Feb 08 11:36:21 AM UTC 25
Finished Feb 08 11:36:25 AM UTC 25
Peak memory 209964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15334
09603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_re
set.1533409603
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1186966455
Short name T853
Test name
Test status
Simulation time 488857863 ps
CPU time 1.73 seconds
Started Feb 08 11:36:20 AM UTC 25
Finished Feb 08 11:36:23 AM UTC 25
Peak memory 209836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186966455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1186966455
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.3917523398
Short name T850
Test name
Test status
Simulation time 338143618 ps
CPU time 1.32 seconds
Started Feb 08 11:36:19 AM UTC 25
Finished Feb 08 11:36:22 AM UTC 25
Peak memory 209580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917523398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3917523398
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2245630822
Short name T859
Test name
Test status
Simulation time 2909683374 ps
CPU time 4.46 seconds
Started Feb 08 11:36:21 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 211244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245630822 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.2245630822
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3289090320
Short name T851
Test name
Test status
Simulation time 394018996 ps
CPU time 3.08 seconds
Started Feb 08 11:36:18 AM UTC 25
Finished Feb 08 11:36:22 AM UTC 25
Peak memory 211432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289090320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3289090320
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2810192473
Short name T876
Test name
Test status
Simulation time 4380595290 ps
CPU time 14.82 seconds
Started Feb 08 11:36:19 AM UTC 25
Finished Feb 08 11:36:35 AM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810192473 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.2810192473
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1022948100
Short name T857
Test name
Test status
Simulation time 454470488 ps
CPU time 1.93 seconds
Started Feb 08 11:36:23 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 209660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10229
48100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_re
set.1022948100
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.424279674
Short name T856
Test name
Test status
Simulation time 348986032 ps
CPU time 2.58 seconds
Started Feb 08 11:36:22 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 211196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424279674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_t
est +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.424279674
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3074599558
Short name T858
Test name
Test status
Simulation time 407607153 ps
CPU time 2.95 seconds
Started Feb 08 11:36:22 AM UTC 25
Finished Feb 08 11:36:27 AM UTC 25
Peak memory 211116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074599558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3074599558
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3606566646
Short name T888
Test name
Test status
Simulation time 2273351719 ps
CPU time 14.58 seconds
Started Feb 08 11:36:23 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 211164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606566646 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.3606566646
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2474271748
Short name T865
Test name
Test status
Simulation time 496202924 ps
CPU time 5.56 seconds
Started Feb 08 11:36:22 AM UTC 25
Finished Feb 08 11:36:30 AM UTC 25
Peak memory 221384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474271748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2474271748
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2027624238
Short name T866
Test name
Test status
Simulation time 625352562 ps
CPU time 1.13 seconds
Started Feb 08 11:36:28 AM UTC 25
Finished Feb 08 11:36:31 AM UTC 25
Peak memory 210024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20276
24238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_re
set.2027624238
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2737345264
Short name T863
Test name
Test status
Simulation time 365441755 ps
CPU time 1.91 seconds
Started Feb 08 11:36:26 AM UTC 25
Finished Feb 08 11:36:29 AM UTC 25
Peak memory 209752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737345264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2737345264
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.3168119121
Short name T862
Test name
Test status
Simulation time 471116908 ps
CPU time 1.68 seconds
Started Feb 08 11:36:26 AM UTC 25
Finished Feb 08 11:36:29 AM UTC 25
Peak memory 209536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168119121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3168119121
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3554900972
Short name T867
Test name
Test status
Simulation time 3047036276 ps
CPU time 2.29 seconds
Started Feb 08 11:36:28 AM UTC 25
Finished Feb 08 11:36:32 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554900972 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.3554900972
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2667231971
Short name T864
Test name
Test status
Simulation time 481064769 ps
CPU time 4.3 seconds
Started Feb 08 11:36:23 AM UTC 25
Finished Feb 08 11:36:30 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667231971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2667231971
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3403418451
Short name T872
Test name
Test status
Simulation time 8239535724 ps
CPU time 8.21 seconds
Started Feb 08 11:36:24 AM UTC 25
Finished Feb 08 11:36:34 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403418451 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.3403418451
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.931984338
Short name T874
Test name
Test status
Simulation time 546640601 ps
CPU time 2.42 seconds
Started Feb 08 11:36:30 AM UTC 25
Finished Feb 08 11:36:35 AM UTC 25
Peak memory 211272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93198
4338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.931984338
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3627518440
Short name T868
Test name
Test status
Simulation time 412910153 ps
CPU time 1.25 seconds
Started Feb 08 11:36:29 AM UTC 25
Finished Feb 08 11:36:32 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627518440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3627518440
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.669231316
Short name T871
Test name
Test status
Simulation time 365759159 ps
CPU time 2.74 seconds
Started Feb 08 11:36:29 AM UTC 25
Finished Feb 08 11:36:34 AM UTC 25
Peak memory 211192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669231316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.669231316
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1540652474
Short name T873
Test name
Test status
Simulation time 2278703331 ps
CPU time 3.07 seconds
Started Feb 08 11:36:29 AM UTC 25
Finished Feb 08 11:36:34 AM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540652474 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.1540652474
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3035110007
Short name T869
Test name
Test status
Simulation time 505643982 ps
CPU time 3.42 seconds
Started Feb 08 11:36:28 AM UTC 25
Finished Feb 08 11:36:33 AM UTC 25
Peak memory 227592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035110007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3035110007
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1095551680
Short name T356
Test name
Test status
Simulation time 4498125338 ps
CPU time 7.85 seconds
Started Feb 08 11:36:28 AM UTC 25
Finished Feb 08 11:36:38 AM UTC 25
Peak memory 211408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095551680 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.1095551680
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2960849933
Short name T877
Test name
Test status
Simulation time 636811389 ps
CPU time 1.76 seconds
Started Feb 08 11:36:33 AM UTC 25
Finished Feb 08 11:36:37 AM UTC 25
Peak memory 209980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29608
49933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_re
set.2960849933
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3605611343
Short name T121
Test name
Test status
Simulation time 471390426 ps
CPU time 2.49 seconds
Started Feb 08 11:36:31 AM UTC 25
Finished Feb 08 11:36:35 AM UTC 25
Peak memory 211256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605611343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3605611343
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.18675848
Short name T870
Test name
Test status
Simulation time 577723248 ps
CPU time 1.05 seconds
Started Feb 08 11:36:31 AM UTC 25
Finished Feb 08 11:36:34 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18675848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.18675848
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4039079707
Short name T881
Test name
Test status
Simulation time 2932890283 ps
CPU time 4.26 seconds
Started Feb 08 11:36:32 AM UTC 25
Finished Feb 08 11:36:38 AM UTC 25
Peak memory 211184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039079707 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.4039079707
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1001527516
Short name T875
Test name
Test status
Simulation time 542945811 ps
CPU time 2.44 seconds
Started Feb 08 11:36:30 AM UTC 25
Finished Feb 08 11:36:35 AM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001527516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1001527516
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3530463052
Short name T884
Test name
Test status
Simulation time 4139595686 ps
CPU time 7.19 seconds
Started Feb 08 11:36:30 AM UTC 25
Finished Feb 08 11:36:39 AM UTC 25
Peak memory 211432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530463052 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.3530463052
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2706714730
Short name T890
Test name
Test status
Simulation time 536721902 ps
CPU time 3.04 seconds
Started Feb 08 11:36:36 AM UTC 25
Finished Feb 08 11:36:41 AM UTC 25
Peak memory 211396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27067
14730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_re
set.2706714730
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4150041648
Short name T887
Test name
Test status
Simulation time 339284292 ps
CPU time 2.42 seconds
Started Feb 08 11:36:35 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 211256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150041648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4150041648
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2212860686
Short name T880
Test name
Test status
Simulation time 422225155 ps
CPU time 1.7 seconds
Started Feb 08 11:36:34 AM UTC 25
Finished Feb 08 11:36:38 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212860686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2212860686
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.433079720
Short name T889
Test name
Test status
Simulation time 2933202605 ps
CPU time 2.73 seconds
Started Feb 08 11:36:35 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 211188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433079720 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.433079720
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1352717315
Short name T878
Test name
Test status
Simulation time 713224176 ps
CPU time 2.79 seconds
Started Feb 08 11:36:33 AM UTC 25
Finished Feb 08 11:36:38 AM UTC 25
Peak memory 211536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352717315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1352717315
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.685271432
Short name T917
Test name
Test status
Simulation time 4466147752 ps
CPU time 15.42 seconds
Started Feb 08 11:36:34 AM UTC 25
Finished Feb 08 11:36:52 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685271432 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.685271432
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.85292226
Short name T113
Test name
Test status
Simulation time 445168278 ps
CPU time 3.04 seconds
Started Feb 08 11:35:23 AM UTC 25
Finished Feb 08 11:35:28 AM UTC 25
Peak memory 211304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85292226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.85292226
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4180606644
Short name T814
Test name
Test status
Simulation time 26380168504 ps
CPU time 33.81 seconds
Started Feb 08 11:35:22 AM UTC 25
Finished Feb 08 11:35:58 AM UTC 25
Peak memory 211604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180606644 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.4180606644
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1407663959
Short name T112
Test name
Test status
Simulation time 1058177689 ps
CPU time 2.45 seconds
Started Feb 08 11:35:20 AM UTC 25
Finished Feb 08 11:35:24 AM UTC 25
Peak memory 211188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407663959 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.1407663959
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1618653670
Short name T90
Test name
Test status
Simulation time 448330533 ps
CPU time 3.21 seconds
Started Feb 08 11:35:25 AM UTC 25
Finished Feb 08 11:35:30 AM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16186
53670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_res
et.1618653670
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1295591031
Short name T123
Test name
Test status
Simulation time 582818447 ps
CPU time 1.85 seconds
Started Feb 08 11:35:21 AM UTC 25
Finished Feb 08 11:35:24 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295591031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1295591031
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3662498572
Short name T803
Test name
Test status
Simulation time 454669650 ps
CPU time 1.74 seconds
Started Feb 08 11:35:19 AM UTC 25
Finished Feb 08 11:35:22 AM UTC 25
Peak memory 210200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662498572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3662498572
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1558416835
Short name T124
Test name
Test status
Simulation time 2147372666 ps
CPU time 6.64 seconds
Started Feb 08 11:35:24 AM UTC 25
Finished Feb 08 11:35:33 AM UTC 25
Peak memory 211184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558416835 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.1558416835
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2262287580
Short name T80
Test name
Test status
Simulation time 543412511 ps
CPU time 2.34 seconds
Started Feb 08 11:35:15 AM UTC 25
Finished Feb 08 11:35:19 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262287580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2262287580
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.994322345
Short name T74
Test name
Test status
Simulation time 5755776180 ps
CPU time 4.53 seconds
Started Feb 08 11:35:15 AM UTC 25
Finished Feb 08 11:35:21 AM UTC 25
Peak memory 211552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994322345 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.994322345
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1413694725
Short name T882
Test name
Test status
Simulation time 411843177 ps
CPU time 1.3 seconds
Started Feb 08 11:36:36 AM UTC 25
Finished Feb 08 11:36:39 AM UTC 25
Peak memory 210292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413694725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1413694725
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2486206493
Short name T883
Test name
Test status
Simulation time 466984498 ps
CPU time 1.17 seconds
Started Feb 08 11:36:36 AM UTC 25
Finished Feb 08 11:36:39 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486206493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2486206493
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2742944089
Short name T892
Test name
Test status
Simulation time 518354247 ps
CPU time 3.4 seconds
Started Feb 08 11:36:36 AM UTC 25
Finished Feb 08 11:36:41 AM UTC 25
Peak memory 211088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742944089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2742944089
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2922827817
Short name T885
Test name
Test status
Simulation time 501084438 ps
CPU time 1.09 seconds
Started Feb 08 11:36:37 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922827817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2922827817
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2586106170
Short name T886
Test name
Test status
Simulation time 518697279 ps
CPU time 1.26 seconds
Started Feb 08 11:36:37 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586106170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2586106170
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.572947664
Short name T893
Test name
Test status
Simulation time 305000262 ps
CPU time 1.57 seconds
Started Feb 08 11:36:38 AM UTC 25
Finished Feb 08 11:36:41 AM UTC 25
Peak memory 210124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572947664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.572947664
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.36906834
Short name T891
Test name
Test status
Simulation time 373944576 ps
CPU time 0.9 seconds
Started Feb 08 11:36:38 AM UTC 25
Finished Feb 08 11:36:41 AM UTC 25
Peak memory 210076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36906834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.36906834
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2981276526
Short name T898
Test name
Test status
Simulation time 359529446 ps
CPU time 1.97 seconds
Started Feb 08 11:36:39 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 209716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981276526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2981276526
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2664084664
Short name T895
Test name
Test status
Simulation time 534373128 ps
CPU time 1.34 seconds
Started Feb 08 11:36:39 AM UTC 25
Finished Feb 08 11:36:42 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664084664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2664084664
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.580027783
Short name T896
Test name
Test status
Simulation time 362956798 ps
CPU time 1.86 seconds
Started Feb 08 11:36:39 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 210168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580027783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.580027783
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3969811653
Short name T115
Test name
Test status
Simulation time 670979357 ps
CPU time 2.38 seconds
Started Feb 08 11:35:34 AM UTC 25
Finished Feb 08 11:35:38 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969811653 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.3969811653
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.320626456
Short name T894
Test name
Test status
Simulation time 26022268602 ps
CPU time 66.08 seconds
Started Feb 08 11:35:34 AM UTC 25
Finished Feb 08 11:36:42 AM UTC 25
Peak memory 211404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320626456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.320626456
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2827551439
Short name T805
Test name
Test status
Simulation time 766409997 ps
CPU time 2.78 seconds
Started Feb 08 11:35:33 AM UTC 25
Finished Feb 08 11:35:37 AM UTC 25
Peak memory 211324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827551439 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.2827551439
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1339705391
Short name T108
Test name
Test status
Simulation time 528371240 ps
CPU time 3.64 seconds
Started Feb 08 11:35:35 AM UTC 25
Finished Feb 08 11:35:40 AM UTC 25
Peak memory 211188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13397
05391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_res
et.1339705391
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.967071125
Short name T114
Test name
Test status
Simulation time 492535200 ps
CPU time 2 seconds
Started Feb 08 11:35:34 AM UTC 25
Finished Feb 08 11:35:37 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967071125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_t
est +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.967071125
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3433818091
Short name T804
Test name
Test status
Simulation time 325339814 ps
CPU time 1.13 seconds
Started Feb 08 11:35:31 AM UTC 25
Finished Feb 08 11:35:33 AM UTC 25
Peak memory 210140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433818091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3433818091
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4094614724
Short name T70
Test name
Test status
Simulation time 2416967322 ps
CPU time 5.27 seconds
Started Feb 08 11:35:35 AM UTC 25
Finished Feb 08 11:35:42 AM UTC 25
Peak memory 211456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094614724 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.4094614724
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.852186120
Short name T82
Test name
Test status
Simulation time 311450740 ps
CPU time 3.45 seconds
Started Feb 08 11:35:28 AM UTC 25
Finished Feb 08 11:35:33 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852186120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.852186120
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.931408452
Short name T77
Test name
Test status
Simulation time 4463571961 ps
CPU time 6.41 seconds
Started Feb 08 11:35:29 AM UTC 25
Finished Feb 08 11:35:37 AM UTC 25
Peak memory 211468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931408452 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.931408452
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.3409328122
Short name T897
Test name
Test status
Simulation time 321778966 ps
CPU time 1.84 seconds
Started Feb 08 11:36:39 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409328122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3409328122
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1256609466
Short name T900
Test name
Test status
Simulation time 456363740 ps
CPU time 1.3 seconds
Started Feb 08 11:36:40 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 209836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256609466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1256609466
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.452698582
Short name T899
Test name
Test status
Simulation time 366116192 ps
CPU time 1.11 seconds
Started Feb 08 11:36:40 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 209828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452698582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.452698582
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4214032602
Short name T901
Test name
Test status
Simulation time 434282797 ps
CPU time 1.36 seconds
Started Feb 08 11:36:40 AM UTC 25
Finished Feb 08 11:36:43 AM UTC 25
Peak memory 210132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214032602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4214032602
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1942472968
Short name T902
Test name
Test status
Simulation time 396760303 ps
CPU time 1.79 seconds
Started Feb 08 11:36:40 AM UTC 25
Finished Feb 08 11:36:44 AM UTC 25
Peak memory 210076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942472968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1942472968
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2918053348
Short name T904
Test name
Test status
Simulation time 507961415 ps
CPU time 2.29 seconds
Started Feb 08 11:36:40 AM UTC 25
Finished Feb 08 11:36:44 AM UTC 25
Peak memory 211048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918053348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2918053348
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.299180612
Short name T908
Test name
Test status
Simulation time 404733003 ps
CPU time 2.33 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:45 AM UTC 25
Peak memory 211036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299180612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.299180612
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.1129304650
Short name T903
Test name
Test status
Simulation time 485145188 ps
CPU time 1.03 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:44 AM UTC 25
Peak memory 210136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129304650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1129304650
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.3515395580
Short name T907
Test name
Test status
Simulation time 282225342 ps
CPU time 1.87 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:45 AM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515395580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3515395580
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3663143084
Short name T909
Test name
Test status
Simulation time 465752750 ps
CPU time 2.33 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 211128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663143084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3663143084
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1898291154
Short name T117
Test name
Test status
Simulation time 815740418 ps
CPU time 4.2 seconds
Started Feb 08 11:35:40 AM UTC 25
Finished Feb 08 11:35:46 AM UTC 25
Peak memory 211376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898291154 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.1898291154
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2974247515
Short name T918
Test name
Test status
Simulation time 37885433280 ps
CPU time 142.27 seconds
Started Feb 08 11:35:39 AM UTC 25
Finished Feb 08 11:38:04 AM UTC 25
Peak memory 211540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974247515 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.2974247515
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.21784392
Short name T116
Test name
Test status
Simulation time 960421545 ps
CPU time 1.83 seconds
Started Feb 08 11:35:38 AM UTC 25
Finished Feb 08 11:35:41 AM UTC 25
Peak memory 209952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21784392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.21784392
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.175133623
Short name T81
Test name
Test status
Simulation time 362338693 ps
CPU time 3.02 seconds
Started Feb 08 11:35:42 AM UTC 25
Finished Feb 08 11:35:47 AM UTC 25
Peak memory 211252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17513
3623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.175133623
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3219024020
Short name T125
Test name
Test status
Simulation time 315313619 ps
CPU time 2.03 seconds
Started Feb 08 11:35:38 AM UTC 25
Finished Feb 08 11:35:41 AM UTC 25
Peak memory 211248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219024020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3219024020
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1903510943
Short name T806
Test name
Test status
Simulation time 389667099 ps
CPU time 1.48 seconds
Started Feb 08 11:35:38 AM UTC 25
Finished Feb 08 11:35:41 AM UTC 25
Peak memory 209780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903510943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1903510943
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3077991182
Short name T71
Test name
Test status
Simulation time 4300416499 ps
CPU time 8.19 seconds
Started Feb 08 11:35:41 AM UTC 25
Finished Feb 08 11:35:51 AM UTC 25
Peak memory 211468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077991182 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.3077991182
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1250080670
Short name T84
Test name
Test status
Simulation time 410789207 ps
CPU time 3.61 seconds
Started Feb 08 11:35:37 AM UTC 25
Finished Feb 08 11:35:42 AM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250080670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1250080670
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2552315345
Short name T905
Test name
Test status
Simulation time 363944461 ps
CPU time 0.94 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:44 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552315345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2552315345
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3162069404
Short name T906
Test name
Test status
Simulation time 476975694 ps
CPU time 1.41 seconds
Started Feb 08 11:36:41 AM UTC 25
Finished Feb 08 11:36:45 AM UTC 25
Peak memory 209776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162069404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3162069404
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2409097174
Short name T911
Test name
Test status
Simulation time 407818226 ps
CPU time 1.3 seconds
Started Feb 08 11:36:43 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 209832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409097174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2409097174
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1087909474
Short name T913
Test name
Test status
Simulation time 432466863 ps
CPU time 1.73 seconds
Started Feb 08 11:36:43 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 210296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087909474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1087909474
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3878851117
Short name T879
Test name
Test status
Simulation time 484744978 ps
CPU time 1.46 seconds
Started Feb 08 11:36:43 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 210196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878851117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3878851117
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1122887559
Short name T912
Test name
Test status
Simulation time 538740690 ps
CPU time 1.47 seconds
Started Feb 08 11:36:43 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 210196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122887559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1122887559
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.39941537
Short name T910
Test name
Test status
Simulation time 482260065 ps
CPU time 1.14 seconds
Started Feb 08 11:36:43 AM UTC 25
Finished Feb 08 11:36:46 AM UTC 25
Peak memory 209684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39941537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.39941537
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1963241908
Short name T915
Test name
Test status
Simulation time 444825944 ps
CPU time 1.29 seconds
Started Feb 08 11:36:44 AM UTC 25
Finished Feb 08 11:36:47 AM UTC 25
Peak memory 209716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963241908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1963241908
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.2547885766
Short name T916
Test name
Test status
Simulation time 315899255 ps
CPU time 2.36 seconds
Started Feb 08 11:36:44 AM UTC 25
Finished Feb 08 11:36:48 AM UTC 25
Peak memory 211056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547885766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2547885766
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.20877436
Short name T914
Test name
Test status
Simulation time 353980653 ps
CPU time 1.18 seconds
Started Feb 08 11:36:44 AM UTC 25
Finished Feb 08 11:36:47 AM UTC 25
Peak memory 210016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20877436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.20877436
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.328480380
Short name T809
Test name
Test status
Simulation time 429616421 ps
CPU time 1.65 seconds
Started Feb 08 11:35:47 AM UTC 25
Finished Feb 08 11:35:50 AM UTC 25
Peak memory 210016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32848
0380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.328480380
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3253146555
Short name T807
Test name
Test status
Simulation time 561121478 ps
CPU time 1.71 seconds
Started Feb 08 11:35:42 AM UTC 25
Finished Feb 08 11:35:46 AM UTC 25
Peak memory 209716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253146555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3253146555
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.4179530693
Short name T808
Test name
Test status
Simulation time 530356965 ps
CPU time 3.39 seconds
Started Feb 08 11:35:42 AM UTC 25
Finished Feb 08 11:35:47 AM UTC 25
Peak memory 211056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179530693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4179530693
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4040615903
Short name T818
Test name
Test status
Simulation time 5194404464 ps
CPU time 15.02 seconds
Started Feb 08 11:35:43 AM UTC 25
Finished Feb 08 11:36:00 AM UTC 25
Peak memory 211404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040615903 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.4040615903
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1542288620
Short name T86
Test name
Test status
Simulation time 828300903 ps
CPU time 4.04 seconds
Started Feb 08 11:35:42 AM UTC 25
Finished Feb 08 11:35:48 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542288620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1542288620
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4028151757
Short name T352
Test name
Test status
Simulation time 8636153207 ps
CPU time 15.72 seconds
Started Feb 08 11:35:42 AM UTC 25
Finished Feb 08 11:36:00 AM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028151757 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.4028151757
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3464458421
Short name T812
Test name
Test status
Simulation time 489671413 ps
CPU time 3.43 seconds
Started Feb 08 11:35:51 AM UTC 25
Finished Feb 08 11:35:56 AM UTC 25
Peak memory 211452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34644
58421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_res
et.3464458421
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3307075829
Short name T126
Test name
Test status
Simulation time 392073074 ps
CPU time 1.96 seconds
Started Feb 08 11:35:49 AM UTC 25
Finished Feb 08 11:35:53 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307075829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3307075829
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1385656592
Short name T810
Test name
Test status
Simulation time 497717353 ps
CPU time 1.56 seconds
Started Feb 08 11:35:49 AM UTC 25
Finished Feb 08 11:35:52 AM UTC 25
Peak memory 210200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385656592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1385656592
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3828871008
Short name T852
Test name
Test status
Simulation time 4908978654 ps
CPU time 31.46 seconds
Started Feb 08 11:35:49 AM UTC 25
Finished Feb 08 11:36:22 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828871008 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3828871008
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3608584109
Short name T85
Test name
Test status
Simulation time 503535484 ps
CPU time 5.33 seconds
Started Feb 08 11:35:47 AM UTC 25
Finished Feb 08 11:35:53 AM UTC 25
Peak memory 221464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608584109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3608584109
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2755400431
Short name T849
Test name
Test status
Simulation time 8991931516 ps
CPU time 32.4 seconds
Started Feb 08 11:35:48 AM UTC 25
Finished Feb 08 11:36:22 AM UTC 25
Peak memory 211460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755400431 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.2755400431
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2697641443
Short name T816
Test name
Test status
Simulation time 421834113 ps
CPU time 1.66 seconds
Started Feb 08 11:35:56 AM UTC 25
Finished Feb 08 11:35:59 AM UTC 25
Peak memory 210024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26976
41443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_res
et.2697641443
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2818601801
Short name T118
Test name
Test status
Simulation time 611401891 ps
CPU time 1.59 seconds
Started Feb 08 11:35:54 AM UTC 25
Finished Feb 08 11:35:57 AM UTC 25
Peak memory 209956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818601801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2818601801
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1975378251
Short name T813
Test name
Test status
Simulation time 506431077 ps
CPU time 1.46 seconds
Started Feb 08 11:35:53 AM UTC 25
Finished Feb 08 11:35:56 AM UTC 25
Peak memory 209720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975378251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1975378251
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1776008414
Short name T815
Test name
Test status
Simulation time 4741948142 ps
CPU time 2.98 seconds
Started Feb 08 11:35:54 AM UTC 25
Finished Feb 08 11:35:58 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776008414 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.1776008414
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1017942177
Short name T811
Test name
Test status
Simulation time 709142159 ps
CPU time 2.64 seconds
Started Feb 08 11:35:51 AM UTC 25
Finished Feb 08 11:35:55 AM UTC 25
Peak memory 211400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017942177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1017942177
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3651512143
Short name T819
Test name
Test status
Simulation time 4814416427 ps
CPU time 7.45 seconds
Started Feb 08 11:35:52 AM UTC 25
Finished Feb 08 11:36:01 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651512143 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.3651512143
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3690843981
Short name T823
Test name
Test status
Simulation time 347614271 ps
CPU time 2.7 seconds
Started Feb 08 11:36:00 AM UTC 25
Finished Feb 08 11:36:05 AM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36908
43981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_res
et.3690843981
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.260938602
Short name T120
Test name
Test status
Simulation time 527878984 ps
CPU time 3.72 seconds
Started Feb 08 11:35:58 AM UTC 25
Finished Feb 08 11:36:04 AM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260938602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_t
est +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.260938602
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.253082431
Short name T820
Test name
Test status
Simulation time 313779626 ps
CPU time 1.21 seconds
Started Feb 08 11:35:58 AM UTC 25
Finished Feb 08 11:36:02 AM UTC 25
Peak memory 210152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253082431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.253082431
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3175898170
Short name T829
Test name
Test status
Simulation time 2527458867 ps
CPU time 8.35 seconds
Started Feb 08 11:35:59 AM UTC 25
Finished Feb 08 11:36:10 AM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175898170 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.3175898170
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3334901158
Short name T817
Test name
Test status
Simulation time 759203523 ps
CPU time 2.27 seconds
Started Feb 08 11:35:56 AM UTC 25
Finished Feb 08 11:36:00 AM UTC 25
Peak memory 211400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334901158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3334901158
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1884427277
Short name T836
Test name
Test status
Simulation time 4073991762 ps
CPU time 14.64 seconds
Started Feb 08 11:35:57 AM UTC 25
Finished Feb 08 11:36:14 AM UTC 25
Peak memory 211404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884427277 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.1884427277
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2450399179
Short name T825
Test name
Test status
Simulation time 489095358 ps
CPU time 1.74 seconds
Started Feb 08 11:36:03 AM UTC 25
Finished Feb 08 11:36:06 AM UTC 25
Peak memory 210016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24503
99179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_res
et.2450399179
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2139135009
Short name T824
Test name
Test status
Simulation time 437036169 ps
CPU time 3.02 seconds
Started Feb 08 11:36:02 AM UTC 25
Finished Feb 08 11:36:06 AM UTC 25
Peak memory 211316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139135009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2139135009
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.566084735
Short name T822
Test name
Test status
Simulation time 559136623 ps
CPU time 1.14 seconds
Started Feb 08 11:36:02 AM UTC 25
Finished Feb 08 11:36:05 AM UTC 25
Peak memory 209652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566084735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test
+UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.566084735
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.549261660
Short name T846
Test name
Test status
Simulation time 4526221909 ps
CPU time 17.64 seconds
Started Feb 08 11:36:02 AM UTC 25
Finished Feb 08 11:36:21 AM UTC 25
Peak memory 211612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549261660 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.549261660
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4224342146
Short name T826
Test name
Test status
Simulation time 367499654 ps
CPU time 3.87 seconds
Started Feb 08 11:36:00 AM UTC 25
Finished Feb 08 11:36:06 AM UTC 25
Peak memory 211344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224342146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_tes
t +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4224342146
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2800566397
Short name T353
Test name
Test status
Simulation time 8229295512 ps
CPU time 12.72 seconds
Started Feb 08 11:36:01 AM UTC 25
Finished Feb 08 11:36:16 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800566397 -assert nopostproc +UVM_TESTNAME=adc_c
trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.2800566397
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.752358512
Short name T154
Test name
Test status
Simulation time 162103368855 ps
CPU time 390.55 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:26:27 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752358512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.752358512
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.805693988
Short name T140
Test name
Test status
Simulation time 316220586994 ps
CPU time 298.73 seconds
Started Feb 08 10:19:50 AM UTC 25
Finished Feb 08 10:24:53 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805693988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.805693988
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1599972080
Short name T377
Test name
Test status
Simulation time 327163550317 ps
CPU time 560.55 seconds
Started Feb 08 10:19:50 AM UTC 25
Finished Feb 08 10:29:17 AM UTC 25
Peak memory 212572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599972080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.1599972080
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4259937255
Short name T275
Test name
Test status
Simulation time 424790553104 ps
CPU time 555.25 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:29:13 AM UTC 25
Peak memory 212584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259937255 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.4259937255
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1243170310
Short name T11
Test name
Test status
Simulation time 39341807276 ps
CPU time 59.85 seconds
Started Feb 08 10:19:52 AM UTC 25
Finished Feb 08 10:20:55 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243170310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1243170310
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1439960522
Short name T4
Test name
Test status
Simulation time 5245968320 ps
CPU time 12.07 seconds
Started Feb 08 10:19:51 AM UTC 25
Finished Feb 08 10:20:05 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439960522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1439960522
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1344833594
Short name T3
Test name
Test status
Simulation time 5499231133 ps
CPU time 10.46 seconds
Started Feb 08 10:19:50 AM UTC 25
Finished Feb 08 10:20:02 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344833594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1344833594
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.864796760
Short name T62
Test name
Test status
Simulation time 150421833770 ps
CPU time 495.87 seconds
Started Feb 08 10:19:52 AM UTC 25
Finished Feb 08 10:28:15 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864796760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.864796760
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2660266716
Short name T41
Test name
Test status
Simulation time 407557178502 ps
CPU time 245.11 seconds
Started Feb 08 10:19:52 AM UTC 25
Finished Feb 08 10:24:02 AM UTC 25
Peak memory 221984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2660266716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_al
l_with_rand_reset.2660266716
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.1419830167
Short name T21
Test name
Test status
Simulation time 463140728 ps
CPU time 2.11 seconds
Started Feb 08 10:20:16 AM UTC 25
Finished Feb 08 10:20:19 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419830167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1419830167
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.4259047493
Short name T136
Test name
Test status
Simulation time 356957020395 ps
CPU time 847.44 seconds
Started Feb 08 10:20:01 AM UTC 25
Finished Feb 08 10:34:18 AM UTC 25
Peak memory 212640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259047493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4259047493
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1283545341
Short name T132
Test name
Test status
Simulation time 330714208248 ps
CPU time 318.96 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:25:19 AM UTC 25
Peak memory 211592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283545341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1283545341
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2480379871
Short name T373
Test name
Test status
Simulation time 335080158393 ps
CPU time 522.54 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:28:44 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480379871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.2480379871
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2027219872
Short name T133
Test name
Test status
Simulation time 164868833622 ps
CPU time 439.46 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:27:20 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027219872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2027219872
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.86086096
Short name T43
Test name
Test status
Simulation time 157980137050 ps
CPU time 273.21 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:24:32 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86086096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM
_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.86086096
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3369837197
Short name T159
Test name
Test status
Simulation time 181734925333 ps
CPU time 455.43 seconds
Started Feb 08 10:19:56 AM UTC 25
Finished Feb 08 10:27:37 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369837197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.3369837197
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2433551136
Short name T254
Test name
Test status
Simulation time 601226623399 ps
CPU time 519.73 seconds
Started Feb 08 10:19:59 AM UTC 25
Finished Feb 08 10:28:45 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433551136 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.2433551136
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2950554529
Short name T59
Test name
Test status
Simulation time 70257829654 ps
CPU time 525.77 seconds
Started Feb 08 10:20:02 AM UTC 25
Finished Feb 08 10:28:55 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950554529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2950554529
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.2499244314
Short name T5
Test name
Test status
Simulation time 3216427672 ps
CPU time 4.68 seconds
Started Feb 08 10:20:01 AM UTC 25
Finished Feb 08 10:20:08 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499244314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2499244314
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2078570845
Short name T23
Test name
Test status
Simulation time 8032851316 ps
CPU time 19.39 seconds
Started Feb 08 10:20:08 AM UTC 25
Finished Feb 08 10:20:30 AM UTC 25
Peak memory 243824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078570845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2078570845
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1195026866
Short name T2
Test name
Test status
Simulation time 5654932379 ps
CPU time 5.28 seconds
Started Feb 08 10:19:55 AM UTC 25
Finished Feb 08 10:20:02 AM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195026866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1195026866
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3179613303
Short name T46
Test name
Test status
Simulation time 525200587833 ps
CPU time 1968.63 seconds
Started Feb 08 10:20:05 AM UTC 25
Finished Feb 08 10:53:15 AM UTC 25
Peak memory 212780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179613303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.3179613303
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2126656015
Short name T387
Test name
Test status
Simulation time 531063656 ps
CPU time 1.57 seconds
Started Feb 08 10:32:34 AM UTC 25
Finished Feb 08 10:32:38 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126656015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2126656015
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1829338151
Short name T143
Test name
Test status
Simulation time 330901927134 ps
CPU time 488.81 seconds
Started Feb 08 10:31:15 AM UTC 25
Finished Feb 08 10:39:30 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829338151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1829338151
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2474222171
Short name T138
Test name
Test status
Simulation time 154446316021 ps
CPU time 93.81 seconds
Started Feb 08 10:31:15 AM UTC 25
Finished Feb 08 10:32:52 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474222171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.2474222171
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3993020834
Short name T268
Test name
Test status
Simulation time 159602262713 ps
CPU time 113.32 seconds
Started Feb 08 10:31:10 AM UTC 25
Finished Feb 08 10:33:06 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993020834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3993020834
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.3127026510
Short name T203
Test name
Test status
Simulation time 489894666508 ps
CPU time 293.52 seconds
Started Feb 08 10:31:13 AM UTC 25
Finished Feb 08 10:36:11 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127026510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.3127026510
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1269070795
Short name T415
Test name
Test status
Simulation time 408148646285 ps
CPU time 641.2 seconds
Started Feb 08 10:31:25 AM UTC 25
Finished Feb 08 10:42:14 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269070795 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.1269070795
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1899803
Short name T390
Test name
Test status
Simulation time 44028580186 ps
CPU time 104.75 seconds
Started Feb 08 10:31:59 AM UTC 25
Finished Feb 08 10:33:47 AM UTC 25
Peak memory 211680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl
_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1899803
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1992017511
Short name T386
Test name
Test status
Simulation time 4930425138 ps
CPU time 16.51 seconds
Started Feb 08 10:31:58 AM UTC 25
Finished Feb 08 10:32:16 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992017511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1992017511
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.992561243
Short name T105
Test name
Test status
Simulation time 5856182923 ps
CPU time 12.31 seconds
Started Feb 08 10:30:59 AM UTC 25
Finished Feb 08 10:31:13 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992561243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.adc_ctrl_smoke.992561243
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3252154805
Short name T144
Test name
Test status
Simulation time 164904261942 ps
CPU time 437.36 seconds
Started Feb 08 10:32:18 AM UTC 25
Finished Feb 08 10:39:42 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252154805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.3252154805
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.7872988
Short name T53
Test name
Test status
Simulation time 426581478496 ps
CPU time 270.81 seconds
Started Feb 08 10:32:17 AM UTC 25
Finished Feb 08 10:36:51 AM UTC 25
Peak memory 222116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=7872988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_
with_rand_reset.7872988
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2638927803
Short name T393
Test name
Test status
Simulation time 364586933 ps
CPU time 1.7 seconds
Started Feb 08 10:35:08 AM UTC 25
Finished Feb 08 10:35:11 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638927803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2638927803
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.906595773
Short name T157
Test name
Test status
Simulation time 336136200016 ps
CPU time 238.49 seconds
Started Feb 08 10:32:52 AM UTC 25
Finished Feb 08 10:36:55 AM UTC 25
Peak memory 211780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906595773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.906595773
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3281669711
Short name T401
Test name
Test status
Simulation time 169468722803 ps
CPU time 214.66 seconds
Started Feb 08 10:33:03 AM UTC 25
Finished Feb 08 10:36:41 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281669711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.3281669711
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3781645209
Short name T166
Test name
Test status
Simulation time 329621432883 ps
CPU time 77.68 seconds
Started Feb 08 10:32:40 AM UTC 25
Finished Feb 08 10:34:00 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781645209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3781645209
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4125233538
Short name T468
Test name
Test status
Simulation time 495352856042 ps
CPU time 1315.24 seconds
Started Feb 08 10:32:46 AM UTC 25
Finished Feb 08 10:54:56 AM UTC 25
Peak memory 212644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125233538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.4125233538
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3655211872
Short name T226
Test name
Test status
Simulation time 368689180196 ps
CPU time 598.52 seconds
Started Feb 08 10:33:07 AM UTC 25
Finished Feb 08 10:43:13 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655211872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.3655211872
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3303670524
Short name T98
Test name
Test status
Simulation time 402839164601 ps
CPU time 990.74 seconds
Started Feb 08 10:33:28 AM UTC 25
Finished Feb 08 10:50:10 AM UTC 25
Peak memory 212912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303670524 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.3303670524
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.993360036
Short name T395
Test name
Test status
Simulation time 35920934125 ps
CPU time 75.87 seconds
Started Feb 08 10:34:11 AM UTC 25
Finished Feb 08 10:35:29 AM UTC 25
Peak memory 211620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993360036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.993360036
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1760821988
Short name T392
Test name
Test status
Simulation time 5466708158 ps
CPU time 16.04 seconds
Started Feb 08 10:34:06 AM UTC 25
Finished Feb 08 10:34:24 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760821988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1760821988
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3592500387
Short name T388
Test name
Test status
Simulation time 5963226774 ps
CPU time 4.71 seconds
Started Feb 08 10:32:39 AM UTC 25
Finished Feb 08 10:32:45 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592500387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3592500387
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1916667427
Short name T398
Test name
Test status
Simulation time 426340456 ps
CPU time 1.35 seconds
Started Feb 08 10:36:13 AM UTC 25
Finished Feb 08 10:36:16 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916667427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1916667427
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1118964705
Short name T158
Test name
Test status
Simulation time 164193043782 ps
CPU time 109.6 seconds
Started Feb 08 10:35:19 AM UTC 25
Finished Feb 08 10:37:11 AM UTC 25
Peak memory 211760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118964705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1118964705
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3175683899
Short name T412
Test name
Test status
Simulation time 486422154352 ps
CPU time 359.38 seconds
Started Feb 08 10:35:26 AM UTC 25
Finished Feb 08 10:41:30 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175683899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.3175683899
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1611767948
Short name T294
Test name
Test status
Simulation time 157153178672 ps
CPU time 184.23 seconds
Started Feb 08 10:35:12 AM UTC 25
Finished Feb 08 10:38:20 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611767948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1611767948
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1772561463
Short name T96
Test name
Test status
Simulation time 495467477753 ps
CPU time 856.73 seconds
Started Feb 08 10:35:19 AM UTC 25
Finished Feb 08 10:49:46 AM UTC 25
Peak memory 212572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772561463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.1772561463
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2926178792
Short name T288
Test name
Test status
Simulation time 339683623785 ps
CPU time 1179.48 seconds
Started Feb 08 10:35:29 AM UTC 25
Finished Feb 08 10:55:22 AM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926178792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.2926178792
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1032962075
Short name T417
Test name
Test status
Simulation time 199716826791 ps
CPU time 455.68 seconds
Started Feb 08 10:35:41 AM UTC 25
Finished Feb 08 10:43:23 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032962075 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.1032962075
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.901780751
Short name T431
Test name
Test status
Simulation time 77856275426 ps
CPU time 617.88 seconds
Started Feb 08 10:36:06 AM UTC 25
Finished Feb 08 10:46:31 AM UTC 25
Peak memory 212032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901780751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.901780751
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3002775746
Short name T400
Test name
Test status
Simulation time 30106978962 ps
CPU time 22.75 seconds
Started Feb 08 10:36:05 AM UTC 25
Finished Feb 08 10:36:29 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002775746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3002775746
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1661430514
Short name T397
Test name
Test status
Simulation time 4886916036 ps
CPU time 5.84 seconds
Started Feb 08 10:36:05 AM UTC 25
Finished Feb 08 10:36:12 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661430514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1661430514
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.3771469276
Short name T394
Test name
Test status
Simulation time 5902154261 ps
CPU time 7.36 seconds
Started Feb 08 10:35:10 AM UTC 25
Finished Feb 08 10:35:19 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771469276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3771469276
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3437491347
Short name T205
Test name
Test status
Simulation time 121082504001 ps
CPU time 432 seconds
Started Feb 08 10:36:12 AM UTC 25
Finished Feb 08 10:43:28 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437491347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.3437491347
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1766677157
Short name T404
Test name
Test status
Simulation time 488615798 ps
CPU time 2.11 seconds
Started Feb 08 10:37:33 AM UTC 25
Finished Feb 08 10:37:37 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766677157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1766677157
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.4164437349
Short name T241
Test name
Test status
Simulation time 183118085664 ps
CPU time 254.73 seconds
Started Feb 08 10:36:56 AM UTC 25
Finished Feb 08 10:41:14 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164437349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.4164437349
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.346927302
Short name T99
Test name
Test status
Simulation time 485119864911 ps
CPU time 810.74 seconds
Started Feb 08 10:36:31 AM UTC 25
Finished Feb 08 10:50:11 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346927302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.346927302
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1539955115
Short name T190
Test name
Test status
Simulation time 338511364305 ps
CPU time 278.68 seconds
Started Feb 08 10:36:17 AM UTC 25
Finished Feb 08 10:41:00 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539955115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1539955115
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.715931958
Short name T406
Test name
Test status
Simulation time 163212542915 ps
CPU time 121.97 seconds
Started Feb 08 10:36:20 AM UTC 25
Finished Feb 08 10:38:25 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715931958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.715931958
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.523996196
Short name T416
Test name
Test status
Simulation time 204274515963 ps
CPU time 345.02 seconds
Started Feb 08 10:36:53 AM UTC 25
Finished Feb 08 10:42:43 AM UTC 25
Peak memory 211636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523996196 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.523996196
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1304091856
Short name T217
Test name
Test status
Simulation time 83131676457 ps
CPU time 454.68 seconds
Started Feb 08 10:37:18 AM UTC 25
Finished Feb 08 10:44:59 AM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304091856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1304091856
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3645792504
Short name T407
Test name
Test status
Simulation time 36394491378 ps
CPU time 109.37 seconds
Started Feb 08 10:37:12 AM UTC 25
Finished Feb 08 10:39:04 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645792504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3645792504
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.2791081708
Short name T402
Test name
Test status
Simulation time 4333996505 ps
CPU time 9.57 seconds
Started Feb 08 10:37:06 AM UTC 25
Finished Feb 08 10:37:17 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791081708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2791081708
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2033130663
Short name T399
Test name
Test status
Simulation time 6352260814 ps
CPU time 2.59 seconds
Started Feb 08 10:36:16 AM UTC 25
Finished Feb 08 10:36:21 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033130663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2033130663
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1549524766
Short name T175
Test name
Test status
Simulation time 168175667358 ps
CPU time 326.81 seconds
Started Feb 08 10:37:19 AM UTC 25
Finished Feb 08 10:42:51 AM UTC 25
Peak memory 222184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1549524766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_a
ll_with_rand_reset.1549524766
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3043689563
Short name T410
Test name
Test status
Simulation time 463441806 ps
CPU time 1.92 seconds
Started Feb 08 10:39:42 AM UTC 25
Finished Feb 08 10:39:45 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043689563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3043689563
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.1546856993
Short name T162
Test name
Test status
Simulation time 340356048308 ps
CPU time 228.85 seconds
Started Feb 08 10:38:26 AM UTC 25
Finished Feb 08 10:42:18 AM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546856993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.1546856993
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1630403877
Short name T273
Test name
Test status
Simulation time 157845861785 ps
CPU time 169.92 seconds
Started Feb 08 10:38:36 AM UTC 25
Finished Feb 08 10:41:29 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630403877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1630403877
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.266768155
Short name T93
Test name
Test status
Simulation time 321456799520 ps
CPU time 646.81 seconds
Started Feb 08 10:38:14 AM UTC 25
Finished Feb 08 10:49:09 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266768155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.266768155
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1139727079
Short name T522
Test name
Test status
Simulation time 488698444151 ps
CPU time 1446.43 seconds
Started Feb 08 10:38:01 AM UTC 25
Finished Feb 08 11:02:23 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139727079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1139727079
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2119068448
Short name T451
Test name
Test status
Simulation time 483871540420 ps
CPU time 795.99 seconds
Started Feb 08 10:38:03 AM UTC 25
Finished Feb 08 10:51:28 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119068448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.2119068448
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.1020641343
Short name T444
Test name
Test status
Simulation time 247996643037 ps
CPU time 734.73 seconds
Started Feb 08 10:38:17 AM UTC 25
Finished Feb 08 10:50:42 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020641343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.1020641343
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4207612013
Short name T470
Test name
Test status
Simulation time 404870836103 ps
CPU time 1021.3 seconds
Started Feb 08 10:38:20 AM UTC 25
Finished Feb 08 10:55:32 AM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207612013 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.4207612013
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2610788671
Short name T360
Test name
Test status
Simulation time 115873053705 ps
CPU time 531.98 seconds
Started Feb 08 10:39:14 AM UTC 25
Finished Feb 08 10:48:12 AM UTC 25
Peak memory 211984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610788671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2610788671
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3807473735
Short name T409
Test name
Test status
Simulation time 31830592348 ps
CPU time 24.19 seconds
Started Feb 08 10:39:05 AM UTC 25
Finished Feb 08 10:39:31 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807473735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3807473735
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.928618125
Short name T408
Test name
Test status
Simulation time 4985498409 ps
CPU time 22.68 seconds
Started Feb 08 10:38:49 AM UTC 25
Finished Feb 08 10:39:13 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928618125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.928618125
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.230559536
Short name T405
Test name
Test status
Simulation time 5956730998 ps
CPU time 25.7 seconds
Started Feb 08 10:37:38 AM UTC 25
Finished Feb 08 10:38:05 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230559536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.adc_ctrl_smoke.230559536
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.57043325
Short name T291
Test name
Test status
Simulation time 518999038778 ps
CPU time 701.5 seconds
Started Feb 08 10:39:32 AM UTC 25
Finished Feb 08 10:51:22 AM UTC 25
Peak memory 211628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57043325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.57043325
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.3047718189
Short name T413
Test name
Test status
Simulation time 422701680 ps
CPU time 1.87 seconds
Started Feb 08 10:41:29 AM UTC 25
Finished Feb 08 10:41:32 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047718189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3047718189
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2572251235
Short name T242
Test name
Test status
Simulation time 322597631135 ps
CPU time 255.48 seconds
Started Feb 08 10:40:44 AM UTC 25
Finished Feb 08 10:45:03 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572251235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2572251235
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1274673209
Short name T146
Test name
Test status
Simulation time 327192495205 ps
CPU time 227.95 seconds
Started Feb 08 10:40:03 AM UTC 25
Finished Feb 08 10:43:55 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274673209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1274673209
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1150337939
Short name T533
Test name
Test status
Simulation time 492873399336 ps
CPU time 1436.41 seconds
Started Feb 08 10:40:08 AM UTC 25
Finished Feb 08 11:04:20 AM UTC 25
Peak memory 212864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150337939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.1150337939
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.2269339783
Short name T257
Test name
Test status
Simulation time 487288478352 ps
CPU time 344.57 seconds
Started Feb 08 10:39:47 AM UTC 25
Finished Feb 08 10:45:37 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269339783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2269339783
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.802453457
Short name T422
Test name
Test status
Simulation time 163200111856 ps
CPU time 264.94 seconds
Started Feb 08 10:40:00 AM UTC 25
Finished Feb 08 10:44:29 AM UTC 25
Peak memory 211672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802453457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.802453457
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1012662791
Short name T164
Test name
Test status
Simulation time 372013667728 ps
CPU time 1033.76 seconds
Started Feb 08 10:40:10 AM UTC 25
Finished Feb 08 10:57:36 AM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012662791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.1012662791
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2913369333
Short name T432
Test name
Test status
Simulation time 187161778215 ps
CPU time 366.99 seconds
Started Feb 08 10:40:28 AM UTC 25
Finished Feb 08 10:46:41 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913369333 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.2913369333
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.3787077298
Short name T92
Test name
Test status
Simulation time 92820200029 ps
CPU time 473.68 seconds
Started Feb 08 10:41:09 AM UTC 25
Finished Feb 08 10:49:08 AM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787077298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3787077298
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.1999917963
Short name T418
Test name
Test status
Simulation time 31879679726 ps
CPU time 137.83 seconds
Started Feb 08 10:41:06 AM UTC 25
Finished Feb 08 10:43:26 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999917963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1999917963
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3858138240
Short name T411
Test name
Test status
Simulation time 3127518801 ps
CPU time 13.69 seconds
Started Feb 08 10:41:02 AM UTC 25
Finished Feb 08 10:41:17 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858138240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3858138240
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.596742193
Short name T186
Test name
Test status
Simulation time 6007342960 ps
CPU time 14.58 seconds
Started Feb 08 10:39:46 AM UTC 25
Finished Feb 08 10:40:03 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596742193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.adc_ctrl_smoke.596742193
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.3117983724
Short name T453
Test name
Test status
Simulation time 212066535041 ps
CPU time 625.13 seconds
Started Feb 08 10:41:18 AM UTC 25
Finished Feb 08 10:51:51 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117983724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.3117983724
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2784371457
Short name T87
Test name
Test status
Simulation time 540764176928 ps
CPU time 453.64 seconds
Started Feb 08 10:41:15 AM UTC 25
Finished Feb 08 10:48:54 AM UTC 25
Peak memory 222108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2784371457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_a
ll_with_rand_reset.2784371457
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2639562317
Short name T420
Test name
Test status
Simulation time 349865999 ps
CPU time 2.35 seconds
Started Feb 08 10:43:56 AM UTC 25
Finished Feb 08 10:44:00 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639562317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2639562317
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1406457867
Short name T147
Test name
Test status
Simulation time 343690205312 ps
CPU time 186.16 seconds
Started Feb 08 10:42:52 AM UTC 25
Finished Feb 08 10:46:01 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406457867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.1406457867
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.74759159
Short name T97
Test name
Test status
Simulation time 164284044954 ps
CPU time 450.2 seconds
Started Feb 08 10:42:15 AM UTC 25
Finished Feb 08 10:49:52 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74759159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.74759159
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3757024332
Short name T425
Test name
Test status
Simulation time 165511555111 ps
CPU time 187.9 seconds
Started Feb 08 10:42:18 AM UTC 25
Finished Feb 08 10:45:30 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757024332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.3757024332
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.4197973247
Short name T224
Test name
Test status
Simulation time 487617832792 ps
CPU time 1244.77 seconds
Started Feb 08 10:41:33 AM UTC 25
Finished Feb 08 11:02:31 AM UTC 25
Peak memory 212928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197973247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4197973247
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.2190810713
Short name T440
Test name
Test status
Simulation time 494262689707 ps
CPU time 382.71 seconds
Started Feb 08 10:42:00 AM UTC 25
Finished Feb 08 10:48:29 AM UTC 25
Peak memory 211552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190810713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.2190810713
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.3511123023
Short name T171
Test name
Test status
Simulation time 370002300251 ps
CPU time 1128.07 seconds
Started Feb 08 10:42:27 AM UTC 25
Finished Feb 08 11:01:28 AM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511123023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.3511123023
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.23827542
Short name T428
Test name
Test status
Simulation time 202786499663 ps
CPU time 184.83 seconds
Started Feb 08 10:42:44 AM UTC 25
Finished Feb 08 10:45:52 AM UTC 25
Peak memory 211552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23827542 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.23827542
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.3071981259
Short name T474
Test name
Test status
Simulation time 108240973227 ps
CPU time 755.58 seconds
Started Feb 08 10:43:29 AM UTC 25
Finished Feb 08 10:56:12 AM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071981259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3071981259
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1041123646
Short name T430
Test name
Test status
Simulation time 40948492124 ps
CPU time 169.96 seconds
Started Feb 08 10:43:27 AM UTC 25
Finished Feb 08 10:46:20 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041123646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1041123646
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1540751009
Short name T419
Test name
Test status
Simulation time 3239133590 ps
CPU time 2.42 seconds
Started Feb 08 10:43:24 AM UTC 25
Finished Feb 08 10:43:28 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540751009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1540751009
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1541198466
Short name T414
Test name
Test status
Simulation time 5827186648 ps
CPU time 26.18 seconds
Started Feb 08 10:41:31 AM UTC 25
Finished Feb 08 10:41:59 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541198466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1541198466
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.4070211985
Short name T348
Test name
Test status
Simulation time 320421272335 ps
CPU time 984.13 seconds
Started Feb 08 10:43:37 AM UTC 25
Finished Feb 08 11:00:12 AM UTC 25
Peak memory 212992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070211985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.4070211985
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2396633498
Short name T234
Test name
Test status
Simulation time 134616983086 ps
CPU time 138.01 seconds
Started Feb 08 10:43:29 AM UTC 25
Finished Feb 08 10:45:50 AM UTC 25
Peak memory 222240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2396633498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_a
ll_with_rand_reset.2396633498
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3130129299
Short name T427
Test name
Test status
Simulation time 514508291 ps
CPU time 1.41 seconds
Started Feb 08 10:45:45 AM UTC 25
Finished Feb 08 10:45:48 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130129299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3130129299
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3842224270
Short name T176
Test name
Test status
Simulation time 519112193300 ps
CPU time 639.39 seconds
Started Feb 08 10:44:59 AM UTC 25
Finished Feb 08 10:55:46 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842224270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.3842224270
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.1263852282
Short name T262
Test name
Test status
Simulation time 349502292021 ps
CPU time 889.89 seconds
Started Feb 08 10:45:04 AM UTC 25
Finished Feb 08 11:00:04 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263852282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1263852282
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.1431082839
Short name T337
Test name
Test status
Simulation time 160719865089 ps
CPU time 237.48 seconds
Started Feb 08 10:44:20 AM UTC 25
Finished Feb 08 10:48:21 AM UTC 25
Peak memory 211396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431082839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1431082839
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3179366228
Short name T434
Test name
Test status
Simulation time 164831733488 ps
CPU time 172.02 seconds
Started Feb 08 10:44:20 AM UTC 25
Finished Feb 08 10:47:15 AM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179366228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.3179366228
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2164127019
Short name T281
Test name
Test status
Simulation time 489753817884 ps
CPU time 271.14 seconds
Started Feb 08 10:44:08 AM UTC 25
Finished Feb 08 10:48:44 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164127019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2164127019
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1398797102
Short name T544
Test name
Test status
Simulation time 492886791173 ps
CPU time 1323 seconds
Started Feb 08 10:44:18 AM UTC 25
Finished Feb 08 11:06:34 AM UTC 25
Peak memory 212836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398797102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1398797102
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3719092931
Short name T341
Test name
Test status
Simulation time 163813094551 ps
CPU time 546.22 seconds
Started Feb 08 10:44:30 AM UTC 25
Finished Feb 08 10:53:43 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719092931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.3719092931
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3155138954
Short name T600
Test name
Test status
Simulation time 597355767122 ps
CPU time 1762.92 seconds
Started Feb 08 10:44:45 AM UTC 25
Finished Feb 08 11:14:27 AM UTC 25
Peak memory 212924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155138954 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.3155138954
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3511278407
Short name T482
Test name
Test status
Simulation time 108403341975 ps
CPU time 697.62 seconds
Started Feb 08 10:45:30 AM UTC 25
Finished Feb 08 10:57:16 AM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511278407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3511278407
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1383738825
Short name T426
Test name
Test status
Simulation time 23203977221 ps
CPU time 25.59 seconds
Started Feb 08 10:45:17 AM UTC 25
Finished Feb 08 10:45:44 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383738825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1383738825
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3981799835
Short name T424
Test name
Test status
Simulation time 3502762172 ps
CPU time 9.11 seconds
Started Feb 08 10:45:06 AM UTC 25
Finished Feb 08 10:45:16 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981799835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3981799835
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3656316740
Short name T421
Test name
Test status
Simulation time 5658716428 ps
CPU time 4.48 seconds
Started Feb 08 10:44:01 AM UTC 25
Finished Feb 08 10:44:07 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656316740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3656316740
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.4123786448
Short name T326
Test name
Test status
Simulation time 229342416383 ps
CPU time 351.53 seconds
Started Feb 08 10:45:43 AM UTC 25
Finished Feb 08 10:51:40 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123786448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.4123786448
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3308993409
Short name T436
Test name
Test status
Simulation time 308793342 ps
CPU time 1.24 seconds
Started Feb 08 10:47:56 AM UTC 25
Finished Feb 08 10:47:59 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308993409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3308993409
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1753865120
Short name T309
Test name
Test status
Simulation time 345475918873 ps
CPU time 718.01 seconds
Started Feb 08 10:46:21 AM UTC 25
Finished Feb 08 10:58:28 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753865120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.1753865120
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1463184655
Short name T435
Test name
Test status
Simulation time 171347379027 ps
CPU time 111.32 seconds
Started Feb 08 10:46:02 AM UTC 25
Finished Feb 08 10:47:55 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463184655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.1463184655
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.974325922
Short name T443
Test name
Test status
Simulation time 328267686450 ps
CPU time 286.53 seconds
Started Feb 08 10:45:50 AM UTC 25
Finished Feb 08 10:50:41 AM UTC 25
Peak memory 211772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974325922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.974325922
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.2037872690
Short name T449
Test name
Test status
Simulation time 327602355007 ps
CPU time 319.66 seconds
Started Feb 08 10:45:54 AM UTC 25
Finished Feb 08 10:51:18 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037872690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.2037872690
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1103444363
Short name T289
Test name
Test status
Simulation time 175626521675 ps
CPU time 111.16 seconds
Started Feb 08 10:46:07 AM UTC 25
Finished Feb 08 10:48:00 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103444363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.1103444363
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.915058764
Short name T454
Test name
Test status
Simulation time 202290707750 ps
CPU time 345.08 seconds
Started Feb 08 10:46:19 AM UTC 25
Finished Feb 08 10:52:09 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915058764 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.915058764
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.779694315
Short name T362
Test name
Test status
Simulation time 92392284015 ps
CPU time 454.77 seconds
Started Feb 08 10:46:50 AM UTC 25
Finished Feb 08 10:54:31 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779694315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.779694315
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1499207878
Short name T439
Test name
Test status
Simulation time 40509552628 ps
CPU time 91.09 seconds
Started Feb 08 10:46:42 AM UTC 25
Finished Feb 08 10:48:16 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499207878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1499207878
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1057498120
Short name T433
Test name
Test status
Simulation time 3429300747 ps
CPU time 15.55 seconds
Started Feb 08 10:46:32 AM UTC 25
Finished Feb 08 10:46:49 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057498120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1057498120
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.587424438
Short name T429
Test name
Test status
Simulation time 6019948515 ps
CPU time 14.9 seconds
Started Feb 08 10:45:49 AM UTC 25
Finished Feb 08 10:46:06 AM UTC 25
Peak memory 211612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587424438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.adc_ctrl_smoke.587424438
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.3098374877
Short name T327
Test name
Test status
Simulation time 557399160245 ps
CPU time 1538.23 seconds
Started Feb 08 10:47:16 AM UTC 25
Finished Feb 08 11:13:10 AM UTC 25
Peak memory 222980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098374877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.3098374877
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.3032831759
Short name T94
Test name
Test status
Simulation time 490185800 ps
CPU time 2.21 seconds
Started Feb 08 10:49:10 AM UTC 25
Finished Feb 08 10:49:14 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032831759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3032831759
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.1923062148
Short name T318
Test name
Test status
Simulation time 380556013262 ps
CPU time 487.31 seconds
Started Feb 08 10:48:22 AM UTC 25
Finished Feb 08 10:56:35 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923062148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.1923062148
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.1437247693
Short name T286
Test name
Test status
Simulation time 350557931370 ps
CPU time 202.67 seconds
Started Feb 08 10:48:30 AM UTC 25
Finished Feb 08 10:51:56 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437247693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1437247693
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1354563746
Short name T260
Test name
Test status
Simulation time 481344691581 ps
CPU time 1617.27 seconds
Started Feb 08 10:48:13 AM UTC 25
Finished Feb 08 11:15:27 AM UTC 25
Peak memory 212592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354563746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1354563746
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2027585910
Short name T603
Test name
Test status
Simulation time 482359111618 ps
CPU time 1572.37 seconds
Started Feb 08 10:48:14 AM UTC 25
Finished Feb 08 11:14:43 AM UTC 25
Peak memory 212736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027585910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.2027585910
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3211133142
Short name T460
Test name
Test status
Simulation time 165792056680 ps
CPU time 302.75 seconds
Started Feb 08 10:48:01 AM UTC 25
Finished Feb 08 10:53:09 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211133142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3211133142
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2611784154
Short name T447
Test name
Test status
Simulation time 166440550227 ps
CPU time 173.66 seconds
Started Feb 08 10:48:05 AM UTC 25
Finished Feb 08 10:51:02 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611784154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.2611784154
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.395475658
Short name T442
Test name
Test status
Simulation time 188539921597 ps
CPU time 129.08 seconds
Started Feb 08 10:48:17 AM UTC 25
Finished Feb 08 10:50:28 AM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395475658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.395475658
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.668006187
Short name T590
Test name
Test status
Simulation time 598751102701 ps
CPU time 1493.7 seconds
Started Feb 08 10:48:18 AM UTC 25
Finished Feb 08 11:13:26 AM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668006187 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.668006187
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1772540623
Short name T212
Test name
Test status
Simulation time 96738115484 ps
CPU time 487.52 seconds
Started Feb 08 10:48:55 AM UTC 25
Finished Feb 08 10:57:08 AM UTC 25
Peak memory 211908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772540623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1772540623
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.64992615
Short name T441
Test name
Test status
Simulation time 43632651230 ps
CPU time 96.28 seconds
Started Feb 08 10:48:44 AM UTC 25
Finished Feb 08 10:50:23 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64992615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.64992615
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1118627763
Short name T91
Test name
Test status
Simulation time 4228859426 ps
CPU time 20.76 seconds
Started Feb 08 10:48:32 AM UTC 25
Finished Feb 08 10:48:55 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118627763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1118627763
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1551745272
Short name T437
Test name
Test status
Simulation time 5761313206 ps
CPU time 4.33 seconds
Started Feb 08 10:47:59 AM UTC 25
Finished Feb 08 10:48:05 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551745272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1551745272
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.1581465163
Short name T274
Test name
Test status
Simulation time 500539877673 ps
CPU time 331.11 seconds
Started Feb 08 10:49:09 AM UTC 25
Finished Feb 08 10:54:45 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581465163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.1581465163
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.939441320
Short name T32
Test name
Test status
Simulation time 50660109513 ps
CPU time 235.88 seconds
Started Feb 08 10:48:56 AM UTC 25
Finished Feb 08 10:52:56 AM UTC 25
Peak memory 222036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=939441320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_al
l_with_rand_reset.939441320
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2569621140
Short name T54
Test name
Test status
Simulation time 430506645 ps
CPU time 2.84 seconds
Started Feb 08 10:20:37 AM UTC 25
Finished Feb 08 10:20:41 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569621140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2569621140
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.2027155910
Short name T57
Test name
Test status
Simulation time 170523378983 ps
CPU time 287.06 seconds
Started Feb 08 10:20:26 AM UTC 25
Finished Feb 08 10:25:17 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027155910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.2027155910
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3037516167
Short name T255
Test name
Test status
Simulation time 327258266887 ps
CPU time 1009.78 seconds
Started Feb 08 10:20:26 AM UTC 25
Finished Feb 08 10:37:27 AM UTC 25
Peak memory 212592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037516167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3037516167
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.3463566755
Short name T14
Test name
Test status
Simulation time 168632617787 ps
CPU time 150.52 seconds
Started Feb 08 10:20:20 AM UTC 25
Finished Feb 08 10:22:53 AM UTC 25
Peak memory 211356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463566755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3463566755
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1004574129
Short name T151
Test name
Test status
Simulation time 165499606598 ps
CPU time 331.25 seconds
Started Feb 08 10:20:20 AM UTC 25
Finished Feb 08 10:25:56 AM UTC 25
Peak memory 211668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004574129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.1004574129
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.397727725
Short name T225
Test name
Test status
Simulation time 491813553735 ps
CPU time 605.83 seconds
Started Feb 08 10:20:18 AM UTC 25
Finished Feb 08 10:30:31 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397727725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.397727725
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2306769423
Short name T13
Test name
Test status
Simulation time 159298059904 ps
CPU time 115.78 seconds
Started Feb 08 10:20:19 AM UTC 25
Finished Feb 08 10:22:17 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306769423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.2306769423
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.344482995
Short name T56
Test name
Test status
Simulation time 348695764689 ps
CPU time 275.98 seconds
Started Feb 08 10:20:23 AM UTC 25
Finished Feb 08 10:25:03 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344482995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.344482995
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.217367562
Short name T63
Test name
Test status
Simulation time 76870417990 ps
CPU time 636.73 seconds
Started Feb 08 10:20:30 AM UTC 25
Finished Feb 08 10:31:15 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217367562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.217367562
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2555297938
Short name T25
Test name
Test status
Simulation time 32362494281 ps
CPU time 111.96 seconds
Started Feb 08 10:20:29 AM UTC 25
Finished Feb 08 10:22:24 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555297938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2555297938
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1273213528
Short name T8
Test name
Test status
Simulation time 4994011177 ps
CPU time 6.56 seconds
Started Feb 08 10:20:27 AM UTC 25
Finished Feb 08 10:20:35 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273213528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1273213528
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.241256148
Short name T55
Test name
Test status
Simulation time 4099429795 ps
CPU time 5.08 seconds
Started Feb 08 10:20:37 AM UTC 25
Finished Feb 08 10:20:43 AM UTC 25
Peak memory 244020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241256148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.241256148
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2111383950
Short name T137
Test name
Test status
Simulation time 341218448047 ps
CPU time 556.36 seconds
Started Feb 08 10:20:35 AM UTC 25
Finished Feb 08 10:29:59 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111383950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.2111383950
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.1651101740
Short name T448
Test name
Test status
Simulation time 514446211 ps
CPU time 1.46 seconds
Started Feb 08 10:51:03 AM UTC 25
Finished Feb 08 10:51:06 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651101740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1651101740
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.747401529
Short name T235
Test name
Test status
Simulation time 352703740111 ps
CPU time 219.35 seconds
Started Feb 08 10:50:42 AM UTC 25
Finished Feb 08 10:54:25 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747401529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.747401529
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.1998437375
Short name T489
Test name
Test status
Simulation time 167766323878 ps
CPU time 475.62 seconds
Started Feb 08 10:49:52 AM UTC 25
Finished Feb 08 10:57:55 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998437375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1998437375
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.973804983
Short name T626
Test name
Test status
Simulation time 491752475105 ps
CPU time 1613.25 seconds
Started Feb 08 10:50:12 AM UTC 25
Finished Feb 08 11:17:22 AM UTC 25
Peak memory 212516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973804983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.973804983
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.45582641
Short name T536
Test name
Test status
Simulation time 328503579037 ps
CPU time 932.07 seconds
Started Feb 08 10:49:21 AM UTC 25
Finished Feb 08 11:05:03 AM UTC 25
Peak memory 212612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45582641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.45582641
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.2533220673
Short name T480
Test name
Test status
Simulation time 331607429453 ps
CPU time 438.49 seconds
Started Feb 08 10:49:46 AM UTC 25
Finished Feb 08 10:57:11 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533220673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.2533220673
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2946396623
Short name T333
Test name
Test status
Simulation time 224398581882 ps
CPU time 452.6 seconds
Started Feb 08 10:50:12 AM UTC 25
Finished Feb 08 10:57:50 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946396623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.2946396623
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.343375104
Short name T504
Test name
Test status
Simulation time 616695134625 ps
CPU time 583.62 seconds
Started Feb 08 10:50:24 AM UTC 25
Finished Feb 08 11:00:15 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343375104 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.343375104
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.86040430
Short name T560
Test name
Test status
Simulation time 141875062416 ps
CPU time 1064.66 seconds
Started Feb 08 10:50:46 AM UTC 25
Finished Feb 08 11:08:42 AM UTC 25
Peak memory 213140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86040430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.86040430
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.2589751420
Short name T456
Test name
Test status
Simulation time 39726508900 ps
CPU time 103.12 seconds
Started Feb 08 10:50:45 AM UTC 25
Finished Feb 08 10:52:31 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589751420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2589751420
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.1921334093
Short name T446
Test name
Test status
Simulation time 3458254631 ps
CPU time 8.1 seconds
Started Feb 08 10:50:43 AM UTC 25
Finished Feb 08 10:50:53 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921334093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1921334093
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.1996921529
Short name T95
Test name
Test status
Simulation time 6210894662 ps
CPU time 5.28 seconds
Started Feb 08 10:49:14 AM UTC 25
Finished Feb 08 10:49:21 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996921529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1996921529
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3064063884
Short name T340
Test name
Test status
Simulation time 169865670541 ps
CPU time 294.52 seconds
Started Feb 08 10:51:01 AM UTC 25
Finished Feb 08 10:56:00 AM UTC 25
Peak memory 211508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064063884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.3064063884
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.859942667
Short name T88
Test name
Test status
Simulation time 15934951198 ps
CPU time 35.61 seconds
Started Feb 08 10:50:54 AM UTC 25
Finished Feb 08 10:51:31 AM UTC 25
Peak memory 221856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=859942667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_al
l_with_rand_reset.859942667
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.3047538032
Short name T457
Test name
Test status
Simulation time 366077362 ps
CPU time 2.46 seconds
Started Feb 08 10:52:31 AM UTC 25
Finished Feb 08 10:52:35 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047538032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3047538032
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1713766957
Short name T267
Test name
Test status
Simulation time 164268510224 ps
CPU time 137.68 seconds
Started Feb 08 10:51:41 AM UTC 25
Finished Feb 08 10:54:01 AM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713766957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.1713766957
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1996416661
Short name T335
Test name
Test status
Simulation time 174647607942 ps
CPU time 325.43 seconds
Started Feb 08 10:51:52 AM UTC 25
Finished Feb 08 10:57:22 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996416661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1996416661
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.1322687570
Short name T462
Test name
Test status
Simulation time 165488729134 ps
CPU time 125.12 seconds
Started Feb 08 10:51:23 AM UTC 25
Finished Feb 08 10:53:31 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322687570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1322687570
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4078277654
Short name T478
Test name
Test status
Simulation time 316257806859 ps
CPU time 320.91 seconds
Started Feb 08 10:51:29 AM UTC 25
Finished Feb 08 10:56:54 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078277654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.4078277654
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.960411981
Short name T484
Test name
Test status
Simulation time 322985331947 ps
CPU time 352.54 seconds
Started Feb 08 10:51:18 AM UTC 25
Finished Feb 08 10:57:16 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960411981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.960411981
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.298187328
Short name T461
Test name
Test status
Simulation time 489931198454 ps
CPU time 109.01 seconds
Started Feb 08 10:51:22 AM UTC 25
Finished Feb 08 10:53:14 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298187328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.298187328
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.1940901001
Short name T493
Test name
Test status
Simulation time 348075607390 ps
CPU time 413.23 seconds
Started Feb 08 10:51:33 AM UTC 25
Finished Feb 08 10:58:31 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940901001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.1940901001
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1606990378
Short name T472
Test name
Test status
Simulation time 606451857033 ps
CPU time 261.17 seconds
Started Feb 08 10:51:35 AM UTC 25
Finished Feb 08 10:56:00 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606990378 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.1606990378
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2985422657
Short name T516
Test name
Test status
Simulation time 72558771944 ps
CPU time 570.69 seconds
Started Feb 08 10:52:12 AM UTC 25
Finished Feb 08 11:01:49 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985422657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2985422657
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.1768157800
Short name T459
Test name
Test status
Simulation time 42345014161 ps
CPU time 47.98 seconds
Started Feb 08 10:52:10 AM UTC 25
Finished Feb 08 10:53:00 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768157800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1768157800
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.1627353305
Short name T455
Test name
Test status
Simulation time 2836146559 ps
CPU time 14.59 seconds
Started Feb 08 10:51:57 AM UTC 25
Finished Feb 08 10:52:13 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627353305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1627353305
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.1215903014
Short name T450
Test name
Test status
Simulation time 5654615093 ps
CPU time 13.05 seconds
Started Feb 08 10:51:07 AM UTC 25
Finished Feb 08 10:51:22 AM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215903014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1215903014
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2497592632
Short name T550
Test name
Test status
Simulation time 567901294329 ps
CPU time 882.42 seconds
Started Feb 08 10:52:23 AM UTC 25
Finished Feb 08 11:07:15 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497592632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.2497592632
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.574101708
Short name T525
Test name
Test status
Simulation time 219649733908 ps
CPU time 631.41 seconds
Started Feb 08 10:52:14 AM UTC 25
Finished Feb 08 11:02:54 AM UTC 25
Peak memory 222304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=574101708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_al
l_with_rand_reset.574101708
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.2249447659
Short name T465
Test name
Test status
Simulation time 383105373 ps
CPU time 1.67 seconds
Started Feb 08 10:54:02 AM UTC 25
Finished Feb 08 10:54:05 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249447659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2249447659
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2924408324
Short name T290
Test name
Test status
Simulation time 162844122478 ps
CPU time 150.37 seconds
Started Feb 08 10:53:15 AM UTC 25
Finished Feb 08 10:55:48 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924408324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.2924408324
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1498779946
Short name T513
Test name
Test status
Simulation time 178693653485 ps
CPU time 473.71 seconds
Started Feb 08 10:53:16 AM UTC 25
Finished Feb 08 11:01:15 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498779946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1498779946
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.1561020750
Short name T342
Test name
Test status
Simulation time 330168704414 ps
CPU time 660.14 seconds
Started Feb 08 10:52:41 AM UTC 25
Finished Feb 08 11:03:50 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561020750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1561020750
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.761533463
Short name T496
Test name
Test status
Simulation time 333987483432 ps
CPU time 347.64 seconds
Started Feb 08 10:52:56 AM UTC 25
Finished Feb 08 10:58:49 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761533463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.761533463
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.2570565173
Short name T547
Test name
Test status
Simulation time 327279325534 ps
CPU time 864.93 seconds
Started Feb 08 10:52:36 AM UTC 25
Finished Feb 08 11:07:11 AM UTC 25
Peak memory 212672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570565173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2570565173
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.1645227686
Short name T473
Test name
Test status
Simulation time 484282306483 ps
CPU time 197.76 seconds
Started Feb 08 10:52:41 AM UTC 25
Finished Feb 08 10:56:02 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645227686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.1645227686
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.510789600
Short name T494
Test name
Test status
Simulation time 578661084114 ps
CPU time 328.51 seconds
Started Feb 08 10:53:01 AM UTC 25
Finished Feb 08 10:58:34 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510789600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.510789600
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2474357382
Short name T520
Test name
Test status
Simulation time 203219145470 ps
CPU time 531.91 seconds
Started Feb 08 10:53:10 AM UTC 25
Finished Feb 08 11:02:09 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474357382 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.2474357382
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.2213852839
Short name T209
Test name
Test status
Simulation time 61812292475 ps
CPU time 314.01 seconds
Started Feb 08 10:53:38 AM UTC 25
Finished Feb 08 10:58:56 AM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213852839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2213852839
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.3330300250
Short name T464
Test name
Test status
Simulation time 27196005922 ps
CPU time 22.26 seconds
Started Feb 08 10:53:35 AM UTC 25
Finished Feb 08 10:53:59 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330300250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3330300250
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1551258486
Short name T463
Test name
Test status
Simulation time 3321585721 ps
CPU time 3.72 seconds
Started Feb 08 10:53:32 AM UTC 25
Finished Feb 08 10:53:37 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551258486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1551258486
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.134361669
Short name T458
Test name
Test status
Simulation time 5956221312 ps
CPU time 5.88 seconds
Started Feb 08 10:52:33 AM UTC 25
Finished Feb 08 10:52:41 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134361669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.adc_ctrl_smoke.134361669
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.2040743990
Short name T467
Test name
Test status
Simulation time 8978431570 ps
CPU time 21.9 seconds
Started Feb 08 10:53:59 AM UTC 25
Finished Feb 08 10:54:23 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040743990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.2040743990
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2332148780
Short name T45
Test name
Test status
Simulation time 209585208028 ps
CPU time 65.72 seconds
Started Feb 08 10:53:44 AM UTC 25
Finished Feb 08 10:54:52 AM UTC 25
Peak memory 222112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2332148780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_a
ll_with_rand_reset.2332148780
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.440094093
Short name T471
Test name
Test status
Simulation time 507916440 ps
CPU time 1.2 seconds
Started Feb 08 10:55:47 AM UTC 25
Finished Feb 08 10:55:50 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440094093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.440094093
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1724992645
Short name T331
Test name
Test status
Simulation time 492341389456 ps
CPU time 342.81 seconds
Started Feb 08 10:54:53 AM UTC 25
Finished Feb 08 11:00:41 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724992645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1724992645
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1877986516
Short name T485
Test name
Test status
Simulation time 164687483779 ps
CPU time 170.56 seconds
Started Feb 08 10:54:23 AM UTC 25
Finished Feb 08 10:57:18 AM UTC 25
Peak memory 211780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877986516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1877986516
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2133629125
Short name T483
Test name
Test status
Simulation time 326958356871 ps
CPU time 165.15 seconds
Started Feb 08 10:54:26 AM UTC 25
Finished Feb 08 10:57:16 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133629125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.2133629125
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.3270322358
Short name T556
Test name
Test status
Simulation time 325116296379 ps
CPU time 791.77 seconds
Started Feb 08 10:54:18 AM UTC 25
Finished Feb 08 11:07:40 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270322358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3270322358
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.266482359
Short name T591
Test name
Test status
Simulation time 488860775942 ps
CPU time 1137.64 seconds
Started Feb 08 10:54:21 AM UTC 25
Finished Feb 08 11:13:31 AM UTC 25
Peak memory 212580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266482359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.266482359
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.2243028946
Short name T264
Test name
Test status
Simulation time 525538983381 ps
CPU time 258.86 seconds
Started Feb 08 10:54:32 AM UTC 25
Finished Feb 08 10:58:55 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243028946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.2243028946
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.437686858
Short name T524
Test name
Test status
Simulation time 202878719219 ps
CPU time 472.87 seconds
Started Feb 08 10:54:33 AM UTC 25
Finished Feb 08 11:02:32 AM UTC 25
Peak memory 211752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437686858 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.437686858
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.619672181
Short name T218
Test name
Test status
Simulation time 137657350164 ps
CPU time 924.9 seconds
Started Feb 08 10:55:23 AM UTC 25
Finished Feb 08 11:10:58 AM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619672181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.619672181
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2001533255
Short name T477
Test name
Test status
Simulation time 46224719590 ps
CPU time 88.8 seconds
Started Feb 08 10:55:22 AM UTC 25
Finished Feb 08 10:56:53 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001533255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2001533255
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.2752018692
Short name T469
Test name
Test status
Simulation time 4851227709 ps
CPU time 21.83 seconds
Started Feb 08 10:54:57 AM UTC 25
Finished Feb 08 10:55:21 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752018692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2752018692
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.659959322
Short name T466
Test name
Test status
Simulation time 5582794666 ps
CPU time 10.08 seconds
Started Feb 08 10:54:06 AM UTC 25
Finished Feb 08 10:54:18 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659959322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.adc_ctrl_smoke.659959322
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2793182252
Short name T624
Test name
Test status
Simulation time 494710581398 ps
CPU time 1272.12 seconds
Started Feb 08 10:55:47 AM UTC 25
Finished Feb 08 11:17:13 AM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793182252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.2793182252
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.3993831172
Short name T481
Test name
Test status
Simulation time 332173059 ps
CPU time 1.62 seconds
Started Feb 08 10:57:09 AM UTC 25
Finished Feb 08 10:57:12 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993831172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3993831172
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1734910192
Short name T300
Test name
Test status
Simulation time 344853821507 ps
CPU time 263.42 seconds
Started Feb 08 10:56:14 AM UTC 25
Finished Feb 08 11:00:41 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734910192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.1734910192
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.3986500501
Short name T198
Test name
Test status
Simulation time 341490797635 ps
CPU time 168.13 seconds
Started Feb 08 10:56:18 AM UTC 25
Finished Feb 08 10:59:09 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986500501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3986500501
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.3621837557
Short name T199
Test name
Test status
Simulation time 167433536550 ps
CPU time 211.56 seconds
Started Feb 08 10:56:00 AM UTC 25
Finished Feb 08 10:59:36 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621837557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3621837557
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3818637685
Short name T479
Test name
Test status
Simulation time 167952959979 ps
CPU time 59.46 seconds
Started Feb 08 10:56:00 AM UTC 25
Finished Feb 08 10:57:02 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818637685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.3818637685
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.1729632451
Short name T656
Test name
Test status
Simulation time 490911207191 ps
CPU time 1581.02 seconds
Started Feb 08 10:55:50 AM UTC 25
Finished Feb 08 11:22:29 AM UTC 25
Peak memory 212616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729632451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1729632451
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2820107770
Short name T523
Test name
Test status
Simulation time 162622522469 ps
CPU time 387.61 seconds
Started Feb 08 10:55:55 AM UTC 25
Finished Feb 08 11:02:28 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820107770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.2820107770
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.2354695827
Short name T497
Test name
Test status
Simulation time 169639541706 ps
CPU time 192.6 seconds
Started Feb 08 10:56:04 AM UTC 25
Finished Feb 08 10:59:20 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354695827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.2354695827
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.25436139
Short name T487
Test name
Test status
Simulation time 208237528529 ps
CPU time 88.15 seconds
Started Feb 08 10:56:09 AM UTC 25
Finished Feb 08 10:57:39 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25436139 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.25436139
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2529021382
Short name T358
Test name
Test status
Simulation time 118781445965 ps
CPU time 515.52 seconds
Started Feb 08 10:56:54 AM UTC 25
Finished Feb 08 11:05:36 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529021382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2529021382
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1873540915
Short name T486
Test name
Test status
Simulation time 31771755454 ps
CPU time 50.6 seconds
Started Feb 08 10:56:43 AM UTC 25
Finished Feb 08 10:57:35 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873540915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1873540915
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.922933606
Short name T476
Test name
Test status
Simulation time 3031217586 ps
CPU time 4.44 seconds
Started Feb 08 10:56:36 AM UTC 25
Finished Feb 08 10:56:42 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922933606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.922933606
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.3710280239
Short name T475
Test name
Test status
Simulation time 5657410051 ps
CPU time 27.25 seconds
Started Feb 08 10:55:48 AM UTC 25
Finished Feb 08 10:56:17 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710280239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3710280239
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3558892761
Short name T499
Test name
Test status
Simulation time 68757878861 ps
CPU time 161.58 seconds
Started Feb 08 10:56:55 AM UTC 25
Finished Feb 08 10:59:40 AM UTC 25
Peak memory 223744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3558892761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_a
ll_with_rand_reset.3558892761
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2663866731
Short name T492
Test name
Test status
Simulation time 411960017 ps
CPU time 1.31 seconds
Started Feb 08 10:58:23 AM UTC 25
Finished Feb 08 10:58:26 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663866731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2663866731
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.1907230970
Short name T505
Test name
Test status
Simulation time 188317041884 ps
CPU time 165.76 seconds
Started Feb 08 10:57:37 AM UTC 25
Finished Feb 08 11:00:25 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907230970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.1907230970
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.1284557503
Short name T507
Test name
Test status
Simulation time 196043472083 ps
CPU time 187.13 seconds
Started Feb 08 10:57:37 AM UTC 25
Finished Feb 08 11:00:47 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284557503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1284557503
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.3386450374
Short name T172
Test name
Test status
Simulation time 167741520380 ps
CPU time 250.91 seconds
Started Feb 08 10:57:16 AM UTC 25
Finished Feb 08 11:01:32 AM UTC 25
Peak memory 211520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386450374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3386450374
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1676436747
Short name T534
Test name
Test status
Simulation time 166168370480 ps
CPU time 421.53 seconds
Started Feb 08 10:57:16 AM UTC 25
Finished Feb 08 11:04:24 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676436747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.1676436747
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.4249716552
Short name T676
Test name
Test status
Simulation time 486970191905 ps
CPU time 1659.18 seconds
Started Feb 08 10:57:13 AM UTC 25
Finished Feb 08 11:25:11 AM UTC 25
Peak memory 212864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249716552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4249716552
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1086752236
Short name T549
Test name
Test status
Simulation time 164988686800 ps
CPU time 588.87 seconds
Started Feb 08 10:57:16 AM UTC 25
Finished Feb 08 11:07:13 AM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086752236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.1086752236
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1635122940
Short name T535
Test name
Test status
Simulation time 166835369094 ps
CPU time 454.85 seconds
Started Feb 08 10:57:19 AM UTC 25
Finished Feb 08 11:05:00 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635122940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.1635122940
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3519355853
Short name T584
Test name
Test status
Simulation time 617208199836 ps
CPU time 880.01 seconds
Started Feb 08 10:57:22 AM UTC 25
Finished Feb 08 11:12:13 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519355853 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.3519355853
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.2609950234
Short name T216
Test name
Test status
Simulation time 107840235986 ps
CPU time 653.16 seconds
Started Feb 08 10:57:51 AM UTC 25
Finished Feb 08 11:08:52 AM UTC 25
Peak memory 211908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609950234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2609950234
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2388511961
Short name T491
Test name
Test status
Simulation time 36883257473 ps
CPU time 37.41 seconds
Started Feb 08 10:57:43 AM UTC 25
Finished Feb 08 10:58:22 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388511961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2388511961
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1984263136
Short name T490
Test name
Test status
Simulation time 4592340802 ps
CPU time 21.73 seconds
Started Feb 08 10:57:40 AM UTC 25
Finished Feb 08 10:58:03 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984263136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1984263136
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.3304111456
Short name T488
Test name
Test status
Simulation time 6075025489 ps
CPU time 28.37 seconds
Started Feb 08 10:57:11 AM UTC 25
Finished Feb 08 10:57:42 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304111456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3304111456
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1648720145
Short name T48
Test name
Test status
Simulation time 202004519432 ps
CPU time 158.13 seconds
Started Feb 08 10:58:04 AM UTC 25
Finished Feb 08 11:00:45 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648720145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.1648720145
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.3535834649
Short name T500
Test name
Test status
Simulation time 503748031 ps
CPU time 1.54 seconds
Started Feb 08 10:59:40 AM UTC 25
Finished Feb 08 10:59:43 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535834649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3535834649
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3714727265
Short name T276
Test name
Test status
Simulation time 370408437403 ps
CPU time 1115.43 seconds
Started Feb 08 10:58:55 AM UTC 25
Finished Feb 08 11:17:44 AM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714727265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.3714727265
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.863095953
Short name T528
Test name
Test status
Simulation time 188823522342 ps
CPU time 267.55 seconds
Started Feb 08 10:58:57 AM UTC 25
Finished Feb 08 11:03:28 AM UTC 25
Peak memory 211612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863095953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.863095953
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.458307175
Short name T542
Test name
Test status
Simulation time 165565774682 ps
CPU time 462.89 seconds
Started Feb 08 10:58:34 AM UTC 25
Finished Feb 08 11:06:23 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458307175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.458307175
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3421242900
Short name T503
Test name
Test status
Simulation time 324892427485 ps
CPU time 81.15 seconds
Started Feb 08 10:58:36 AM UTC 25
Finished Feb 08 11:00:00 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421242900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.3421242900
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.2990534177
Short name T314
Test name
Test status
Simulation time 494848771751 ps
CPU time 493.56 seconds
Started Feb 08 10:58:29 AM UTC 25
Finished Feb 08 11:06:49 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990534177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2990534177
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.3748302256
Short name T501
Test name
Test status
Simulation time 165950397717 ps
CPU time 70.11 seconds
Started Feb 08 10:58:32 AM UTC 25
Finished Feb 08 10:59:44 AM UTC 25
Peak memory 211660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748302256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.3748302256
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.942928432
Short name T703
Test name
Test status
Simulation time 600352131341 ps
CPU time 1805.35 seconds
Started Feb 08 10:58:50 AM UTC 25
Finished Feb 08 11:29:15 AM UTC 25
Peak memory 212656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942928432 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.942928432
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.58573595
Short name T597
Test name
Test status
Simulation time 114466380199 ps
CPU time 865.73 seconds
Started Feb 08 10:59:25 AM UTC 25
Finished Feb 08 11:14:00 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58573595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.58573595
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.221119782
Short name T506
Test name
Test status
Simulation time 21535018453 ps
CPU time 83.43 seconds
Started Feb 08 10:59:21 AM UTC 25
Finished Feb 08 11:00:46 AM UTC 25
Peak memory 211620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221119782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.221119782
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1780015437
Short name T498
Test name
Test status
Simulation time 4997811789 ps
CPU time 12.83 seconds
Started Feb 08 10:59:10 AM UTC 25
Finished Feb 08 10:59:24 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780015437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1780015437
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.3831525102
Short name T495
Test name
Test status
Simulation time 6022904692 ps
CPU time 7.63 seconds
Started Feb 08 10:58:26 AM UTC 25
Finished Feb 08 10:58:35 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831525102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3831525102
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.280798721
Short name T518
Test name
Test status
Simulation time 327021709269 ps
CPU time 142.47 seconds
Started Feb 08 10:59:37 AM UTC 25
Finished Feb 08 11:02:02 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280798721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.280798721
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.121492091
Short name T100
Test name
Test status
Simulation time 176112993026 ps
CPU time 142.2 seconds
Started Feb 08 10:59:34 AM UTC 25
Finished Feb 08 11:01:59 AM UTC 25
Peak memory 222112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=121492091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_al
l_with_rand_reset.121492091
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.1316643697
Short name T510
Test name
Test status
Simulation time 619931631 ps
CPU time 1.06 seconds
Started Feb 08 11:00:49 AM UTC 25
Finished Feb 08 11:00:52 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316643697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1316643697
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1810067865
Short name T514
Test name
Test status
Simulation time 201512222277 ps
CPU time 46.83 seconds
Started Feb 08 11:00:35 AM UTC 25
Finished Feb 08 11:01:26 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810067865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.1810067865
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.75209190
Short name T526
Test name
Test status
Simulation time 168719401846 ps
CPU time 133.96 seconds
Started Feb 08 11:00:43 AM UTC 25
Finished Feb 08 11:03:00 AM UTC 25
Peak memory 211080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75209190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.75209190
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.878627183
Short name T279
Test name
Test status
Simulation time 325661763841 ps
CPU time 824.69 seconds
Started Feb 08 11:00:00 AM UTC 25
Finished Feb 08 11:14:28 AM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878627183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.878627183
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1936132847
Short name T613
Test name
Test status
Simulation time 333935264721 ps
CPU time 891.29 seconds
Started Feb 08 11:00:25 AM UTC 25
Finished Feb 08 11:15:38 AM UTC 25
Peak memory 212576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936132847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.1936132847
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2381345733
Short name T568
Test name
Test status
Simulation time 328950920660 ps
CPU time 604.96 seconds
Started Feb 08 10:59:45 AM UTC 25
Finished Feb 08 11:09:58 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381345733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2381345733
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.630948477
Short name T508
Test name
Test status
Simulation time 166318987245 ps
CPU time 55.68 seconds
Started Feb 08 10:59:50 AM UTC 25
Finished Feb 08 11:00:48 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630948477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.630948477
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1857547249
Short name T541
Test name
Test status
Simulation time 353321973381 ps
CPU time 337.21 seconds
Started Feb 08 11:00:33 AM UTC 25
Finished Feb 08 11:06:18 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857547249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.1857547249
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3643546322
Short name T530
Test name
Test status
Simulation time 196132880578 ps
CPU time 183.67 seconds
Started Feb 08 11:00:35 AM UTC 25
Finished Feb 08 11:03:44 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643546322 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.3643546322
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.445032488
Short name T545
Test name
Test status
Simulation time 83492111175 ps
CPU time 353.51 seconds
Started Feb 08 11:00:47 AM UTC 25
Finished Feb 08 11:06:45 AM UTC 25
Peak memory 211980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445032488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.445032488
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.1201116669
Short name T511
Test name
Test status
Simulation time 21413111277 ps
CPU time 17.28 seconds
Started Feb 08 11:00:47 AM UTC 25
Finished Feb 08 11:01:06 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201116669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1201116669
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.3509649994
Short name T509
Test name
Test status
Simulation time 4277519577 ps
CPU time 5.14 seconds
Started Feb 08 11:00:43 AM UTC 25
Finished Feb 08 11:00:50 AM UTC 25
Peak memory 211084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509649994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3509649994
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.3519996969
Short name T502
Test name
Test status
Simulation time 6117605408 ps
CPU time 4.87 seconds
Started Feb 08 10:59:43 AM UTC 25
Finished Feb 08 10:59:49 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519996969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3519996969
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.1367504903
Short name T564
Test name
Test status
Simulation time 200575072062 ps
CPU time 520.16 seconds
Started Feb 08 11:00:49 AM UTC 25
Finished Feb 08 11:09:36 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367504903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.1367504903
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3994754438
Short name T109
Test name
Test status
Simulation time 165692044388 ps
CPU time 788.08 seconds
Started Feb 08 11:00:47 AM UTC 25
Finished Feb 08 11:14:05 AM UTC 25
Peak memory 222312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3994754438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_a
ll_with_rand_reset.3994754438
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1730109033
Short name T519
Test name
Test status
Simulation time 361017552 ps
CPU time 1.27 seconds
Started Feb 08 11:02:03 AM UTC 25
Finished Feb 08 11:02:06 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730109033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1730109033
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.1332971820
Short name T307
Test name
Test status
Simulation time 527728855728 ps
CPU time 136.59 seconds
Started Feb 08 11:01:27 AM UTC 25
Finished Feb 08 11:03:46 AM UTC 25
Peak memory 211776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332971820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.1332971820
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.1949405440
Short name T322
Test name
Test status
Simulation time 323461707556 ps
CPU time 652.6 seconds
Started Feb 08 11:01:29 AM UTC 25
Finished Feb 08 11:12:29 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949405440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1949405440
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.2976029929
Short name T551
Test name
Test status
Simulation time 331372315192 ps
CPU time 366.99 seconds
Started Feb 08 11:01:11 AM UTC 25
Finished Feb 08 11:07:22 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976029929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2976029929
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1090930161
Short name T567
Test name
Test status
Simulation time 488293567998 ps
CPU time 517.98 seconds
Started Feb 08 11:01:12 AM UTC 25
Finished Feb 08 11:09:56 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090930161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.1090930161
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.847856520
Short name T594
Test name
Test status
Simulation time 489177786245 ps
CPU time 761.17 seconds
Started Feb 08 11:00:53 AM UTC 25
Finished Feb 08 11:13:44 AM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847856520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.847856520
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.2466828407
Short name T615
Test name
Test status
Simulation time 324612231154 ps
CPU time 884.86 seconds
Started Feb 08 11:01:07 AM UTC 25
Finished Feb 08 11:16:03 AM UTC 25
Peak memory 212644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466828407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.2466828407
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1478844070
Short name T295
Test name
Test status
Simulation time 190764858361 ps
CPU time 193.52 seconds
Started Feb 08 11:01:13 AM UTC 25
Finished Feb 08 11:04:30 AM UTC 25
Peak memory 211716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478844070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.1478844070
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4219362400
Short name T569
Test name
Test status
Simulation time 601394100135 ps
CPU time 518.65 seconds
Started Feb 08 11:01:16 AM UTC 25
Finished Feb 08 11:10:01 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219362400 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.4219362400
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.1771507580
Short name T573
Test name
Test status
Simulation time 124959118093 ps
CPU time 526.42 seconds
Started Feb 08 11:01:50 AM UTC 25
Finished Feb 08 11:10:42 AM UTC 25
Peak memory 211908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771507580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1771507580
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.4102375729
Short name T517
Test name
Test status
Simulation time 35954632060 ps
CPU time 19.75 seconds
Started Feb 08 11:01:39 AM UTC 25
Finished Feb 08 11:02:00 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102375729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4102375729
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.540436144
Short name T515
Test name
Test status
Simulation time 3574794271 ps
CPU time 3.86 seconds
Started Feb 08 11:01:33 AM UTC 25
Finished Feb 08 11:01:38 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540436144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.540436144
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.3601523580
Short name T512
Test name
Test status
Simulation time 6024683294 ps
CPU time 15.79 seconds
Started Feb 08 11:00:51 AM UTC 25
Finished Feb 08 11:01:09 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601523580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3601523580
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.343236395
Short name T617
Test name
Test status
Simulation time 350671612423 ps
CPU time 860.36 seconds
Started Feb 08 11:02:01 AM UTC 25
Finished Feb 08 11:16:31 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343236395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.343236395
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1031742660
Short name T34
Test name
Test status
Simulation time 70568961457 ps
CPU time 56.88 seconds
Started Feb 08 11:01:59 AM UTC 25
Finished Feb 08 11:02:58 AM UTC 25
Peak memory 221772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1031742660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_a
ll_with_rand_reset.1031742660
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.835471398
Short name T531
Test name
Test status
Simulation time 461131441 ps
CPU time 1.34 seconds
Started Feb 08 11:03:45 AM UTC 25
Finished Feb 08 11:03:48 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835471398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.835471398
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.3580975373
Short name T602
Test name
Test status
Simulation time 164878666237 ps
CPU time 712.75 seconds
Started Feb 08 11:02:36 AM UTC 25
Finished Feb 08 11:14:37 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580975373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.3580975373
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3661296687
Short name T546
Test name
Test status
Simulation time 347571111226 ps
CPU time 248.62 seconds
Started Feb 08 11:02:55 AM UTC 25
Finished Feb 08 11:07:08 AM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661296687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3661296687
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.747081295
Short name T570
Test name
Test status
Simulation time 161230713409 ps
CPU time 484.35 seconds
Started Feb 08 11:02:24 AM UTC 25
Finished Feb 08 11:10:34 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747081295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.747081295
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3615774675
Short name T596
Test name
Test status
Simulation time 334190308467 ps
CPU time 672.67 seconds
Started Feb 08 11:02:29 AM UTC 25
Finished Feb 08 11:13:50 AM UTC 25
Peak memory 211628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615774675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.3615774675
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3775769302
Short name T303
Test name
Test status
Simulation time 494094907116 ps
CPU time 393.91 seconds
Started Feb 08 11:02:09 AM UTC 25
Finished Feb 08 11:08:49 AM UTC 25
Peak memory 211508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775769302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3775769302
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.2354924171
Short name T621
Test name
Test status
Simulation time 334716040426 ps
CPU time 871.28 seconds
Started Feb 08 11:02:23 AM UTC 25
Finished Feb 08 11:17:03 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354924171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.2354924171
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.2332166311
Short name T538
Test name
Test status
Simulation time 364947919727 ps
CPU time 184.07 seconds
Started Feb 08 11:02:32 AM UTC 25
Finished Feb 08 11:05:40 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332166311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.2332166311
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3554078922
Short name T571
Test name
Test status
Simulation time 193311981268 ps
CPU time 477.65 seconds
Started Feb 08 11:02:33 AM UTC 25
Finished Feb 08 11:10:37 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554078922 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.3554078922
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.2697001796
Short name T579
Test name
Test status
Simulation time 69824335782 ps
CPU time 502.32 seconds
Started Feb 08 11:03:03 AM UTC 25
Finished Feb 08 11:11:32 AM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697001796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2697001796
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.4292415578
Short name T529
Test name
Test status
Simulation time 23734890321 ps
CPU time 25.29 seconds
Started Feb 08 11:03:01 AM UTC 25
Finished Feb 08 11:03:28 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292415578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4292415578
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.1617496575
Short name T527
Test name
Test status
Simulation time 4535736335 ps
CPU time 2.12 seconds
Started Feb 08 11:02:59 AM UTC 25
Finished Feb 08 11:03:03 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617496575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1617496575
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.1286128657
Short name T521
Test name
Test status
Simulation time 5707205688 ps
CPU time 14.21 seconds
Started Feb 08 11:02:06 AM UTC 25
Finished Feb 08 11:02:22 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286128657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1286128657
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3564240552
Short name T220
Test name
Test status
Simulation time 370506978817 ps
CPU time 289.77 seconds
Started Feb 08 11:03:29 AM UTC 25
Finished Feb 08 11:08:24 AM UTC 25
Peak memory 222040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3564240552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_a
ll_with_rand_reset.3564240552
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2977643383
Short name T26
Test name
Test status
Simulation time 461718099 ps
CPU time 3.24 seconds
Started Feb 08 10:22:24 AM UTC 25
Finished Feb 08 10:22:29 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977643383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2977643383
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1807052035
Short name T15
Test name
Test status
Simulation time 344184145847 ps
CPU time 111.91 seconds
Started Feb 08 10:21:00 AM UTC 25
Finished Feb 08 10:22:55 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807052035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.1807052035
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.900036006
Short name T236
Test name
Test status
Simulation time 322940792517 ps
CPU time 888 seconds
Started Feb 08 10:20:51 AM UTC 25
Finished Feb 08 10:35:49 AM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900036006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.900036006
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2492967240
Short name T383
Test name
Test status
Simulation time 331300930123 ps
CPU time 575.26 seconds
Started Feb 08 10:20:52 AM UTC 25
Finished Feb 08 10:30:34 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492967240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.2492967240
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.345940262
Short name T152
Test name
Test status
Simulation time 494675467869 ps
CPU time 329.82 seconds
Started Feb 08 10:20:44 AM UTC 25
Finished Feb 08 10:26:18 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345940262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.345940262
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.3931710742
Short name T368
Test name
Test status
Simulation time 161513676433 ps
CPU time 409.7 seconds
Started Feb 08 10:20:44 AM UTC 25
Finished Feb 08 10:27:39 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931710742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.3931710742
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2578433052
Short name T389
Test name
Test status
Simulation time 401417611176 ps
CPU time 719.47 seconds
Started Feb 08 10:20:55 AM UTC 25
Finished Feb 08 10:33:03 AM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578433052 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.2578433052
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.355790945
Short name T58
Test name
Test status
Simulation time 42208607790 ps
CPU time 48.93 seconds
Started Feb 08 10:21:54 AM UTC 25
Finished Feb 08 10:22:45 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355790945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.355790945
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.1244114287
Short name T24
Test name
Test status
Simulation time 4100651822 ps
CPU time 11.18 seconds
Started Feb 08 10:21:49 AM UTC 25
Finished Feb 08 10:22:02 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244114287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1244114287
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2707080225
Short name T27
Test name
Test status
Simulation time 8188427002 ps
CPU time 13.02 seconds
Started Feb 08 10:22:18 AM UTC 25
Finished Feb 08 10:22:32 AM UTC 25
Peak memory 243820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707080225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2707080225
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3910569411
Short name T10
Test name
Test status
Simulation time 5732630555 ps
CPU time 8.21 seconds
Started Feb 08 10:20:42 AM UTC 25
Finished Feb 08 10:20:51 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910569411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3910569411
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3486305617
Short name T227
Test name
Test status
Simulation time 329648351042 ps
CPU time 846.64 seconds
Started Feb 08 10:22:04 AM UTC 25
Finished Feb 08 10:36:20 AM UTC 25
Peak memory 212596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486305617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.3486305617
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.989574272
Short name T540
Test name
Test status
Simulation time 445061395 ps
CPU time 1.81 seconds
Started Feb 08 11:06:14 AM UTC 25
Finished Feb 08 11:06:18 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989574272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.989574272
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.584347142
Short name T599
Test name
Test status
Simulation time 176421095174 ps
CPU time 573.14 seconds
Started Feb 08 11:04:31 AM UTC 25
Finished Feb 08 11:14:11 AM UTC 25
Peak memory 211716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584347142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.584347142
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.826655708
Short name T557
Test name
Test status
Simulation time 164227894514 ps
CPU time 166.8 seconds
Started Feb 08 11:05:01 AM UTC 25
Finished Feb 08 11:07:51 AM UTC 25
Peak memory 211696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826655708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.826655708
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.2420232179
Short name T345
Test name
Test status
Simulation time 489828700685 ps
CPU time 1140.65 seconds
Started Feb 08 11:03:51 AM UTC 25
Finished Feb 08 11:23:04 AM UTC 25
Peak memory 212672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420232179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2420232179
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3428833542
Short name T559
Test name
Test status
Simulation time 162386452371 ps
CPU time 246.12 seconds
Started Feb 08 11:04:18 AM UTC 25
Finished Feb 08 11:08:28 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428833542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.3428833542
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.1451636562
Short name T654
Test name
Test status
Simulation time 325513629765 ps
CPU time 1081.13 seconds
Started Feb 08 11:03:49 AM UTC 25
Finished Feb 08 11:22:02 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451636562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1451636562
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1507965044
Short name T587
Test name
Test status
Simulation time 160331858708 ps
CPU time 540.06 seconds
Started Feb 08 11:03:50 AM UTC 25
Finished Feb 08 11:12:57 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507965044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.1507965044
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3211138262
Short name T265
Test name
Test status
Simulation time 177550988498 ps
CPU time 72.86 seconds
Started Feb 08 11:04:21 AM UTC 25
Finished Feb 08 11:05:36 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211138262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3211138262
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.4214541749
Short name T558
Test name
Test status
Simulation time 214240289032 ps
CPU time 214.69 seconds
Started Feb 08 11:04:25 AM UTC 25
Finished Feb 08 11:08:03 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214541749 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.4214541749
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.798745207
Short name T585
Test name
Test status
Simulation time 68782222579 ps
CPU time 419.45 seconds
Started Feb 08 11:05:36 AM UTC 25
Finished Feb 08 11:12:41 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798745207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.798745207
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2287502021
Short name T539
Test name
Test status
Simulation time 45599845002 ps
CPU time 42.84 seconds
Started Feb 08 11:05:29 AM UTC 25
Finished Feb 08 11:06:14 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287502021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2287502021
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.2173782978
Short name T537
Test name
Test status
Simulation time 5356051511 ps
CPU time 22.97 seconds
Started Feb 08 11:05:04 AM UTC 25
Finished Feb 08 11:05:29 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173782978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2173782978
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.1285915428
Short name T532
Test name
Test status
Simulation time 5627899719 ps
CPU time 27.12 seconds
Started Feb 08 11:03:47 AM UTC 25
Finished Feb 08 11:04:16 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285915428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1285915428
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.451111052
Short name T328
Test name
Test status
Simulation time 667620458979 ps
CPU time 200.59 seconds
Started Feb 08 11:05:40 AM UTC 25
Finished Feb 08 11:09:04 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451111052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.451111052
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4097496427
Short name T35
Test name
Test status
Simulation time 94320290390 ps
CPU time 217.92 seconds
Started Feb 08 11:05:36 AM UTC 25
Finished Feb 08 11:09:18 AM UTC 25
Peak memory 222108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4097496427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_a
ll_with_rand_reset.4097496427
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1540030797
Short name T552
Test name
Test status
Simulation time 503963593 ps
CPU time 2.11 seconds
Started Feb 08 11:07:23 AM UTC 25
Finished Feb 08 11:07:27 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540030797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1540030797
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1743219553
Short name T251
Test name
Test status
Simulation time 426465263642 ps
CPU time 514.2 seconds
Started Feb 08 11:06:46 AM UTC 25
Finished Feb 08 11:15:27 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743219553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.1743219553
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.605254082
Short name T282
Test name
Test status
Simulation time 373484025214 ps
CPU time 1186.93 seconds
Started Feb 08 11:06:50 AM UTC 25
Finished Feb 08 11:26:51 AM UTC 25
Peak memory 212836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605254082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.605254082
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1227680838
Short name T609
Test name
Test status
Simulation time 170048855433 ps
CPU time 533.21 seconds
Started Feb 08 11:06:25 AM UTC 25
Finished Feb 08 11:15:25 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227680838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.1227680838
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.3562902599
Short name T548
Test name
Test status
Simulation time 162771482379 ps
CPU time 50.67 seconds
Started Feb 08 11:06:19 AM UTC 25
Finished Feb 08 11:07:12 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562902599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3562902599
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.1425368875
Short name T593
Test name
Test status
Simulation time 162891955941 ps
CPU time 432.89 seconds
Started Feb 08 11:06:21 AM UTC 25
Finished Feb 08 11:13:38 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425368875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.1425368875
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2895121310
Short name T575
Test name
Test status
Simulation time 396716265804 ps
CPU time 264.11 seconds
Started Feb 08 11:06:35 AM UTC 25
Finished Feb 08 11:11:03 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895121310 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.2895121310
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.70903345
Short name T625
Test name
Test status
Simulation time 79800077037 ps
CPU time 598.19 seconds
Started Feb 08 11:07:13 AM UTC 25
Finished Feb 08 11:17:19 AM UTC 25
Peak memory 211824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70903345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.70903345
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.676798331
Short name T555
Test name
Test status
Simulation time 28603578466 ps
CPU time 25.71 seconds
Started Feb 08 11:07:12 AM UTC 25
Finished Feb 08 11:07:39 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676798331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.676798331
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.66960584
Short name T553
Test name
Test status
Simulation time 3874382424 ps
CPU time 17.59 seconds
Started Feb 08 11:07:09 AM UTC 25
Finished Feb 08 11:07:28 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66960584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.66960584
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.4065298970
Short name T543
Test name
Test status
Simulation time 6110799682 ps
CPU time 7.68 seconds
Started Feb 08 11:06:18 AM UTC 25
Finished Feb 08 11:06:28 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065298970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4065298970
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.2348051960
Short name T790
Test name
Test status
Simulation time 672039411656 ps
CPU time 2375.48 seconds
Started Feb 08 11:07:16 AM UTC 25
Finished Feb 08 11:47:17 AM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348051960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.2348051960
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.554048468
Short name T65
Test name
Test status
Simulation time 485558418477 ps
CPU time 656.41 seconds
Started Feb 08 11:07:14 AM UTC 25
Finished Feb 08 11:18:18 AM UTC 25
Peak memory 222032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=554048468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_al
l_with_rand_reset.554048468
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.4239585340
Short name T563
Test name
Test status
Simulation time 446551465 ps
CPU time 1.07 seconds
Started Feb 08 11:09:02 AM UTC 25
Finished Feb 08 11:09:04 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239585340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4239585340
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2377145574
Short name T580
Test name
Test status
Simulation time 551528257372 ps
CPU time 190.47 seconds
Started Feb 08 11:08:20 AM UTC 25
Finished Feb 08 11:11:33 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377145574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.2377145574
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.2659015116
Short name T334
Test name
Test status
Simulation time 547659414092 ps
CPU time 783.59 seconds
Started Feb 08 11:08:25 AM UTC 25
Finished Feb 08 11:21:37 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659015116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2659015116
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.837696417
Short name T645
Test name
Test status
Simulation time 499032310920 ps
CPU time 739.29 seconds
Started Feb 08 11:07:40 AM UTC 25
Finished Feb 08 11:20:09 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837696417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.837696417
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2659612991
Short name T592
Test name
Test status
Simulation time 165664786679 ps
CPU time 350.81 seconds
Started Feb 08 11:07:40 AM UTC 25
Finished Feb 08 11:13:36 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659612991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.2659612991
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2318938077
Short name T346
Test name
Test status
Simulation time 488352755788 ps
CPU time 1459.33 seconds
Started Feb 08 11:07:29 AM UTC 25
Finished Feb 08 11:32:06 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318938077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2318938077
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.812635897
Short name T578
Test name
Test status
Simulation time 324856304987 ps
CPU time 220.23 seconds
Started Feb 08 11:07:38 AM UTC 25
Finished Feb 08 11:11:22 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812635897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.812635897
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3038302334
Short name T634
Test name
Test status
Simulation time 398445470412 ps
CPU time 614.91 seconds
Started Feb 08 11:08:04 AM UTC 25
Finished Feb 08 11:18:26 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038302334 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.3038302334
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.2552887304
Short name T214
Test name
Test status
Simulation time 117042374126 ps
CPU time 749.04 seconds
Started Feb 08 11:08:50 AM UTC 25
Finished Feb 08 11:21:28 AM UTC 25
Peak memory 211728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552887304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2552887304
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.82174561
Short name T566
Test name
Test status
Simulation time 28863661616 ps
CPU time 64.19 seconds
Started Feb 08 11:08:43 AM UTC 25
Finished Feb 08 11:09:49 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82174561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.82174561
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.3863693049
Short name T561
Test name
Test status
Simulation time 5324741508 ps
CPU time 18.97 seconds
Started Feb 08 11:08:29 AM UTC 25
Finished Feb 08 11:08:50 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863693049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3863693049
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.1238507281
Short name T554
Test name
Test status
Simulation time 5877929957 ps
CPU time 8.45 seconds
Started Feb 08 11:07:27 AM UTC 25
Finished Feb 08 11:07:38 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238507281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1238507281
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1089925642
Short name T562
Test name
Test status
Simulation time 16510933054 ps
CPU time 6.96 seconds
Started Feb 08 11:08:53 AM UTC 25
Finished Feb 08 11:09:01 AM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089925642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.1089925642
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3603065058
Short name T304
Test name
Test status
Simulation time 223261289078 ps
CPU time 411.3 seconds
Started Feb 08 11:08:50 AM UTC 25
Finished Feb 08 11:15:47 AM UTC 25
Peak memory 221876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3603065058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_a
ll_with_rand_reset.3603065058
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.1363992475
Short name T574
Test name
Test status
Simulation time 292143395 ps
CPU time 2.22 seconds
Started Feb 08 11:10:59 AM UTC 25
Finished Feb 08 11:11:03 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363992475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1363992475
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1834509617
Short name T194
Test name
Test status
Simulation time 511477053831 ps
CPU time 135.01 seconds
Started Feb 08 11:09:59 AM UTC 25
Finished Feb 08 11:12:16 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834509617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.1834509617
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3486951542
Short name T581
Test name
Test status
Simulation time 338039505812 ps
CPU time 94.11 seconds
Started Feb 08 11:10:02 AM UTC 25
Finished Feb 08 11:11:38 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486951542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3486951542
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.1258789212
Short name T330
Test name
Test status
Simulation time 162920285388 ps
CPU time 176.7 seconds
Started Feb 08 11:09:37 AM UTC 25
Finished Feb 08 11:12:37 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258789212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1258789212
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4101928244
Short name T761
Test name
Test status
Simulation time 488786968112 ps
CPU time 1553.6 seconds
Started Feb 08 11:09:37 AM UTC 25
Finished Feb 08 11:35:47 AM UTC 25
Peak memory 212656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101928244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.4101928244
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.3573982034
Short name T745
Test name
Test status
Simulation time 497212829292 ps
CPU time 1457.19 seconds
Started Feb 08 11:09:05 AM UTC 25
Finished Feb 08 11:33:38 AM UTC 25
Peak memory 212616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573982034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3573982034
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.1360507734
Short name T582
Test name
Test status
Simulation time 167346740144 ps
CPU time 162.11 seconds
Started Feb 08 11:09:18 AM UTC 25
Finished Feb 08 11:12:03 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360507734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.1360507734
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.3614886621
Short name T722
Test name
Test status
Simulation time 411337772895 ps
CPU time 1239.6 seconds
Started Feb 08 11:09:50 AM UTC 25
Finished Feb 08 11:30:42 AM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614886621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.3614886621
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2829366911
Short name T630
Test name
Test status
Simulation time 610001097576 ps
CPU time 463.99 seconds
Started Feb 08 11:09:58 AM UTC 25
Finished Feb 08 11:17:47 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829366911 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.2829366911
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.644640879
Short name T666
Test name
Test status
Simulation time 112397541787 ps
CPU time 763.14 seconds
Started Feb 08 11:10:40 AM UTC 25
Finished Feb 08 11:23:32 AM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644640879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.644640879
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.449157358
Short name T577
Test name
Test status
Simulation time 35304549755 ps
CPU time 37.52 seconds
Started Feb 08 11:10:38 AM UTC 25
Finished Feb 08 11:11:17 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449157358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.449157358
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.2802292616
Short name T572
Test name
Test status
Simulation time 3223302130 ps
CPU time 3.01 seconds
Started Feb 08 11:10:35 AM UTC 25
Finished Feb 08 11:10:39 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802292616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2802292616
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1819933160
Short name T565
Test name
Test status
Simulation time 5893400305 ps
CPU time 29.5 seconds
Started Feb 08 11:09:05 AM UTC 25
Finished Feb 08 11:09:37 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819933160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1819933160
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.2199323639
Short name T639
Test name
Test status
Simulation time 166355339804 ps
CPU time 515.39 seconds
Started Feb 08 11:10:43 AM UTC 25
Finished Feb 08 11:19:25 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199323639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.2199323639
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.160721083
Short name T586
Test name
Test status
Simulation time 387536012 ps
CPU time 1.39 seconds
Started Feb 08 11:12:38 AM UTC 25
Finished Feb 08 11:12:41 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160721083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.160721083
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.3690637180
Short name T313
Test name
Test status
Simulation time 554474620710 ps
CPU time 266.31 seconds
Started Feb 08 11:11:34 AM UTC 25
Finished Feb 08 11:16:04 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690637180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.3690637180
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.1136142683
Short name T178
Test name
Test status
Simulation time 492136067228 ps
CPU time 144.99 seconds
Started Feb 08 11:11:39 AM UTC 25
Finished Feb 08 11:14:06 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136142683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1136142683
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.4004156102
Short name T638
Test name
Test status
Simulation time 161658638713 ps
CPU time 474.6 seconds
Started Feb 08 11:11:18 AM UTC 25
Finished Feb 08 11:19:19 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004156102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4004156102
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3984505612
Short name T605
Test name
Test status
Simulation time 480900554505 ps
CPU time 215.83 seconds
Started Feb 08 11:11:23 AM UTC 25
Finished Feb 08 11:15:03 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984505612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3984505612
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.987152022
Short name T349
Test name
Test status
Simulation time 326720451981 ps
CPU time 418.13 seconds
Started Feb 08 11:11:04 AM UTC 25
Finished Feb 08 11:18:08 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987152022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.987152022
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.267577144
Short name T607
Test name
Test status
Simulation time 163598650713 ps
CPU time 234.12 seconds
Started Feb 08 11:11:11 AM UTC 25
Finished Feb 08 11:15:09 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267577144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.267577144
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3064720484
Short name T714
Test name
Test status
Simulation time 374220814880 ps
CPU time 1095.58 seconds
Started Feb 08 11:11:28 AM UTC 25
Finished Feb 08 11:29:56 AM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064720484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.3064720484
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1010371803
Short name T629
Test name
Test status
Simulation time 584699323284 ps
CPU time 362.58 seconds
Started Feb 08 11:11:32 AM UTC 25
Finished Feb 08 11:17:40 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010371803 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.1010371803
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.1330078815
Short name T688
Test name
Test status
Simulation time 107344792073 ps
CPU time 884.91 seconds
Started Feb 08 11:12:14 AM UTC 25
Finished Feb 08 11:27:10 AM UTC 25
Peak memory 213004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330078815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1330078815
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2895604603
Short name T589
Test name
Test status
Simulation time 32655483384 ps
CPU time 68.45 seconds
Started Feb 08 11:12:12 AM UTC 25
Finished Feb 08 11:13:22 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895604603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2895604603
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.1423529211
Short name T583
Test name
Test status
Simulation time 4127258625 ps
CPU time 5.06 seconds
Started Feb 08 11:12:05 AM UTC 25
Finished Feb 08 11:12:11 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423529211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1423529211
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.4149155920
Short name T576
Test name
Test status
Simulation time 6185170342 ps
CPU time 4.96 seconds
Started Feb 08 11:11:04 AM UTC 25
Finished Feb 08 11:11:10 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149155920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4149155920
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.2839132142
Short name T66
Test name
Test status
Simulation time 528706239872 ps
CPU time 592.1 seconds
Started Feb 08 11:12:30 AM UTC 25
Finished Feb 08 11:22:29 AM UTC 25
Peak memory 222040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839132142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.2839132142
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.262936094
Short name T36
Test name
Test status
Simulation time 431096131415 ps
CPU time 276.47 seconds
Started Feb 08 11:12:17 AM UTC 25
Finished Feb 08 11:16:58 AM UTC 25
Peak memory 221784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=262936094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_al
l_with_rand_reset.262936094
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.1165579990
Short name T598
Test name
Test status
Simulation time 307457535 ps
CPU time 1.24 seconds
Started Feb 08 11:14:01 AM UTC 25
Finished Feb 08 11:14:04 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165579990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1165579990
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2850691368
Short name T650
Test name
Test status
Simulation time 163353117321 ps
CPU time 491.13 seconds
Started Feb 08 11:13:10 AM UTC 25
Finished Feb 08 11:21:28 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850691368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.2850691368
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2463480843
Short name T757
Test name
Test status
Simulation time 494966844405 ps
CPU time 1360.11 seconds
Started Feb 08 11:12:41 AM UTC 25
Finished Feb 08 11:35:36 AM UTC 25
Peak memory 212672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463480843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2463480843
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.2759531356
Short name T646
Test name
Test status
Simulation time 329043185545 ps
CPU time 461.82 seconds
Started Feb 08 11:12:58 AM UTC 25
Finished Feb 08 11:20:46 AM UTC 25
Peak memory 211472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759531356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.2759531356
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.4212649473
Short name T179
Test name
Test status
Simulation time 425042360950 ps
CPU time 201.05 seconds
Started Feb 08 11:13:23 AM UTC 25
Finished Feb 08 11:16:48 AM UTC 25
Peak memory 211776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212649473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.4212649473
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4166821041
Short name T686
Test name
Test status
Simulation time 406175639468 ps
CPU time 783.59 seconds
Started Feb 08 11:13:28 AM UTC 25
Finished Feb 08 11:26:40 AM UTC 25
Peak memory 211612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166821041 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.4166821041
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3814552049
Short name T652
Test name
Test status
Simulation time 76163813982 ps
CPU time 470.65 seconds
Started Feb 08 11:13:46 AM UTC 25
Finished Feb 08 11:21:42 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814552049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3814552049
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.4122049894
Short name T604
Test name
Test status
Simulation time 24912283935 ps
CPU time 67.62 seconds
Started Feb 08 11:13:45 AM UTC 25
Finished Feb 08 11:14:55 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122049894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4122049894
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.1523320103
Short name T595
Test name
Test status
Simulation time 3094704332 ps
CPU time 4.14 seconds
Started Feb 08 11:13:40 AM UTC 25
Finished Feb 08 11:13:45 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523320103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1523320103
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.415467124
Short name T588
Test name
Test status
Simulation time 6021568094 ps
CPU time 24.18 seconds
Started Feb 08 11:12:41 AM UTC 25
Finished Feb 08 11:13:07 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415467124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.adc_ctrl_smoke.415467124
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.915950540
Short name T301
Test name
Test status
Simulation time 197029392626 ps
CPU time 135.78 seconds
Started Feb 08 11:13:52 AM UTC 25
Finished Feb 08 11:16:11 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915950540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.915950540
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.901534746
Short name T37
Test name
Test status
Simulation time 93671073571 ps
CPU time 328.42 seconds
Started Feb 08 11:13:51 AM UTC 25
Finished Feb 08 11:19:24 AM UTC 25
Peak memory 228180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=901534746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_al
l_with_rand_reset.901534746
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.171633460
Short name T611
Test name
Test status
Simulation time 339714568 ps
CPU time 2.25 seconds
Started Feb 08 11:15:26 AM UTC 25
Finished Feb 08 11:15:30 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171633460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.171633460
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.712164043
Short name T292
Test name
Test status
Simulation time 490775687536 ps
CPU time 369.78 seconds
Started Feb 08 11:14:38 AM UTC 25
Finished Feb 08 11:20:53 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712164043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.712164043
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.4128910961
Short name T614
Test name
Test status
Simulation time 178573278376 ps
CPU time 69.44 seconds
Started Feb 08 11:14:44 AM UTC 25
Finished Feb 08 11:15:56 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128910961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4128910961
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.2762530573
Short name T622
Test name
Test status
Simulation time 167081547437 ps
CPU time 174.86 seconds
Started Feb 08 11:14:11 AM UTC 25
Finished Feb 08 11:17:09 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762530573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2762530573
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3595316027
Short name T618
Test name
Test status
Simulation time 162049868485 ps
CPU time 141.59 seconds
Started Feb 08 11:14:27 AM UTC 25
Finished Feb 08 11:16:52 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595316027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.3595316027
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.3910326113
Short name T608
Test name
Test status
Simulation time 159377987434 ps
CPU time 70.83 seconds
Started Feb 08 11:14:06 AM UTC 25
Finished Feb 08 11:15:19 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910326113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3910326113
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.3477715512
Short name T637
Test name
Test status
Simulation time 325857881334 ps
CPU time 302.78 seconds
Started Feb 08 11:14:07 AM UTC 25
Finished Feb 08 11:19:14 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477715512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.3477715512
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.2619810604
Short name T783
Test name
Test status
Simulation time 603570517149 ps
CPU time 1710.01 seconds
Started Feb 08 11:14:28 AM UTC 25
Finished Feb 08 11:43:17 AM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619810604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.2619810604
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3875514545
Short name T623
Test name
Test status
Simulation time 211070241030 ps
CPU time 149.44 seconds
Started Feb 08 11:14:37 AM UTC 25
Finished Feb 08 11:17:10 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875514545 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.3875514545
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.1448551423
Short name T707
Test name
Test status
Simulation time 123512417449 ps
CPU time 857.04 seconds
Started Feb 08 11:15:05 AM UTC 25
Finished Feb 08 11:29:31 AM UTC 25
Peak memory 213080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448551423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1448551423
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2051554106
Short name T610
Test name
Test status
Simulation time 23127656926 ps
CPU time 22.81 seconds
Started Feb 08 11:15:04 AM UTC 25
Finished Feb 08 11:15:28 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051554106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2051554106
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.242294771
Short name T606
Test name
Test status
Simulation time 5201320145 ps
CPU time 6.28 seconds
Started Feb 08 11:14:56 AM UTC 25
Finished Feb 08 11:15:04 AM UTC 25
Peak memory 211680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242294771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.242294771
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.15152118
Short name T601
Test name
Test status
Simulation time 6108811005 ps
CPU time 29.69 seconds
Started Feb 08 11:14:05 AM UTC 25
Finished Feb 08 11:14:36 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15152118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.adc_ctrl_smoke.15152118
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.1642282027
Short name T697
Test name
Test status
Simulation time 189856774761 ps
CPU time 776.03 seconds
Started Feb 08 11:15:20 AM UTC 25
Finished Feb 08 11:28:26 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642282027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.1642282027
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.134921537
Short name T620
Test name
Test status
Simulation time 33654776152 ps
CPU time 103.53 seconds
Started Feb 08 11:15:10 AM UTC 25
Finished Feb 08 11:16:55 AM UTC 25
Peak memory 222108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=134921537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_al
l_with_rand_reset.134921537
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.3648884604
Short name T619
Test name
Test status
Simulation time 345565434 ps
CPU time 2.34 seconds
Started Feb 08 11:16:49 AM UTC 25
Finished Feb 08 11:16:53 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648884604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3648884604
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2011837052
Short name T316
Test name
Test status
Simulation time 162031894520 ps
CPU time 379.02 seconds
Started Feb 08 11:15:48 AM UTC 25
Finished Feb 08 11:22:12 AM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011837052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.2011837052
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.2328209352
Short name T633
Test name
Test status
Simulation time 162251865973 ps
CPU time 129.38 seconds
Started Feb 08 11:15:56 AM UTC 25
Finished Feb 08 11:18:08 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328209352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2328209352
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.647038753
Short name T674
Test name
Test status
Simulation time 167152330908 ps
CPU time 564.88 seconds
Started Feb 08 11:15:31 AM UTC 25
Finished Feb 08 11:25:03 AM UTC 25
Peak memory 211780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647038753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.647038753
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1130789074
Short name T662
Test name
Test status
Simulation time 162224708556 ps
CPU time 465.17 seconds
Started Feb 08 11:15:31 AM UTC 25
Finished Feb 08 11:23:22 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130789074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.1130789074
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1881638470
Short name T709
Test name
Test status
Simulation time 503518903301 ps
CPU time 840.25 seconds
Started Feb 08 11:15:28 AM UTC 25
Finished Feb 08 11:29:39 AM UTC 25
Peak memory 212604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881638470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1881638470
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1438500519
Short name T668
Test name
Test status
Simulation time 322256407529 ps
CPU time 482.56 seconds
Started Feb 08 11:15:29 AM UTC 25
Finished Feb 08 11:23:38 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438500519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.1438500519
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.1289886879
Short name T683
Test name
Test status
Simulation time 556753308021 ps
CPU time 643.63 seconds
Started Feb 08 11:15:37 AM UTC 25
Finished Feb 08 11:26:28 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289886879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.1289886879
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1970508858
Short name T695
Test name
Test status
Simulation time 588280636717 ps
CPU time 752.85 seconds
Started Feb 08 11:15:38 AM UTC 25
Finished Feb 08 11:28:20 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970508858 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.1970508858
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.1973500978
Short name T635
Test name
Test status
Simulation time 38300275570 ps
CPU time 150.21 seconds
Started Feb 08 11:16:05 AM UTC 25
Finished Feb 08 11:18:38 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973500978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1973500978
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.1264571352
Short name T616
Test name
Test status
Simulation time 4317984187 ps
CPU time 3.1 seconds
Started Feb 08 11:16:03 AM UTC 25
Finished Feb 08 11:16:08 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264571352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1264571352
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.1773282315
Short name T612
Test name
Test status
Simulation time 6001840212 ps
CPU time 6.37 seconds
Started Feb 08 11:15:28 AM UTC 25
Finished Feb 08 11:15:36 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773282315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1773282315
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.2525985681
Short name T306
Test name
Test status
Simulation time 4391138880234 ps
CPU time 1519.94 seconds
Started Feb 08 11:16:32 AM UTC 25
Finished Feb 08 11:42:08 AM UTC 25
Peak memory 223136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525985681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.2525985681
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.3477879663
Short name T631
Test name
Test status
Simulation time 559089504 ps
CPU time 1.44 seconds
Started Feb 08 11:17:45 AM UTC 25
Finished Feb 08 11:17:47 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477879663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3477879663
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3065966982
Short name T708
Test name
Test status
Simulation time 185075143005 ps
CPU time 733.96 seconds
Started Feb 08 11:17:14 AM UTC 25
Finished Feb 08 11:29:38 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065966982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.3065966982
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3952948230
Short name T308
Test name
Test status
Simulation time 163318810722 ps
CPU time 177.11 seconds
Started Feb 08 11:17:19 AM UTC 25
Finished Feb 08 11:20:20 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952948230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3952948230
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.2928893609
Short name T180
Test name
Test status
Simulation time 486363463593 ps
CPU time 306 seconds
Started Feb 08 11:16:58 AM UTC 25
Finished Feb 08 11:22:09 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928893609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2928893609
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1969722855
Short name T636
Test name
Test status
Simulation time 166712611188 ps
CPU time 98.04 seconds
Started Feb 08 11:17:04 AM UTC 25
Finished Feb 08 11:18:44 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969722855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.1969722855
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2326832673
Short name T232
Test name
Test status
Simulation time 160709674444 ps
CPU time 452.65 seconds
Started Feb 08 11:16:54 AM UTC 25
Finished Feb 08 11:24:33 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326832673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2326832673
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2502631005
Short name T679
Test name
Test status
Simulation time 166898393855 ps
CPU time 543.16 seconds
Started Feb 08 11:16:56 AM UTC 25
Finished Feb 08 11:26:06 AM UTC 25
Peak memory 211804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502631005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.2502631005
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.4085048911
Short name T691
Test name
Test status
Simulation time 546814254963 ps
CPU time 624.23 seconds
Started Feb 08 11:17:10 AM UTC 25
Finished Feb 08 11:27:42 AM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085048911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.4085048911
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2680260767
Short name T741
Test name
Test status
Simulation time 393133545687 ps
CPU time 946.85 seconds
Started Feb 08 11:17:10 AM UTC 25
Finished Feb 08 11:33:07 AM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680260767 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.2680260767
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3507146413
Short name T658
Test name
Test status
Simulation time 75380756615 ps
CPU time 316.92 seconds
Started Feb 08 11:17:37 AM UTC 25
Finished Feb 08 11:22:59 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507146413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3507146413
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.3078291768
Short name T640
Test name
Test status
Simulation time 27352913916 ps
CPU time 119.09 seconds
Started Feb 08 11:17:24 AM UTC 25
Finished Feb 08 11:19:26 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078291768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3078291768
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.2353718693
Short name T628
Test name
Test status
Simulation time 4573189511 ps
CPU time 11.93 seconds
Started Feb 08 11:17:23 AM UTC 25
Finished Feb 08 11:17:37 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353718693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2353718693
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1606590861
Short name T627
Test name
Test status
Simulation time 5921290647 ps
CPU time 28.78 seconds
Started Feb 08 11:16:53 AM UTC 25
Finished Feb 08 11:17:24 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606590861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1606590861
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.904392256
Short name T284
Test name
Test status
Simulation time 150475412798 ps
CPU time 305.08 seconds
Started Feb 08 11:17:40 AM UTC 25
Finished Feb 08 11:22:49 AM UTC 25
Peak memory 222116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=904392256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_al
l_with_rand_reset.904392256
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.2351457078
Short name T641
Test name
Test status
Simulation time 350265404 ps
CPU time 2.33 seconds
Started Feb 08 11:19:29 AM UTC 25
Finished Feb 08 11:19:33 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351457078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2351457078
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.3538677739
Short name T725
Test name
Test status
Simulation time 340313450733 ps
CPU time 728.7 seconds
Started Feb 08 11:18:38 AM UTC 25
Finished Feb 08 11:30:55 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538677739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.3538677739
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2594992836
Short name T347
Test name
Test status
Simulation time 331936389308 ps
CPU time 258.83 seconds
Started Feb 08 11:18:45 AM UTC 25
Finished Feb 08 11:23:08 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594992836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2594992836
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2239944132
Short name T711
Test name
Test status
Simulation time 487197546075 ps
CPU time 689.52 seconds
Started Feb 08 11:18:09 AM UTC 25
Finished Feb 08 11:29:47 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239944132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2239944132
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3971447392
Short name T644
Test name
Test status
Simulation time 159039538202 ps
CPU time 103.38 seconds
Started Feb 08 11:18:09 AM UTC 25
Finished Feb 08 11:19:55 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971447392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.3971447392
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.1125157596
Short name T266
Test name
Test status
Simulation time 164087401069 ps
CPU time 387.36 seconds
Started Feb 08 11:17:48 AM UTC 25
Finished Feb 08 11:24:20 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125157596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1125157596
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.2168210376
Short name T647
Test name
Test status
Simulation time 328212760753 ps
CPU time 177.87 seconds
Started Feb 08 11:18:08 AM UTC 25
Finished Feb 08 11:21:09 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168210376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.2168210376
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.1845340298
Short name T667
Test name
Test status
Simulation time 169053140865 ps
CPU time 313.07 seconds
Started Feb 08 11:18:19 AM UTC 25
Finished Feb 08 11:23:37 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845340298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.1845340298
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1632975710
Short name T660
Test name
Test status
Simulation time 404248829469 ps
CPU time 286.14 seconds
Started Feb 08 11:18:27 AM UTC 25
Finished Feb 08 11:23:17 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632975710 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.1632975710
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.342645766
Short name T696
Test name
Test status
Simulation time 87972710759 ps
CPU time 532 seconds
Started Feb 08 11:19:25 AM UTC 25
Finished Feb 08 11:28:23 AM UTC 25
Peak memory 212032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342645766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.342645766
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3673169336
Short name T648
Test name
Test status
Simulation time 26646985971 ps
CPU time 111.62 seconds
Started Feb 08 11:19:19 AM UTC 25
Finished Feb 08 11:21:14 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673169336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3673169336
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2947153614
Short name T642
Test name
Test status
Simulation time 4464744206 ps
CPU time 20.03 seconds
Started Feb 08 11:19:15 AM UTC 25
Finished Feb 08 11:19:37 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947153614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2947153614
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.1173008165
Short name T632
Test name
Test status
Simulation time 5787919912 ps
CPU time 17.97 seconds
Started Feb 08 11:17:48 AM UTC 25
Finished Feb 08 11:18:07 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173008165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1173008165
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.3678262017
Short name T323
Test name
Test status
Simulation time 516251893533 ps
CPU time 1443.36 seconds
Started Feb 08 11:19:27 AM UTC 25
Finished Feb 08 11:43:45 AM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678262017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.3678262017
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1762936993
Short name T261
Test name
Test status
Simulation time 104334822080 ps
CPU time 216.49 seconds
Started Feb 08 11:19:26 AM UTC 25
Finished Feb 08 11:23:06 AM UTC 25
Peak memory 221776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1762936993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_a
ll_with_rand_reset.1762936993
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1313180734
Short name T38
Test name
Test status
Simulation time 511787577 ps
CPU time 1.99 seconds
Started Feb 08 10:23:45 AM UTC 25
Finished Feb 08 10:23:48 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313180734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1313180734
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3065142619
Short name T167
Test name
Test status
Simulation time 207846014591 ps
CPU time 755.16 seconds
Started Feb 08 10:23:12 AM UTC 25
Finished Feb 08 10:35:56 AM UTC 25
Peak memory 212592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065142619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3065142619
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.215829645
Short name T223
Test name
Test status
Simulation time 161413112845 ps
CPU time 448.5 seconds
Started Feb 08 10:22:45 AM UTC 25
Finished Feb 08 10:30:19 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215829645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.215829645
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3540058931
Short name T376
Test name
Test status
Simulation time 166792565014 ps
CPU time 372.78 seconds
Started Feb 08 10:22:54 AM UTC 25
Finished Feb 08 10:29:12 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540058931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.3540058931
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.4223557466
Short name T141
Test name
Test status
Simulation time 165141598899 ps
CPU time 157.37 seconds
Started Feb 08 10:22:33 AM UTC 25
Finished Feb 08 10:25:13 AM UTC 25
Peak memory 211844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223557466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4223557466
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1917615226
Short name T367
Test name
Test status
Simulation time 167279722672 ps
CPU time 285.62 seconds
Started Feb 08 10:22:37 AM UTC 25
Finished Feb 08 10:27:27 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917615226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.1917615226
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3457460661
Short name T19
Test name
Test status
Simulation time 178271478036 ps
CPU time 46.09 seconds
Started Feb 08 10:22:55 AM UTC 25
Finished Feb 08 10:23:43 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457460661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.3457460661
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3923209386
Short name T188
Test name
Test status
Simulation time 401017513962 ps
CPU time 1020.28 seconds
Started Feb 08 10:22:57 AM UTC 25
Finished Feb 08 10:40:10 AM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923209386 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.3923209386
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3264723166
Short name T207
Test name
Test status
Simulation time 134932778079 ps
CPU time 806.94 seconds
Started Feb 08 10:23:29 AM UTC 25
Finished Feb 08 10:37:05 AM UTC 25
Peak memory 212996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264723166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3264723166
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2209356282
Short name T39
Test name
Test status
Simulation time 44960778108 ps
CPU time 30.1 seconds
Started Feb 08 10:23:26 AM UTC 25
Finished Feb 08 10:23:58 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209356282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2209356282
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1034520072
Short name T130
Test name
Test status
Simulation time 4677209431 ps
CPU time 7 seconds
Started Feb 08 10:23:26 AM UTC 25
Finished Feb 08 10:23:35 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034520072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1034520072
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.3389438973
Short name T42
Test name
Test status
Simulation time 4452503583 ps
CPU time 20.41 seconds
Started Feb 08 10:23:42 AM UTC 25
Finished Feb 08 10:24:03 AM UTC 25
Peak memory 243820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389438973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3389438973
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2755558951
Short name T28
Test name
Test status
Simulation time 5950503066 ps
CPU time 4.82 seconds
Started Feb 08 10:22:30 AM UTC 25
Finished Feb 08 10:22:36 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755558951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2755558951
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3262194403
Short name T47
Test name
Test status
Simulation time 489544655766 ps
CPU time 1911.76 seconds
Started Feb 08 10:23:35 AM UTC 25
Finished Feb 08 10:55:46 AM UTC 25
Peak memory 212996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262194403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.3262194403
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.614813049
Short name T651
Test name
Test status
Simulation time 367762683 ps
CPU time 2.59 seconds
Started Feb 08 11:21:38 AM UTC 25
Finished Feb 08 11:21:42 AM UTC 25
Peak memory 211752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614813049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.614813049
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1299225688
Short name T343
Test name
Test status
Simulation time 378059823630 ps
CPU time 536.75 seconds
Started Feb 08 11:20:46 AM UTC 25
Finished Feb 08 11:29:50 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299225688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.1299225688
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.3359299108
Short name T730
Test name
Test status
Simulation time 489982345875 ps
CPU time 676.46 seconds
Started Feb 08 11:19:56 AM UTC 25
Finished Feb 08 11:31:21 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359299108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3359299108
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3414715009
Short name T755
Test name
Test status
Simulation time 330163172052 ps
CPU time 925.68 seconds
Started Feb 08 11:19:57 AM UTC 25
Finished Feb 08 11:35:33 AM UTC 25
Peak memory 212580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414715009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.3414715009
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.1777116114
Short name T779
Test name
Test status
Simulation time 490037432610 ps
CPU time 1179.36 seconds
Started Feb 08 11:19:38 AM UTC 25
Finished Feb 08 11:39:30 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777116114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1777116114
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2400806677
Short name T663
Test name
Test status
Simulation time 328962424719 ps
CPU time 212.57 seconds
Started Feb 08 11:19:51 AM UTC 25
Finished Feb 08 11:23:27 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400806677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.2400806677
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1191698892
Short name T344
Test name
Test status
Simulation time 173511089964 ps
CPU time 519.46 seconds
Started Feb 08 11:20:09 AM UTC 25
Finished Feb 08 11:28:55 AM UTC 25
Peak memory 211840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191698892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.1191698892
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2809968821
Short name T681
Test name
Test status
Simulation time 200968284106 ps
CPU time 350.29 seconds
Started Feb 08 11:20:20 AM UTC 25
Finished Feb 08 11:26:15 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809968821 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.2809968821
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3730957409
Short name T720
Test name
Test status
Simulation time 78465134395 ps
CPU time 534.54 seconds
Started Feb 08 11:21:28 AM UTC 25
Finished Feb 08 11:30:29 AM UTC 25
Peak memory 211984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730957409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3730957409
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.3112369331
Short name T653
Test name
Test status
Simulation time 26609202969 ps
CPU time 28.92 seconds
Started Feb 08 11:21:14 AM UTC 25
Finished Feb 08 11:21:45 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112369331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3112369331
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.2715358454
Short name T649
Test name
Test status
Simulation time 3473994761 ps
CPU time 15.52 seconds
Started Feb 08 11:21:09 AM UTC 25
Finished Feb 08 11:21:26 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715358454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2715358454
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.4059166818
Short name T643
Test name
Test status
Simulation time 6037103512 ps
CPU time 14.56 seconds
Started Feb 08 11:19:34 AM UTC 25
Finished Feb 08 11:19:50 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059166818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4059166818
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.686097326
Short name T363
Test name
Test status
Simulation time 587339391135 ps
CPU time 720.57 seconds
Started Feb 08 11:21:29 AM UTC 25
Finished Feb 08 11:33:37 AM UTC 25
Peak memory 221888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686097326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.686097326
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3149178142
Short name T712
Test name
Test status
Simulation time 109786490938 ps
CPU time 493.01 seconds
Started Feb 08 11:21:29 AM UTC 25
Finished Feb 08 11:29:48 AM UTC 25
Peak memory 222104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3149178142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_a
ll_with_rand_reset.3149178142
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.1883366360
Short name T659
Test name
Test status
Simulation time 279449679 ps
CPU time 2.2 seconds
Started Feb 08 11:23:07 AM UTC 25
Finished Feb 08 11:23:10 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883366360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1883366360
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.2805406949
Short name T726
Test name
Test status
Simulation time 179533102099 ps
CPU time 503.89 seconds
Started Feb 08 11:22:29 AM UTC 25
Finished Feb 08 11:30:59 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805406949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2805406949
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.4152997378
Short name T673
Test name
Test status
Simulation time 165407953398 ps
CPU time 170.24 seconds
Started Feb 08 11:22:03 AM UTC 25
Finished Feb 08 11:24:56 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152997378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4152997378
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3806280532
Short name T775
Test name
Test status
Simulation time 321582545086 ps
CPU time 938.59 seconds
Started Feb 08 11:22:09 AM UTC 25
Finished Feb 08 11:37:58 AM UTC 25
Peak memory 212580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806280532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.3806280532
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.815266350
Short name T670
Test name
Test status
Simulation time 328838556716 ps
CPU time 135.59 seconds
Started Feb 08 11:21:43 AM UTC 25
Finished Feb 08 11:24:02 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815266350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.815266350
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.4148704838
Short name T677
Test name
Test status
Simulation time 322069525452 ps
CPU time 211.68 seconds
Started Feb 08 11:21:46 AM UTC 25
Finished Feb 08 11:25:21 AM UTC 25
Peak memory 211552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148704838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.4148704838
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.3704540577
Short name T351
Test name
Test status
Simulation time 386834128134 ps
CPU time 1221.93 seconds
Started Feb 08 11:22:09 AM UTC 25
Finished Feb 08 11:42:44 AM UTC 25
Peak memory 212576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704540577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.3704540577
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3764562789
Short name T786
Test name
Test status
Simulation time 603645436885 ps
CPU time 1373.86 seconds
Started Feb 08 11:22:12 AM UTC 25
Finished Feb 08 11:45:20 AM UTC 25
Peak memory 212656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764562789 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.3764562789
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.2602603601
Short name T736
Test name
Test status
Simulation time 71829852790 ps
CPU time 542.2 seconds
Started Feb 08 11:22:49 AM UTC 25
Finished Feb 08 11:31:58 AM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602603601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2602603601
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.2742652576
Short name T664
Test name
Test status
Simulation time 43739926641 ps
CPU time 48.12 seconds
Started Feb 08 11:22:38 AM UTC 25
Finished Feb 08 11:23:28 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742652576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2742652576
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.831249295
Short name T657
Test name
Test status
Simulation time 4305762305 ps
CPU time 5.69 seconds
Started Feb 08 11:22:30 AM UTC 25
Finished Feb 08 11:22:37 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831249295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.831249295
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.1940196201
Short name T655
Test name
Test status
Simulation time 5546672466 ps
CPU time 26.77 seconds
Started Feb 08 11:21:43 AM UTC 25
Finished Feb 08 11:22:11 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940196201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1940196201
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.353365283
Short name T665
Test name
Test status
Simulation time 9609374474 ps
CPU time 23.7 seconds
Started Feb 08 11:23:06 AM UTC 25
Finished Feb 08 11:23:31 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353365283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.353365283
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4120336241
Short name T701
Test name
Test status
Simulation time 1190696419321 ps
CPU time 336.17 seconds
Started Feb 08 11:23:00 AM UTC 25
Finished Feb 08 11:28:41 AM UTC 25
Peak memory 228448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4120336241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_a
ll_with_rand_reset.4120336241
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.865877909
Short name T671
Test name
Test status
Simulation time 437904747 ps
CPU time 1.31 seconds
Started Feb 08 11:24:21 AM UTC 25
Finished Feb 08 11:24:24 AM UTC 25
Peak memory 209652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865877909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.865877909
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.3045903334
Short name T675
Test name
Test status
Simulation time 322803818283 ps
CPU time 105.22 seconds
Started Feb 08 11:23:19 AM UTC 25
Finished Feb 08 11:25:07 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045903334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3045903334
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2139117799
Short name T771
Test name
Test status
Simulation time 328174915726 ps
CPU time 820.4 seconds
Started Feb 08 11:23:23 AM UTC 25
Finished Feb 08 11:37:14 AM UTC 25
Peak memory 212852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139117799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.2139117799
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.570745141
Short name T678
Test name
Test status
Simulation time 163139705182 ps
CPU time 170.47 seconds
Started Feb 08 11:23:11 AM UTC 25
Finished Feb 08 11:26:04 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570745141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.570745141
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.1648229765
Short name T689
Test name
Test status
Simulation time 315706680025 ps
CPU time 248.81 seconds
Started Feb 08 11:23:18 AM UTC 25
Finished Feb 08 11:27:31 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648229765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.1648229765
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3145735031
Short name T277
Test name
Test status
Simulation time 357217193704 ps
CPU time 319.09 seconds
Started Feb 08 11:23:28 AM UTC 25
Finished Feb 08 11:28:52 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145735031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3145735031
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4251316945
Short name T797
Test name
Test status
Simulation time 597683382432 ps
CPU time 1776.63 seconds
Started Feb 08 11:23:29 AM UTC 25
Finished Feb 08 11:53:24 AM UTC 25
Peak memory 212656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251316945 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.4251316945
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.1096366075
Short name T359
Test name
Test status
Simulation time 88828128858 ps
CPU time 495.94 seconds
Started Feb 08 11:23:42 AM UTC 25
Finished Feb 08 11:32:05 AM UTC 25
Peak memory 211912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096366075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1096366075
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3855897186
Short name T680
Test name
Test status
Simulation time 34134198835 ps
CPU time 150.46 seconds
Started Feb 08 11:23:39 AM UTC 25
Finished Feb 08 11:26:13 AM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855897186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3855897186
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.1061721680
Short name T669
Test name
Test status
Simulation time 2975134521 ps
CPU time 3.01 seconds
Started Feb 08 11:23:37 AM UTC 25
Finished Feb 08 11:23:42 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061721680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1061721680
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.737138879
Short name T661
Test name
Test status
Simulation time 5884618519 ps
CPU time 7.38 seconds
Started Feb 08 11:23:09 AM UTC 25
Finished Feb 08 11:23:18 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737138879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.adc_ctrl_smoke.737138879
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.979289713
Short name T285
Test name
Test status
Simulation time 486544112076 ps
CPU time 1437.98 seconds
Started Feb 08 11:24:02 AM UTC 25
Finished Feb 08 11:48:16 AM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979289713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.979289713
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1043825437
Short name T700
Test name
Test status
Simulation time 99993359849 ps
CPU time 281.6 seconds
Started Feb 08 11:23:54 AM UTC 25
Finished Feb 08 11:28:40 AM UTC 25
Peak memory 228252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1043825437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_a
ll_with_rand_reset.1043825437
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2903910185
Short name T684
Test name
Test status
Simulation time 467031989 ps
CPU time 1.91 seconds
Started Feb 08 11:26:30 AM UTC 25
Finished Feb 08 11:26:33 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903910185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2903910185
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.3890421995
Short name T350
Test name
Test status
Simulation time 340652595123 ps
CPU time 139.03 seconds
Started Feb 08 11:25:12 AM UTC 25
Finished Feb 08 11:27:34 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890421995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.3890421995
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1424111199
Short name T325
Test name
Test status
Simulation time 349987007801 ps
CPU time 239.44 seconds
Started Feb 08 11:25:22 AM UTC 25
Finished Feb 08 11:29:25 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424111199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1424111199
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3326289413
Short name T742
Test name
Test status
Simulation time 163292104778 ps
CPU time 491.54 seconds
Started Feb 08 11:24:57 AM UTC 25
Finished Feb 08 11:33:15 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326289413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.3326289413
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.2778925487
Short name T715
Test name
Test status
Simulation time 332605582811 ps
CPU time 320.39 seconds
Started Feb 08 11:24:34 AM UTC 25
Finished Feb 08 11:29:59 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778925487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2778925487
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1226872006
Short name T713
Test name
Test status
Simulation time 484398912105 ps
CPU time 308.88 seconds
Started Feb 08 11:24:36 AM UTC 25
Finished Feb 08 11:29:49 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226872006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.1226872006
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1344026535
Short name T324
Test name
Test status
Simulation time 577408147161 ps
CPU time 1135.44 seconds
Started Feb 08 11:25:04 AM UTC 25
Finished Feb 08 11:44:11 AM UTC 25
Peak memory 212860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344026535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1344026535
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1024654314
Short name T754
Test name
Test status
Simulation time 191812528090 ps
CPU time 613.18 seconds
Started Feb 08 11:25:08 AM UTC 25
Finished Feb 08 11:35:29 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024654314 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.1024654314
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.2207398931
Short name T774
Test name
Test status
Simulation time 114911293778 ps
CPU time 691.64 seconds
Started Feb 08 11:26:13 AM UTC 25
Finished Feb 08 11:37:53 AM UTC 25
Peak memory 212036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207398931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2207398931
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2524387547
Short name T685
Test name
Test status
Simulation time 24094563007 ps
CPU time 29.4 seconds
Started Feb 08 11:26:07 AM UTC 25
Finished Feb 08 11:26:38 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524387547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2524387547
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.426227692
Short name T682
Test name
Test status
Simulation time 2931281862 ps
CPU time 13.6 seconds
Started Feb 08 11:26:05 AM UTC 25
Finished Feb 08 11:26:20 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426227692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.426227692
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.3143119416
Short name T672
Test name
Test status
Simulation time 6004278601 ps
CPU time 15 seconds
Started Feb 08 11:24:25 AM UTC 25
Finished Feb 08 11:24:41 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143119416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3143119416
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.981252984
Short name T773
Test name
Test status
Simulation time 188336626391 ps
CPU time 655.31 seconds
Started Feb 08 11:26:21 AM UTC 25
Finished Feb 08 11:37:25 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981252984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.981252984
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3623976489
Short name T690
Test name
Test status
Simulation time 25563702487 ps
CPU time 73.54 seconds
Started Feb 08 11:26:16 AM UTC 25
Finished Feb 08 11:27:32 AM UTC 25
Peak memory 221980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3623976489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_a
ll_with_rand_reset.3623976489
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.97769981
Short name T694
Test name
Test status
Simulation time 475113837 ps
CPU time 1.42 seconds
Started Feb 08 11:28:07 AM UTC 25
Finished Feb 08 11:28:10 AM UTC 25
Peak memory 209652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97769981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_
test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.97769981
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.3188464765
Short name T182
Test name
Test status
Simulation time 491235515930 ps
CPU time 382.26 seconds
Started Feb 08 11:27:31 AM UTC 25
Finished Feb 08 11:33:59 AM UTC 25
Peak memory 211776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188464765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.3188464765
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.1883874583
Short name T746
Test name
Test status
Simulation time 168098018483 ps
CPU time 365.41 seconds
Started Feb 08 11:27:33 AM UTC 25
Finished Feb 08 11:33:44 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883874583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1883874583
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.4167774746
Short name T744
Test name
Test status
Simulation time 484667295865 ps
CPU time 385.24 seconds
Started Feb 08 11:26:52 AM UTC 25
Finished Feb 08 11:33:22 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167774746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4167774746
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1262867403
Short name T702
Test name
Test status
Simulation time 171136112608 ps
CPU time 103.1 seconds
Started Feb 08 11:27:00 AM UTC 25
Finished Feb 08 11:28:45 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262867403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.1262867403
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.449914319
Short name T195
Test name
Test status
Simulation time 483356377928 ps
CPU time 317.72 seconds
Started Feb 08 11:26:39 AM UTC 25
Finished Feb 08 11:32:01 AM UTC 25
Peak memory 211784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449914319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.449914319
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.2215485431
Short name T698
Test name
Test status
Simulation time 321099820790 ps
CPU time 107.14 seconds
Started Feb 08 11:26:41 AM UTC 25
Finished Feb 08 11:28:30 AM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215485431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.2215485431
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1356545224
Short name T787
Test name
Test status
Simulation time 404521372808 ps
CPU time 1094.99 seconds
Started Feb 08 11:27:11 AM UTC 25
Finished Feb 08 11:45:37 AM UTC 25
Peak memory 212672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356545224 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.1356545224
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2294671248
Short name T772
Test name
Test status
Simulation time 90683522943 ps
CPU time 573.54 seconds
Started Feb 08 11:27:42 AM UTC 25
Finished Feb 08 11:37:22 AM UTC 25
Peak memory 211908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294671248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2294671248
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1177570598
Short name T692
Test name
Test status
Simulation time 25244330862 ps
CPU time 9.2 seconds
Started Feb 08 11:27:38 AM UTC 25
Finished Feb 08 11:27:49 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177570598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1177570598
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.462408820
Short name T693
Test name
Test status
Simulation time 5245193593 ps
CPU time 14.96 seconds
Started Feb 08 11:27:35 AM UTC 25
Finished Feb 08 11:27:52 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462408820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.462408820
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3434050075
Short name T687
Test name
Test status
Simulation time 5604991181 ps
CPU time 24.09 seconds
Started Feb 08 11:26:34 AM UTC 25
Finished Feb 08 11:26:59 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434050075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3434050075
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.782900230
Short name T739
Test name
Test status
Simulation time 331826236963 ps
CPU time 285.18 seconds
Started Feb 08 11:27:52 AM UTC 25
Finished Feb 08 11:32:42 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782900230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.782900230
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.2799036048
Short name T706
Test name
Test status
Simulation time 544505092 ps
CPU time 1.47 seconds
Started Feb 08 11:29:23 AM UTC 25
Finished Feb 08 11:29:26 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799036048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2799036048
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.149371984
Short name T748
Test name
Test status
Simulation time 163597850486 ps
CPU time 340.46 seconds
Started Feb 08 11:28:42 AM UTC 25
Finished Feb 08 11:34:27 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149371984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.149371984
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.3090991200
Short name T760
Test name
Test status
Simulation time 169692741421 ps
CPU time 411.4 seconds
Started Feb 08 11:28:46 AM UTC 25
Finished Feb 08 11:35:43 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090991200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3090991200
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.3745090535
Short name T731
Test name
Test status
Simulation time 326036549256 ps
CPU time 194.16 seconds
Started Feb 08 11:28:27 AM UTC 25
Finished Feb 08 11:31:44 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745090535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3745090535
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.885735811
Short name T732
Test name
Test status
Simulation time 160182022522 ps
CPU time 191.32 seconds
Started Feb 08 11:28:31 AM UTC 25
Finished Feb 08 11:31:46 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885735811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.885735811
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.1343429479
Short name T792
Test name
Test status
Simulation time 484719444373 ps
CPU time 1239.64 seconds
Started Feb 08 11:28:21 AM UTC 25
Finished Feb 08 11:49:13 AM UTC 25
Peak memory 212944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343429479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1343429479
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.3531244842
Short name T759
Test name
Test status
Simulation time 329120597716 ps
CPU time 428.51 seconds
Started Feb 08 11:28:25 AM UTC 25
Finished Feb 08 11:35:39 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531244842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.3531244842
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.1587762738
Short name T196
Test name
Test status
Simulation time 380290239074 ps
CPU time 255.99 seconds
Started Feb 08 11:28:35 AM UTC 25
Finished Feb 08 11:32:55 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587762738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.1587762738
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2778732158
Short name T737
Test name
Test status
Simulation time 611787216244 ps
CPU time 210.84 seconds
Started Feb 08 11:28:41 AM UTC 25
Finished Feb 08 11:32:16 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778732158 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2778732158
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.3423017644
Short name T767
Test name
Test status
Simulation time 75325265207 ps
CPU time 441.71 seconds
Started Feb 08 11:29:15 AM UTC 25
Finished Feb 08 11:36:42 AM UTC 25
Peak memory 211844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423017644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3423017644
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2649517942
Short name T705
Test name
Test status
Simulation time 37084533467 ps
CPU time 24.86 seconds
Started Feb 08 11:28:56 AM UTC 25
Finished Feb 08 11:29:23 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649517942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2649517942
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.2231552632
Short name T704
Test name
Test status
Simulation time 5322091586 ps
CPU time 25.15 seconds
Started Feb 08 11:28:53 AM UTC 25
Finished Feb 08 11:29:20 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231552632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2231552632
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.2738378041
Short name T699
Test name
Test status
Simulation time 5960424542 ps
CPU time 20.69 seconds
Started Feb 08 11:28:12 AM UTC 25
Finished Feb 08 11:28:34 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738378041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2738378041
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.393939107
Short name T312
Test name
Test status
Simulation time 235614421609 ps
CPU time 448.11 seconds
Started Feb 08 11:29:21 AM UTC 25
Finished Feb 08 11:36:55 AM UTC 25
Peak memory 221964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393939107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.393939107
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2237475592
Short name T283
Test name
Test status
Simulation time 71168941238 ps
CPU time 32.32 seconds
Started Feb 08 11:29:16 AM UTC 25
Finished Feb 08 11:29:50 AM UTC 25
Peak memory 221696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2237475592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_a
ll_with_rand_reset.2237475592
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1560606919
Short name T717
Test name
Test status
Simulation time 457764808 ps
CPU time 2.96 seconds
Started Feb 08 11:29:59 AM UTC 25
Finished Feb 08 11:30:04 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560606919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1560606919
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.4080774469
Short name T181
Test name
Test status
Simulation time 171730489360 ps
CPU time 39.16 seconds
Started Feb 08 11:29:44 AM UTC 25
Finished Feb 08 11:30:25 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080774469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.4080774469
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.3533172615
Short name T798
Test name
Test status
Simulation time 539582747726 ps
CPU time 1435.84 seconds
Started Feb 08 11:29:48 AM UTC 25
Finished Feb 08 11:53:58 AM UTC 25
Peak memory 212636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533172615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3533172615
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.4211305393
Short name T788
Test name
Test status
Simulation time 492252194044 ps
CPU time 1025.53 seconds
Started Feb 08 11:29:28 AM UTC 25
Finished Feb 08 11:46:45 AM UTC 25
Peak memory 212800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211305393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4211305393
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3296827269
Short name T724
Test name
Test status
Simulation time 320663780700 ps
CPU time 77.92 seconds
Started Feb 08 11:29:32 AM UTC 25
Finished Feb 08 11:30:52 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296827269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.3296827269
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.588561646
Short name T796
Test name
Test status
Simulation time 491126274877 ps
CPU time 1356.18 seconds
Started Feb 08 11:29:26 AM UTC 25
Finished Feb 08 11:52:17 AM UTC 25
Peak memory 212804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588561646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.588561646
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3469184937
Short name T734
Test name
Test status
Simulation time 162956872283 ps
CPU time 141.39 seconds
Started Feb 08 11:29:28 AM UTC 25
Finished Feb 08 11:31:52 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469184937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.3469184937
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.2793862409
Short name T735
Test name
Test status
Simulation time 201507429577 ps
CPU time 130.34 seconds
Started Feb 08 11:29:39 AM UTC 25
Finished Feb 08 11:31:52 AM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793862409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.2793862409
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3725211624
Short name T780
Test name
Test status
Simulation time 206772546043 ps
CPU time 612.41 seconds
Started Feb 08 11:29:40 AM UTC 25
Finished Feb 08 11:40:00 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725211624 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.3725211624
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.1263981493
Short name T763
Test name
Test status
Simulation time 82777375627 ps
CPU time 370.67 seconds
Started Feb 08 11:29:50 AM UTC 25
Finished Feb 08 11:36:05 AM UTC 25
Peak memory 211912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263981493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1263981493
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.525898171
Short name T721
Test name
Test status
Simulation time 40125804095 ps
CPU time 45.23 seconds
Started Feb 08 11:29:50 AM UTC 25
Finished Feb 08 11:30:37 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525898171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.525898171
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.4036918565
Short name T716
Test name
Test status
Simulation time 4269947643 ps
CPU time 9.53 seconds
Started Feb 08 11:29:49 AM UTC 25
Finished Feb 08 11:30:00 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036918565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4036918565
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.1342359454
Short name T710
Test name
Test status
Simulation time 6012237412 ps
CPU time 15.87 seconds
Started Feb 08 11:29:25 AM UTC 25
Finished Feb 08 11:29:43 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342359454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1342359454
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.827785040
Short name T719
Test name
Test status
Simulation time 6117162341 ps
CPU time 25.46 seconds
Started Feb 08 11:29:57 AM UTC 25
Finished Feb 08 11:30:24 AM UTC 25
Peak memory 211412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827785040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.827785040
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3838200491
Short name T723
Test name
Test status
Simulation time 51905438952 ps
CPU time 55.39 seconds
Started Feb 08 11:29:51 AM UTC 25
Finished Feb 08 11:30:49 AM UTC 25
Peak memory 221696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3838200491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_a
ll_with_rand_reset.3838200491
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.1499346858
Short name T729
Test name
Test status
Simulation time 355795567 ps
CPU time 2.56 seconds
Started Feb 08 11:31:16 AM UTC 25
Finished Feb 08 11:31:20 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499346858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1499346858
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1869716716
Short name T749
Test name
Test status
Simulation time 339655789878 ps
CPU time 226.91 seconds
Started Feb 08 11:30:38 AM UTC 25
Finished Feb 08 11:34:28 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869716716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.1869716716
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2946726733
Short name T769
Test name
Test status
Simulation time 356926856808 ps
CPU time 366.48 seconds
Started Feb 08 11:30:43 AM UTC 25
Finished Feb 08 11:36:55 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946726733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2946726733
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.283194738
Short name T765
Test name
Test status
Simulation time 164638731463 ps
CPU time 374.11 seconds
Started Feb 08 11:30:17 AM UTC 25
Finished Feb 08 11:36:37 AM UTC 25
Peak memory 211908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283194738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.283194738
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4046730407
Short name T750
Test name
Test status
Simulation time 159485647186 ps
CPU time 239.9 seconds
Started Feb 08 11:30:26 AM UTC 25
Finished Feb 08 11:34:29 AM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046730407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.4046730407
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.196201461
Short name T183
Test name
Test status
Simulation time 482473101299 ps
CPU time 258.44 seconds
Started Feb 08 11:30:04 AM UTC 25
Finished Feb 08 11:34:27 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196201461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.196201461
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.157041549
Short name T777
Test name
Test status
Simulation time 161782923523 ps
CPU time 461.71 seconds
Started Feb 08 11:30:16 AM UTC 25
Finished Feb 08 11:38:04 AM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157041549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.157041549
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.2824607063
Short name T776
Test name
Test status
Simulation time 667281143577 ps
CPU time 450.01 seconds
Started Feb 08 11:30:26 AM UTC 25
Finished Feb 08 11:38:01 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824607063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.2824607063
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3855089979
Short name T800
Test name
Test status
Simulation time 620408712654 ps
CPU time 1937.27 seconds
Started Feb 08 11:30:30 AM UTC 25
Finished Feb 08 12:03:07 PM UTC 25
Peak memory 212988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855089979 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.3855089979
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.4055439703
Short name T793
Test name
Test status
Simulation time 142024855557 ps
CPU time 1112.06 seconds
Started Feb 08 11:30:56 AM UTC 25
Finished Feb 08 11:49:40 AM UTC 25
Peak memory 212940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055439703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4055439703
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.1455505763
Short name T728
Test name
Test status
Simulation time 25929542337 ps
CPU time 20.69 seconds
Started Feb 08 11:30:53 AM UTC 25
Finished Feb 08 11:31:15 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455505763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1455505763
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.465198595
Short name T727
Test name
Test status
Simulation time 4179428104 ps
CPU time 14.63 seconds
Started Feb 08 11:30:50 AM UTC 25
Finished Feb 08 11:31:06 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465198595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.465198595
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.3736026374
Short name T718
Test name
Test status
Simulation time 5912529734 ps
CPU time 15.08 seconds
Started Feb 08 11:30:00 AM UTC 25
Finished Feb 08 11:30:17 AM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736026374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3736026374
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.296296641
Short name T789
Test name
Test status
Simulation time 335064002347 ps
CPU time 948.07 seconds
Started Feb 08 11:31:07 AM UTC 25
Finished Feb 08 11:47:05 AM UTC 25
Peak memory 212576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296296641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.296296641
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.2989837290
Short name T740
Test name
Test status
Simulation time 400157031 ps
CPU time 2.7 seconds
Started Feb 08 11:32:56 AM UTC 25
Finished Feb 08 11:33:00 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989837290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2989837290
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1462710714
Short name T298
Test name
Test status
Simulation time 324954063195 ps
CPU time 295.25 seconds
Started Feb 08 11:31:59 AM UTC 25
Finished Feb 08 11:36:59 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462710714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.1462710714
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.1318118784
Short name T758
Test name
Test status
Simulation time 317691258498 ps
CPU time 227.99 seconds
Started Feb 08 11:31:46 AM UTC 25
Finished Feb 08 11:35:38 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318118784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1318118784
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1326165917
Short name T753
Test name
Test status
Simulation time 162242734790 ps
CPU time 190.72 seconds
Started Feb 08 11:31:50 AM UTC 25
Finished Feb 08 11:35:05 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326165917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.1326165917
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.400593658
Short name T799
Test name
Test status
Simulation time 486925774656 ps
CPU time 1372.51 seconds
Started Feb 08 11:31:21 AM UTC 25
Finished Feb 08 11:54:28 AM UTC 25
Peak memory 212676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400593658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.400593658
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.2267784331
Short name T781
Test name
Test status
Simulation time 488527801997 ps
CPU time 516.15 seconds
Started Feb 08 11:31:45 AM UTC 25
Finished Feb 08 11:40:28 AM UTC 25
Peak memory 211800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267784331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.2267784331
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.2985144993
Short name T791
Test name
Test status
Simulation time 405119220322 ps
CPU time 1011.33 seconds
Started Feb 08 11:31:52 AM UTC 25
Finished Feb 08 11:48:55 AM UTC 25
Peak memory 212524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985144993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.2985144993
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3325155936
Short name T768
Test name
Test status
Simulation time 210395511432 ps
CPU time 292.32 seconds
Started Feb 08 11:31:52 AM UTC 25
Finished Feb 08 11:36:49 AM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325155936 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3325155936
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3002401074
Short name T782
Test name
Test status
Simulation time 90070865001 ps
CPU time 552.31 seconds
Started Feb 08 11:32:17 AM UTC 25
Finished Feb 08 11:41:35 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002401074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3002401074
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.1840098560
Short name T756
Test name
Test status
Simulation time 43959300093 ps
CPU time 203.94 seconds
Started Feb 08 11:32:07 AM UTC 25
Finished Feb 08 11:35:34 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840098560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1840098560
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.239896905
Short name T738
Test name
Test status
Simulation time 3068403411 ps
CPU time 13.21 seconds
Started Feb 08 11:32:06 AM UTC 25
Finished Feb 08 11:32:20 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239896905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.239896905
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.1668327008
Short name T733
Test name
Test status
Simulation time 5986594904 ps
CPU time 26.79 seconds
Started Feb 08 11:31:21 AM UTC 25
Finished Feb 08 11:31:50 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668327008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1668327008
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.3750913697
Short name T795
Test name
Test status
Simulation time 339162038402 ps
CPU time 1039.38 seconds
Started Feb 08 11:32:43 AM UTC 25
Finished Feb 08 11:50:15 AM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750913697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.3750913697
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.4278751795
Short name T751
Test name
Test status
Simulation time 333234189 ps
CPU time 1.29 seconds
Started Feb 08 11:34:29 AM UTC 25
Finished Feb 08 11:34:32 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278751795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.4278751795
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.834872266
Short name T766
Test name
Test status
Simulation time 163543042950 ps
CPU time 158.07 seconds
Started Feb 08 11:34:00 AM UTC 25
Finished Feb 08 11:36:40 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834872266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.834872266
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.4270252884
Short name T240
Test name
Test status
Simulation time 159985121674 ps
CPU time 99.78 seconds
Started Feb 08 11:33:17 AM UTC 25
Finished Feb 08 11:34:59 AM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270252884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4270252884
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1635289408
Short name T785
Test name
Test status
Simulation time 327629957087 ps
CPU time 649.95 seconds
Started Feb 08 11:33:23 AM UTC 25
Finished Feb 08 11:44:21 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635289408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.1635289408
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.2589225153
Short name T794
Test name
Test status
Simulation time 333109386864 ps
CPU time 1013.78 seconds
Started Feb 08 11:33:08 AM UTC 25
Finished Feb 08 11:50:13 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589225153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2589225153
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.4048972355
Short name T752
Test name
Test status
Simulation time 163492705467 ps
CPU time 101.53 seconds
Started Feb 08 11:33:15 AM UTC 25
Finished Feb 08 11:34:59 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048972355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.4048972355
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.437846273
Short name T184
Test name
Test status
Simulation time 569078404380 ps
CPU time 128.85 seconds
Started Feb 08 11:33:38 AM UTC 25
Finished Feb 08 11:35:50 AM UTC 25
Peak memory 211776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437846273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ad
c_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.437846273
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2443445297
Short name T762
Test name
Test status
Simulation time 201541679291 ps
CPU time 139.16 seconds
Started Feb 08 11:33:39 AM UTC 25
Finished Feb 08 11:36:02 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443445297 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.2443445297
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.2153034620
Short name T778
Test name
Test status
Simulation time 78108320274 ps
CPU time 255.44 seconds
Started Feb 08 11:34:24 AM UTC 25
Finished Feb 08 11:38:42 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153034620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2153034620
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.2836540822
Short name T764
Test name
Test status
Simulation time 42660628595 ps
CPU time 120.21 seconds
Started Feb 08 11:34:22 AM UTC 25
Finished Feb 08 11:36:25 AM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836540822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2836540822
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.1640316364
Short name T747
Test name
Test status
Simulation time 4904369057 ps
CPU time 11.4 seconds
Started Feb 08 11:34:08 AM UTC 25
Finished Feb 08 11:34:20 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640316364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1640316364
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.3078830237
Short name T743
Test name
Test status
Simulation time 5952284431 ps
CPU time 14.13 seconds
Started Feb 08 11:33:01 AM UTC 25
Finished Feb 08 11:33:17 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078830237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3078830237
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.4261224468
Short name T784
Test name
Test status
Simulation time 326388393088 ps
CPU time 556.06 seconds
Started Feb 08 11:34:28 AM UTC 25
Finished Feb 08 11:43:50 AM UTC 25
Peak memory 212104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261224468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.4261224468
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2330829714
Short name T770
Test name
Test status
Simulation time 45517366103 ps
CPU time 149.2 seconds
Started Feb 08 11:34:28 AM UTC 25
Finished Feb 08 11:37:00 AM UTC 25
Peak memory 221908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2330829714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_a
ll_with_rand_reset.2330829714
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.2265785377
Short name T148
Test name
Test status
Simulation time 352787995 ps
CPU time 1.34 seconds
Started Feb 08 10:25:15 AM UTC 25
Finished Feb 08 10:25:17 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265785377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2265785377
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3611297256
Short name T153
Test name
Test status
Simulation time 163970250798 ps
CPU time 110.49 seconds
Started Feb 08 10:24:26 AM UTC 25
Finished Feb 08 10:26:19 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611297256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.3611297256
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2467188177
Short name T243
Test name
Test status
Simulation time 165473796636 ps
CPU time 295.02 seconds
Started Feb 08 10:24:33 AM UTC 25
Finished Feb 08 10:29:33 AM UTC 25
Peak memory 211776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467188177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2467188177
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2335273980
Short name T237
Test name
Test status
Simulation time 166819033445 ps
CPU time 438.28 seconds
Started Feb 08 10:24:01 AM UTC 25
Finished Feb 08 10:31:25 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335273980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2335273980
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2376781803
Short name T270
Test name
Test status
Simulation time 493706873786 ps
CPU time 162.69 seconds
Started Feb 08 10:24:03 AM UTC 25
Finished Feb 08 10:26:49 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376781803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.2376781803
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.217566644
Short name T452
Test name
Test status
Simulation time 499251016457 ps
CPU time 1637.7 seconds
Started Feb 08 10:23:59 AM UTC 25
Finished Feb 08 10:51:34 AM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217566644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.217566644
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3018985215
Short name T229
Test name
Test status
Simulation time 175836900689 ps
CPU time 467.32 seconds
Started Feb 08 10:24:04 AM UTC 25
Finished Feb 08 10:31:57 AM UTC 25
Peak memory 211572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018985215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.3018985215
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1623122662
Short name T403
Test name
Test status
Simulation time 605723606190 ps
CPU time 781.38 seconds
Started Feb 08 10:24:08 AM UTC 25
Finished Feb 08 10:37:18 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623122662 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.1623122662
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4018468480
Short name T210
Test name
Test status
Simulation time 73501903143 ps
CPU time 433.95 seconds
Started Feb 08 10:24:44 AM UTC 25
Finished Feb 08 10:32:04 AM UTC 25
Peak memory 211976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018468480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4018468480
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1487518164
Short name T150
Test name
Test status
Simulation time 44329856188 ps
CPU time 54.16 seconds
Started Feb 08 10:24:40 AM UTC 25
Finished Feb 08 10:25:37 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487518164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1487518164
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2713578097
Short name T44
Test name
Test status
Simulation time 4710031192 ps
CPU time 2.48 seconds
Started Feb 08 10:24:35 AM UTC 25
Finished Feb 08 10:24:39 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713578097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2713578097
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1266025140
Short name T40
Test name
Test status
Simulation time 5778670487 ps
CPU time 13.6 seconds
Started Feb 08 10:23:45 AM UTC 25
Finished Feb 08 10:24:00 AM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266025140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1266025140
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3375265934
Short name T244
Test name
Test status
Simulation time 516005627640 ps
CPU time 1270.12 seconds
Started Feb 08 10:25:04 AM UTC 25
Finished Feb 08 10:46:28 AM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375265934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.3375265934
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.123500008
Short name T364
Test name
Test status
Simulation time 357786654 ps
CPU time 2.52 seconds
Started Feb 08 10:26:50 AM UTC 25
Finished Feb 08 10:26:54 AM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123500008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.123500008
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1560741882
Short name T135
Test name
Test status
Simulation time 363283729468 ps
CPU time 235.62 seconds
Started Feb 08 10:26:11 AM UTC 25
Finished Feb 08 10:30:11 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560741882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.1560741882
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2089687507
Short name T160
Test name
Test status
Simulation time 163838101776 ps
CPU time 78.64 seconds
Started Feb 08 10:26:19 AM UTC 25
Finished Feb 08 10:27:41 AM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089687507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2089687507
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1875545348
Short name T370
Test name
Test status
Simulation time 334523314351 ps
CPU time 131.88 seconds
Started Feb 08 10:25:38 AM UTC 25
Finished Feb 08 10:27:53 AM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875545348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.1875545348
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.3333421942
Short name T230
Test name
Test status
Simulation time 165278972479 ps
CPU time 134.84 seconds
Started Feb 08 10:25:19 AM UTC 25
Finished Feb 08 10:27:37 AM UTC 25
Peak memory 211768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333421942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3333421942
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.190641651
Short name T365
Test name
Test status
Simulation time 165684047962 ps
CPU time 110.46 seconds
Started Feb 08 10:25:20 AM UTC 25
Finished Feb 08 10:27:13 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190641651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.190641651
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1557366674
Short name T381
Test name
Test status
Simulation time 404495002886 ps
CPU time 218.34 seconds
Started Feb 08 10:25:56 AM UTC 25
Finished Feb 08 10:29:39 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557366674 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.1557366674
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.2320116839
Short name T374
Test name
Test status
Simulation time 31831851665 ps
CPU time 136.22 seconds
Started Feb 08 10:26:26 AM UTC 25
Finished Feb 08 10:28:45 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320116839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2320116839
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.4021861558
Short name T201
Test name
Test status
Simulation time 3602821914 ps
CPU time 4.72 seconds
Started Feb 08 10:26:20 AM UTC 25
Finished Feb 08 10:26:27 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021861558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4021861558
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2128484967
Short name T149
Test name
Test status
Simulation time 5764494887 ps
CPU time 6.89 seconds
Started Feb 08 10:25:18 AM UTC 25
Finished Feb 08 10:25:26 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128484967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2128484967
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3649579383
Short name T51
Test name
Test status
Simulation time 468148894168 ps
CPU time 247.6 seconds
Started Feb 08 10:26:28 AM UTC 25
Finished Feb 08 10:30:39 AM UTC 25
Peak memory 221584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3649579383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_al
l_with_rand_reset.3649579383
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.680335589
Short name T371
Test name
Test status
Simulation time 353085817 ps
CPU time 1.13 seconds
Started Feb 08 10:27:54 AM UTC 25
Finished Feb 08 10:27:57 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680335589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.680335589
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.526359404
Short name T222
Test name
Test status
Simulation time 162263327267 ps
CPU time 18.06 seconds
Started Feb 08 10:27:27 AM UTC 25
Finished Feb 08 10:27:47 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526359404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.526359404
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1662232172
Short name T249
Test name
Test status
Simulation time 161506232112 ps
CPU time 500.92 seconds
Started Feb 08 10:27:38 AM UTC 25
Finished Feb 08 10:36:05 AM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662232172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1662232172
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1660353051
Short name T317
Test name
Test status
Simulation time 493863749944 ps
CPU time 1013.4 seconds
Started Feb 08 10:27:14 AM UTC 25
Finished Feb 08 10:44:19 AM UTC 25
Peak memory 212592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660353051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1660353051
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1189914585
Short name T202
Test name
Test status
Simulation time 490145783850 ps
CPU time 462.41 seconds
Started Feb 08 10:27:21 AM UTC 25
Finished Feb 08 10:35:10 AM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189914585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.1189914585
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.2542277459
Short name T106
Test name
Test status
Simulation time 164841325248 ps
CPU time 246.01 seconds
Started Feb 08 10:27:05 AM UTC 25
Finished Feb 08 10:31:15 AM UTC 25
Peak memory 211720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542277459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2542277459
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.221878965
Short name T375
Test name
Test status
Simulation time 168162035194 ps
CPU time 118.16 seconds
Started Feb 08 10:27:10 AM UTC 25
Finished Feb 08 10:29:11 AM UTC 25
Peak memory 211636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221878965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UV
M_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.221878965
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.2157107798
Short name T173
Test name
Test status
Simulation time 184247171717 ps
CPU time 63.66 seconds
Started Feb 08 10:27:22 AM UTC 25
Finished Feb 08 10:28:28 AM UTC 25
Peak memory 211564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157107798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.2157107798
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4186171284
Short name T391
Test name
Test status
Simulation time 397043583983 ps
CPU time 396.12 seconds
Started Feb 08 10:27:23 AM UTC 25
Finished Feb 08 10:34:04 AM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186171284 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.4186171284
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.1717537394
Short name T61
Test name
Test status
Simulation time 81807912488 ps
CPU time 383.71 seconds
Started Feb 08 10:27:42 AM UTC 25
Finished Feb 08 10:34:10 AM UTC 25
Peak memory 212028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717537394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1717537394
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1310870458
Short name T380
Test name
Test status
Simulation time 32798992389 ps
CPU time 104.18 seconds
Started Feb 08 10:27:41 AM UTC 25
Finished Feb 08 10:29:27 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310870458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1310870458
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.986251392
Short name T369
Test name
Test status
Simulation time 5231697207 ps
CPU time 6.71 seconds
Started Feb 08 10:27:38 AM UTC 25
Finished Feb 08 10:27:46 AM UTC 25
Peak memory 211424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986251392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.986251392
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.95330037
Short name T366
Test name
Test status
Simulation time 5795994044 ps
CPU time 25.07 seconds
Started Feb 08 10:26:55 AM UTC 25
Finished Feb 08 10:27:22 AM UTC 25
Peak memory 211620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95330037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.adc_ctrl_smoke.95330037
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3813785720
Short name T310
Test name
Test status
Simulation time 463265987229 ps
CPU time 2139.72 seconds
Started Feb 08 10:27:49 AM UTC 25
Finished Feb 08 11:03:51 AM UTC 25
Peak memory 223232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813785720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.3813785720
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.2877999006
Short name T379
Test name
Test status
Simulation time 525719376 ps
CPU time 1.09 seconds
Started Feb 08 10:29:22 AM UTC 25
Finished Feb 08 10:29:25 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877999006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2877999006
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.3853635302
Short name T256
Test name
Test status
Simulation time 491679652307 ps
CPU time 870.92 seconds
Started Feb 08 10:28:56 AM UTC 25
Finished Feb 08 10:43:36 AM UTC 25
Peak memory 211492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853635302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.3853635302
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3226950114
Short name T155
Test name
Test status
Simulation time 331161523226 ps
CPU time 404.14 seconds
Started Feb 08 10:28:29 AM UTC 25
Finished Feb 08 10:35:19 AM UTC 25
Peak memory 211592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226950114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3226950114
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.89663999
Short name T396
Test name
Test status
Simulation time 328443108992 ps
CPU time 433.3 seconds
Started Feb 08 10:28:45 AM UTC 25
Finished Feb 08 10:36:04 AM UTC 25
Peak memory 211468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89663999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM
_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.89663999
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2334780614
Short name T193
Test name
Test status
Simulation time 485102002793 ps
CPU time 1042.73 seconds
Started Feb 08 10:28:08 AM UTC 25
Finished Feb 08 10:45:42 AM UTC 25
Peak memory 212616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334780614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2334780614
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1166340793
Short name T384
Test name
Test status
Simulation time 163314877518 ps
CPU time 184.83 seconds
Started Feb 08 10:28:16 AM UTC 25
Finished Feb 08 10:31:24 AM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166340793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.1166340793
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2852710461
Short name T250
Test name
Test status
Simulation time 591577184997 ps
CPU time 409.86 seconds
Started Feb 08 10:28:45 AM UTC 25
Finished Feb 08 10:35:41 AM UTC 25
Peak memory 211056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852710461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.2852710461
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.757250416
Short name T438
Test name
Test status
Simulation time 607767642848 ps
CPU time 1153.04 seconds
Started Feb 08 10:28:45 AM UTC 25
Finished Feb 08 10:48:12 AM UTC 25
Peak memory 212276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757250416 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.757250416
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2678969006
Short name T185
Test name
Test status
Simulation time 106651993292 ps
CPU time 639.24 seconds
Started Feb 08 10:29:14 AM UTC 25
Finished Feb 08 10:40:00 AM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678969006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2678969006
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.45271631
Short name T385
Test name
Test status
Simulation time 36803472660 ps
CPU time 145.74 seconds
Started Feb 08 10:29:13 AM UTC 25
Finished Feb 08 10:31:41 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45271631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.45271631
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1067315987
Short name T378
Test name
Test status
Simulation time 4830298067 ps
CPU time 5.55 seconds
Started Feb 08 10:29:12 AM UTC 25
Finished Feb 08 10:29:19 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067315987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1067315987
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1444392077
Short name T372
Test name
Test status
Simulation time 5901157282 ps
CPU time 7.48 seconds
Started Feb 08 10:27:58 AM UTC 25
Finished Feb 08 10:28:07 AM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444392077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1444392077
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.2182810651
Short name T271
Test name
Test status
Simulation time 375782908599 ps
CPU time 1138.68 seconds
Started Feb 08 10:29:20 AM UTC 25
Finished Feb 08 10:48:31 AM UTC 25
Peak memory 212580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182810651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.2182810651
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1481003467
Short name T31
Test name
Test status
Simulation time 62702964676 ps
CPU time 198.14 seconds
Started Feb 08 10:29:18 AM UTC 25
Finished Feb 08 10:32:39 AM UTC 25
Peak memory 221688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1481003467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_al
l_with_rand_reset.1481003467
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.120514122
Short name T103
Test name
Test status
Simulation time 563471822 ps
CPU time 1.21 seconds
Started Feb 08 10:30:56 AM UTC 25
Finished Feb 08 10:30:59 AM UTC 25
Peak memory 209656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120514122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base
_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.120514122
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.570361479
Short name T107
Test name
Test status
Simulation time 168122199538 ps
CPU time 64.86 seconds
Started Feb 08 10:30:14 AM UTC 25
Finished Feb 08 10:31:21 AM UTC 25
Peak memory 211848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570361479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.570361479
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.2917834473
Short name T192
Test name
Test status
Simulation time 192749198673 ps
CPU time 182.84 seconds
Started Feb 08 10:30:21 AM UTC 25
Finished Feb 08 10:33:27 AM UTC 25
Peak memory 211520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917834473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2917834473
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.394320279
Short name T238
Test name
Test status
Simulation time 327418327896 ps
CPU time 339.84 seconds
Started Feb 08 10:29:40 AM UTC 25
Finished Feb 08 10:35:25 AM UTC 25
Peak memory 211772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394320279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ct
rl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.394320279
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3471507646
Short name T445
Test name
Test status
Simulation time 492019597383 ps
CPU time 1234.61 seconds
Started Feb 08 10:29:55 AM UTC 25
Finished Feb 08 10:50:44 AM UTC 25
Peak memory 212732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471507646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.3471507646
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1913167114
Short name T228
Test name
Test status
Simulation time 338140744212 ps
CPU time 505 seconds
Started Feb 08 10:29:28 AM UTC 25
Finished Feb 08 10:38:00 AM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913167114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1913167114
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1962019557
Short name T423
Test name
Test status
Simulation time 328578531829 ps
CPU time 899.22 seconds
Started Feb 08 10:29:34 AM UTC 25
Finished Feb 08 10:44:44 AM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962019557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +U
VM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.1962019557
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3063435877
Short name T246
Test name
Test status
Simulation time 521326517146 ps
CPU time 1445.83 seconds
Started Feb 08 10:29:59 AM UTC 25
Finished Feb 08 10:54:21 AM UTC 25
Peak memory 212584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063435877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a
dc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.3063435877
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3414713202
Short name T174
Test name
Test status
Simulation time 405663307230 ps
CPU time 347.88 seconds
Started Feb 08 10:30:11 AM UTC 25
Finished Feb 08 10:36:04 AM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414713202 -assert nopostproc +UVM_TE
STNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.3414713202
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.34127373
Short name T191
Test name
Test status
Simulation time 109138849975 ps
CPU time 620.49 seconds
Started Feb 08 10:30:40 AM UTC 25
Finished Feb 08 10:41:08 AM UTC 25
Peak memory 211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34127373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctr
l_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.34127373
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3541258494
Short name T104
Test name
Test status
Simulation time 40215557612 ps
CPU time 32.03 seconds
Started Feb 08 10:30:35 AM UTC 25
Finished Feb 08 10:31:09 AM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541258494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3541258494
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3499447640
Short name T101
Test name
Test status
Simulation time 4664389890 ps
CPU time 17.29 seconds
Started Feb 08 10:30:32 AM UTC 25
Finished Feb 08 10:30:51 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499447640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3499447640
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2860523190
Short name T382
Test name
Test status
Simulation time 5957966921 ps
CPU time 26.88 seconds
Started Feb 08 10:29:26 AM UTC 25
Finished Feb 08 10:29:54 AM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860523190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2860523190
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1389895212
Short name T293
Test name
Test status
Simulation time 387765296865 ps
CPU time 891.53 seconds
Started Feb 08 10:30:52 AM UTC 25
Finished Feb 08 10:45:54 AM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389895212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.1389895212
Directory /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest
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