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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.07 96.67 100.00 100.00 98.82 98.33 90.82


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T792 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.67076769 Oct 14 11:30:10 PM UTC 24 Oct 14 11:59:46 PM UTC 24 620781224226 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4227475976 Oct 14 11:37:24 PM UTC 24 Oct 15 12:01:00 AM UTC 24 489936371483 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1198570067 Oct 14 11:38:50 PM UTC 24 Oct 15 12:09:22 AM UTC 24 601566804782 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2884828031 Oct 14 11:19:59 PM UTC 24 Oct 15 12:38:54 AM UTC 24 2537496390149 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1610527095 Oct 15 12:27:01 AM UTC 24 Oct 15 12:27:04 AM UTC 24 548635049 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1545914176 Oct 15 12:26:58 AM UTC 24 Oct 15 12:27:04 AM UTC 24 550218287 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.910633003 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:11 AM UTC 24 565399744 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2891121108 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:12 AM UTC 24 758044453 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4112076670 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:12 AM UTC 24 1024927637 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.511190378 Oct 15 12:27:00 AM UTC 24 Oct 15 12:27:13 AM UTC 24 7573721278 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.820680448 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:14 AM UTC 24 4803506988 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3388919676 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:14 AM UTC 24 614877314 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.979174123 Oct 15 12:27:51 AM UTC 24 Oct 15 12:27:56 AM UTC 24 439722776 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3075748144 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:14 AM UTC 24 610109268 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3349181342 Oct 15 12:27:12 AM UTC 24 Oct 15 12:27:15 AM UTC 24 413072450 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1419015489 Oct 15 12:27:12 AM UTC 24 Oct 15 12:27:16 AM UTC 24 439802267 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.907685585 Oct 15 12:27:12 AM UTC 24 Oct 15 12:27:16 AM UTC 24 1141131189 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2927795506 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:18 AM UTC 24 347264438 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3281244784 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:19 AM UTC 24 554302436 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.459162300 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:20 AM UTC 24 477009580 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1238070892 Oct 15 12:27:17 AM UTC 24 Oct 15 12:27:20 AM UTC 24 458268970 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1744953135 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:20 AM UTC 24 639002889 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2946396862 Oct 15 12:27:19 AM UTC 24 Oct 15 12:27:23 AM UTC 24 1936605448 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3828962806 Oct 15 12:27:19 AM UTC 24 Oct 15 12:27:24 AM UTC 24 1180570480 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3935043699 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:24 AM UTC 24 1127323205 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2498672822 Oct 15 12:27:20 AM UTC 24 Oct 15 12:27:24 AM UTC 24 538294037 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1975182538 Oct 15 12:27:20 AM UTC 24 Oct 15 12:27:25 AM UTC 24 550932369 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3203538639 Oct 15 12:27:25 AM UTC 24 Oct 15 12:27:56 AM UTC 24 27167631521 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3168397311 Oct 15 12:27:23 AM UTC 24 Oct 15 12:27:27 AM UTC 24 468788850 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2082214796 Oct 15 12:27:25 AM UTC 24 Oct 15 12:27:29 AM UTC 24 544905004 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1520569675 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:29 AM UTC 24 2138562478 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2649040880 Oct 15 12:27:24 AM UTC 24 Oct 15 12:27:29 AM UTC 24 1041298624 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.749990072 Oct 15 12:27:27 AM UTC 24 Oct 15 12:27:30 AM UTC 24 372118495 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.117539755 Oct 15 12:27:26 AM UTC 24 Oct 15 12:27:31 AM UTC 24 2405825110 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3737088820 Oct 15 12:27:29 AM UTC 24 Oct 15 12:27:32 AM UTC 24 516309194 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4173065113 Oct 15 12:27:28 AM UTC 24 Oct 15 12:27:32 AM UTC 24 490098934 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2067758416 Oct 15 12:27:09 AM UTC 24 Oct 15 12:27:33 AM UTC 24 16653950004 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3898327982 Oct 15 12:27:10 AM UTC 24 Oct 15 12:27:33 AM UTC 24 8693190382 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3912585372 Oct 15 12:27:30 AM UTC 24 Oct 15 12:27:33 AM UTC 24 489284327 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.475306923 Oct 15 12:27:26 AM UTC 24 Oct 15 12:27:34 AM UTC 24 1233500498 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2470912961 Oct 15 12:27:30 AM UTC 24 Oct 15 12:27:34 AM UTC 24 1140573303 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3712541039 Oct 15 12:27:21 AM UTC 24 Oct 15 12:27:35 AM UTC 24 4226671089 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3786459117 Oct 15 12:27:29 AM UTC 24 Oct 15 12:27:35 AM UTC 24 4502519162 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3918046309 Oct 15 12:27:17 AM UTC 24 Oct 15 12:27:35 AM UTC 24 26661115711 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2821190687 Oct 15 12:27:33 AM UTC 24 Oct 15 12:27:36 AM UTC 24 625399233 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3437026833 Oct 15 12:27:33 AM UTC 24 Oct 15 12:27:37 AM UTC 24 993826762 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.4060364626 Oct 15 12:27:34 AM UTC 24 Oct 15 12:27:38 AM UTC 24 436625894 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4118729360 Oct 15 12:27:32 AM UTC 24 Oct 15 12:27:38 AM UTC 24 2045056507 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3929191412 Oct 15 12:27:34 AM UTC 24 Oct 15 12:27:38 AM UTC 24 351177869 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.898361466 Oct 15 12:27:36 AM UTC 24 Oct 15 12:27:39 AM UTC 24 463269878 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.671264845 Oct 15 12:27:35 AM UTC 24 Oct 15 12:27:39 AM UTC 24 437489979 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.371950424 Oct 15 12:27:33 AM UTC 24 Oct 15 12:27:40 AM UTC 24 4600011395 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3073471318 Oct 15 12:27:55 AM UTC 24 Oct 15 12:27:58 AM UTC 24 388780167 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3761000617 Oct 15 12:27:36 AM UTC 24 Oct 15 12:27:40 AM UTC 24 402505321 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1006872569 Oct 15 12:27:39 AM UTC 24 Oct 15 12:27:41 AM UTC 24 497046032 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3222082649 Oct 15 12:27:37 AM UTC 24 Oct 15 12:27:41 AM UTC 24 325440815 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.819542829 Oct 15 12:27:36 AM UTC 24 Oct 15 12:27:42 AM UTC 24 485672160 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4233950214 Oct 15 12:27:40 AM UTC 24 Oct 15 12:27:42 AM UTC 24 373158916 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1857153670 Oct 15 12:27:16 AM UTC 24 Oct 15 12:27:43 AM UTC 24 8159370446 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.578299804 Oct 15 12:27:40 AM UTC 24 Oct 15 12:27:43 AM UTC 24 4641568969 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2974009453 Oct 15 12:27:38 AM UTC 24 Oct 15 12:27:43 AM UTC 24 435541638 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.175644369 Oct 15 12:27:41 AM UTC 24 Oct 15 12:27:44 AM UTC 24 334488836 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3005343318 Oct 15 12:27:36 AM UTC 24 Oct 15 12:27:45 AM UTC 24 2764122039 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2925420427 Oct 15 12:27:42 AM UTC 24 Oct 15 12:27:45 AM UTC 24 349751904 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2755922987 Oct 15 12:27:43 AM UTC 24 Oct 15 12:27:46 AM UTC 24 536218128 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1266317693 Oct 15 12:27:41 AM UTC 24 Oct 15 12:27:46 AM UTC 24 789765954 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.3890097967 Oct 15 12:27:44 AM UTC 24 Oct 15 12:27:47 AM UTC 24 405022832 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2946400014 Oct 15 12:27:44 AM UTC 24 Oct 15 12:27:47 AM UTC 24 492802039 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2944067014 Oct 15 12:27:43 AM UTC 24 Oct 15 12:27:47 AM UTC 24 542366108 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1662512442 Oct 15 12:27:44 AM UTC 24 Oct 15 12:27:49 AM UTC 24 1272198392 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1014470756 Oct 15 12:27:43 AM UTC 24 Oct 15 12:27:50 AM UTC 24 4233941260 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2392788239 Oct 15 12:27:48 AM UTC 24 Oct 15 12:27:51 AM UTC 24 369847903 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3863579912 Oct 15 12:27:47 AM UTC 24 Oct 15 12:27:52 AM UTC 24 545695096 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3378630732 Oct 15 12:27:47 AM UTC 24 Oct 15 12:27:52 AM UTC 24 456391143 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.605840026 Oct 15 12:27:48 AM UTC 24 Oct 15 12:27:52 AM UTC 24 451316734 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1938878238 Oct 15 12:27:48 AM UTC 24 Oct 15 12:27:52 AM UTC 24 5343899514 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.270764045 Oct 15 12:27:49 AM UTC 24 Oct 15 12:27:52 AM UTC 24 2804810551 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.465279508 Oct 15 12:27:45 AM UTC 24 Oct 15 12:27:53 AM UTC 24 4554657396 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1190151839 Oct 15 12:27:38 AM UTC 24 Oct 15 12:27:53 AM UTC 24 4139393233 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.507519198 Oct 15 12:27:50 AM UTC 24 Oct 15 12:27:54 AM UTC 24 404252889 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.4110665115 Oct 15 12:27:52 AM UTC 24 Oct 15 12:27:54 AM UTC 24 512350273 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.200236763 Oct 15 12:27:52 AM UTC 24 Oct 15 12:27:54 AM UTC 24 433758196 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2428236609 Oct 15 12:27:13 AM UTC 24 Oct 15 12:27:55 AM UTC 24 25068746078 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.100766687 Oct 15 12:27:55 AM UTC 24 Oct 15 12:27:59 AM UTC 24 511205915 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3349427312 Oct 15 12:27:35 AM UTC 24 Oct 15 12:27:55 AM UTC 24 4833419300 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2427602510 Oct 15 12:27:53 AM UTC 24 Oct 15 12:27:56 AM UTC 24 563637038 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1655492422 Oct 15 12:27:53 AM UTC 24 Oct 15 12:27:59 AM UTC 24 640353315 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.4116542903 Oct 15 12:28:20 AM UTC 24 Oct 15 12:28:22 AM UTC 24 473045426 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1637240981 Oct 15 12:27:56 AM UTC 24 Oct 15 12:27:59 AM UTC 24 611501331 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3872061822 Oct 15 12:27:36 AM UTC 24 Oct 15 12:27:59 AM UTC 24 4451839935 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3251703664 Oct 15 12:27:57 AM UTC 24 Oct 15 12:27:59 AM UTC 24 558113685 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2731481305 Oct 15 12:27:56 AM UTC 24 Oct 15 12:28:00 AM UTC 24 461992667 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1847403889 Oct 15 12:27:44 AM UTC 24 Oct 15 12:28:00 AM UTC 24 4485169130 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3091834346 Oct 15 12:27:57 AM UTC 24 Oct 15 12:28:00 AM UTC 24 2447469227 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2904597046 Oct 15 12:27:57 AM UTC 24 Oct 15 12:28:00 AM UTC 24 484655134 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4199326994 Oct 15 12:27:42 AM UTC 24 Oct 15 12:28:00 AM UTC 24 4527965795 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2086186094 Oct 15 12:27:53 AM UTC 24 Oct 15 12:28:00 AM UTC 24 4458341321 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1866544944 Oct 15 12:27:56 AM UTC 24 Oct 15 12:28:02 AM UTC 24 2595609955 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.518334033 Oct 15 12:27:59 AM UTC 24 Oct 15 12:28:02 AM UTC 24 480807252 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1719458734 Oct 15 12:27:59 AM UTC 24 Oct 15 12:28:02 AM UTC 24 496335030 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.817713290 Oct 15 12:27:56 AM UTC 24 Oct 15 12:28:03 AM UTC 24 4249254994 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2501822743 Oct 15 12:27:59 AM UTC 24 Oct 15 12:28:03 AM UTC 24 411656155 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3425440222 Oct 15 12:27:59 AM UTC 24 Oct 15 12:28:03 AM UTC 24 347609595 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.971139485 Oct 15 12:28:02 AM UTC 24 Oct 15 12:28:04 AM UTC 24 311310844 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1336498803 Oct 15 12:28:01 AM UTC 24 Oct 15 12:28:04 AM UTC 24 517551643 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3753765087 Oct 15 12:28:02 AM UTC 24 Oct 15 12:28:04 AM UTC 24 491359834 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3624280481 Oct 15 12:28:01 AM UTC 24 Oct 15 12:28:06 AM UTC 24 1298746956 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3910190373 Oct 15 12:28:01 AM UTC 24 Oct 15 12:28:06 AM UTC 24 1975500426 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.910148350 Oct 15 12:27:53 AM UTC 24 Oct 15 12:28:07 AM UTC 24 8550717060 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.944874278 Oct 15 12:27:34 AM UTC 24 Oct 15 12:28:07 AM UTC 24 8203187855 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.829925127 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:08 AM UTC 24 349844778 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.700421071 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:09 AM UTC 24 636118305 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.289158631 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:10 AM UTC 24 348443935 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2460401456 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:10 AM UTC 24 473320755 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2731396635 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:10 AM UTC 24 408017469 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3642421622 Oct 15 12:28:07 AM UTC 24 Oct 15 12:28:10 AM UTC 24 575487579 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2621132148 Oct 15 12:27:52 AM UTC 24 Oct 15 12:28:10 AM UTC 24 4271559752 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.250249632 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:10 AM UTC 24 453999935 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4274005644 Oct 15 12:28:09 AM UTC 24 Oct 15 12:28:11 AM UTC 24 550202238 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4043658391 Oct 15 12:28:07 AM UTC 24 Oct 15 12:28:12 AM UTC 24 416858046 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.837717064 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:12 AM UTC 24 2317650982 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.791187266 Oct 15 12:28:07 AM UTC 24 Oct 15 12:28:13 AM UTC 24 4113353724 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.926855891 Oct 15 12:28:10 AM UTC 24 Oct 15 12:28:13 AM UTC 24 525845845 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3916827245 Oct 15 12:27:59 AM UTC 24 Oct 15 12:28:13 AM UTC 24 4603877050 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1292662183 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:13 AM UTC 24 499982109 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.90166946 Oct 15 12:28:09 AM UTC 24 Oct 15 12:28:13 AM UTC 24 523134607 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3864516737 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:14 AM UTC 24 517640389 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1172475620 Oct 15 12:28:09 AM UTC 24 Oct 15 12:28:14 AM UTC 24 4818519850 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4281278736 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:15 AM UTC 24 360822525 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.435358769 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:15 AM UTC 24 4298865396 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2863746160 Oct 15 12:28:20 AM UTC 24 Oct 15 12:28:22 AM UTC 24 419904815 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3031529260 Oct 15 12:28:02 AM UTC 24 Oct 15 12:28:15 AM UTC 24 4701235211 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.322748450 Oct 15 12:28:12 AM UTC 24 Oct 15 12:28:15 AM UTC 24 561515564 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1778934087 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:15 AM UTC 24 462557138 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1345919263 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:15 AM UTC 24 492179702 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3678412512 Oct 15 12:28:13 AM UTC 24 Oct 15 12:28:16 AM UTC 24 378840752 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2220349026 Oct 15 12:28:13 AM UTC 24 Oct 15 12:28:16 AM UTC 24 475950689 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.292638728 Oct 15 12:28:06 AM UTC 24 Oct 15 12:28:16 AM UTC 24 4749652163 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2395704016 Oct 15 12:28:13 AM UTC 24 Oct 15 12:28:16 AM UTC 24 335856763 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1026391083 Oct 15 12:28:13 AM UTC 24 Oct 15 12:28:16 AM UTC 24 480751803 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.607556009 Oct 15 12:28:15 AM UTC 24 Oct 15 12:28:17 AM UTC 24 323886004 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3394626414 Oct 15 12:28:15 AM UTC 24 Oct 15 12:28:17 AM UTC 24 355835543 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2660429143 Oct 15 12:28:15 AM UTC 24 Oct 15 12:28:17 AM UTC 24 484912051 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.4007334789 Oct 15 12:28:15 AM UTC 24 Oct 15 12:28:18 AM UTC 24 442531596 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.4156852526 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:18 AM UTC 24 621286696 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.2517525352 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:18 AM UTC 24 479229723 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3411152535 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:18 AM UTC 24 536641117 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1871706075 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:19 AM UTC 24 329618096 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1932093540 Oct 15 12:28:12 AM UTC 24 Oct 15 12:28:19 AM UTC 24 4310589672 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.3600267646 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:19 AM UTC 24 340924191 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4025882332 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:19 AM UTC 24 319794670 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.428216616 Oct 15 12:28:16 AM UTC 24 Oct 15 12:28:20 AM UTC 24 449963284 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.1386003122 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 518925344 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3364868216 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 500848519 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3034671937 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 390661583 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3143376708 Oct 15 12:28:18 AM UTC 24 Oct 15 12:28:20 AM UTC 24 367067744 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3306219136 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 481167836 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.810676838 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 526440927 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1789468180 Oct 15 12:28:17 AM UTC 24 Oct 15 12:28:20 AM UTC 24 555064584 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3369216140 Oct 15 12:28:19 AM UTC 24 Oct 15 12:28:21 AM UTC 24 391004816 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3591148859 Oct 15 12:28:19 AM UTC 24 Oct 15 12:28:22 AM UTC 24 381515814 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2083054037 Oct 15 12:28:19 AM UTC 24 Oct 15 12:28:22 AM UTC 24 462544504 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.4165142145 Oct 15 12:28:20 AM UTC 24 Oct 15 12:28:22 AM UTC 24 466428112 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1693879313 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:23 AM UTC 24 2870055480 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3498934400 Oct 15 12:28:01 AM UTC 24 Oct 15 12:28:23 AM UTC 24 8203536615 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1406049406 Oct 15 12:28:20 AM UTC 24 Oct 15 12:28:23 AM UTC 24 402964673 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.913468057 Oct 15 12:28:20 AM UTC 24 Oct 15 12:28:24 AM UTC 24 475448279 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.308361853 Oct 15 12:28:11 AM UTC 24 Oct 15 12:28:31 AM UTC 24 8405784274 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2835400655 Oct 15 12:27:31 AM UTC 24 Oct 15 12:29:34 AM UTC 24 53169730245 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3936541682
Short name T5
Test name
Test status
Simulation time 2734934462 ps
CPU time 8.13 seconds
Started Oct 14 10:26:15 PM UTC 24
Finished Oct 14 10:26:24 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936541682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3936541682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.885087558
Short name T10
Test name
Test status
Simulation time 18317092920 ps
CPU time 13.81 seconds
Started Oct 14 10:26:18 PM UTC 24
Finished Oct 14 10:26:33 PM UTC 24
Peak memory 220580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=885087558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.adc_ctrl_stress_all_with_rand_reset.885087558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3973301159
Short name T50
Test name
Test status
Simulation time 72243358295 ps
CPU time 243.56 seconds
Started Oct 14 10:27:19 PM UTC 24
Finished Oct 14 10:31:25 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973301159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3973301159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3508598688
Short name T19
Test name
Test status
Simulation time 676376225067 ps
CPU time 168.36 seconds
Started Oct 14 10:26:14 PM UTC 24
Finished Oct 14 10:29:05 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508598688 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.3508598688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.3744731271
Short name T242
Test name
Test status
Simulation time 571341877415 ps
CPU time 735.76 seconds
Started Oct 14 10:30:56 PM UTC 24
Finished Oct 14 10:43:19 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744731271 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.3744731271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1062136776
Short name T15
Test name
Test status
Simulation time 28214313723 ps
CPU time 10.97 seconds
Started Oct 14 10:27:22 PM UTC 24
Finished Oct 14 10:27:34 PM UTC 24
Peak memory 220448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1062136776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.adc_ctrl_stress_all_with_rand_reset.1062136776
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3464404132
Short name T45
Test name
Test status
Simulation time 28668564161 ps
CPU time 18.39 seconds
Started Oct 14 10:32:29 PM UTC 24
Finished Oct 14 10:32:48 PM UTC 24
Peak memory 220516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3464404132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.adc_ctrl_stress_all_with_rand_reset.3464404132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.395929402
Short name T171
Test name
Test status
Simulation time 492929431976 ps
CPU time 1049.91 seconds
Started Oct 14 10:29:13 PM UTC 24
Finished Oct 14 10:46:55 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395929402 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.395929402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3775799825
Short name T54
Test name
Test status
Simulation time 133180713229 ps
CPU time 751.35 seconds
Started Oct 14 10:32:29 PM UTC 24
Finished Oct 14 10:45:07 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775799825 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.3775799825
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3415124227
Short name T138
Test name
Test status
Simulation time 535726270093 ps
CPU time 377.41 seconds
Started Oct 14 10:28:07 PM UTC 24
Finished Oct 14 10:34:28 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415124227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.3415124227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.4130055752
Short name T156
Test name
Test status
Simulation time 488793164248 ps
CPU time 400.24 seconds
Started Oct 14 10:41:18 PM UTC 24
Finished Oct 14 10:48:03 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130055752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4130055752
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2619154613
Short name T124
Test name
Test status
Simulation time 524029351844 ps
CPU time 299.09 seconds
Started Oct 14 10:33:04 PM UTC 24
Finished Oct 14 10:38:07 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619154613 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.2619154613
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.735832152
Short name T120
Test name
Test status
Simulation time 352420778114 ps
CPU time 187.71 seconds
Started Oct 14 10:27:11 PM UTC 24
Finished Oct 14 10:30:22 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735832152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.735832152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4071213463
Short name T22
Test name
Test status
Simulation time 7309650911 ps
CPU time 27.84 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:26:42 PM UTC 24
Peak memory 242440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071213463 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4071213463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2929206548
Short name T80
Test name
Test status
Simulation time 599038393907 ps
CPU time 363.52 seconds
Started Oct 14 10:27:03 PM UTC 24
Finished Oct 14 10:33:11 PM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929206548 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.2929206548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.3061957647
Short name T248
Test name
Test status
Simulation time 577320944523 ps
CPU time 300.83 seconds
Started Oct 14 10:46:47 PM UTC 24
Finished Oct 14 10:51:51 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061957647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3061957647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3914486751
Short name T142
Test name
Test status
Simulation time 374713264693 ps
CPU time 311.22 seconds
Started Oct 14 10:32:55 PM UTC 24
Finished Oct 14 10:38:10 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914486751 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.3914486751
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1504006943
Short name T18
Test name
Test status
Simulation time 170934851143 ps
CPU time 53.19 seconds
Started Oct 14 10:27:54 PM UTC 24
Finished Oct 14 10:28:48 PM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504006943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.1504006943
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3388919676
Short name T65
Test name
Test status
Simulation time 614877314 ps
CPU time 4.12 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:14 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388919676 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3388919676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2108992123
Short name T267
Test name
Test status
Simulation time 503796119192 ps
CPU time 942.71 seconds
Started Oct 14 10:40:51 PM UTC 24
Finished Oct 14 10:56:44 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108992123 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.2108992123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.961805046
Short name T159
Test name
Test status
Simulation time 329130921404 ps
CPU time 304.44 seconds
Started Oct 14 10:56:05 PM UTC 24
Finished Oct 14 11:01:14 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961805046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.961805046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3203538639
Short name T58
Test name
Test status
Simulation time 27167631521 ps
CPU time 29.95 seconds
Started Oct 15 12:27:25 AM UTC 24
Finished Oct 15 12:27:56 AM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203538639 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.3203538639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1738781119
Short name T151
Test name
Test status
Simulation time 558298904320 ps
CPU time 503.77 seconds
Started Oct 14 10:28:29 PM UTC 24
Finished Oct 14 10:36:58 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738781119 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.1738781119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2406639276
Short name T201
Test name
Test status
Simulation time 331151706171 ps
CPU time 293.19 seconds
Started Oct 14 10:43:21 PM UTC 24
Finished Oct 14 10:48:18 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406639276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2406639276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.4206969120
Short name T282
Test name
Test status
Simulation time 512182939034 ps
CPU time 1496.56 seconds
Started Oct 14 10:47:22 PM UTC 24
Finished Oct 14 11:12:34 PM UTC 24
Peak memory 212856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206969120 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.4206969120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2198683013
Short name T141
Test name
Test status
Simulation time 408906918725 ps
CPU time 372.49 seconds
Started Oct 14 10:29:06 PM UTC 24
Finished Oct 14 10:35:23 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198683013 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.2198683013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3024801488
Short name T308
Test name
Test status
Simulation time 521014017593 ps
CPU time 395.87 seconds
Started Oct 14 11:09:59 PM UTC 24
Finished Oct 14 11:16:40 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024801488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3024801488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.3492407244
Short name T146
Test name
Test status
Simulation time 351148925801 ps
CPU time 205.74 seconds
Started Oct 14 10:42:38 PM UTC 24
Finished Oct 14 10:46:07 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492407244 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.3492407244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2938491702
Short name T216
Test name
Test status
Simulation time 495071427616 ps
CPU time 281.03 seconds
Started Oct 14 11:01:03 PM UTC 24
Finished Oct 14 11:05:47 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938491702 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.2938491702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.630390171
Short name T310
Test name
Test status
Simulation time 657182938860 ps
CPU time 987.88 seconds
Started Oct 14 11:15:22 PM UTC 24
Finished Oct 14 11:32:00 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630390171 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.630390171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.2768623796
Short name T298
Test name
Test status
Simulation time 358435870251 ps
CPU time 1030.16 seconds
Started Oct 14 10:59:55 PM UTC 24
Finished Oct 14 11:17:15 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768623796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2768623796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.4155811958
Short name T326
Test name
Test status
Simulation time 329554916847 ps
CPU time 396.35 seconds
Started Oct 14 11:20:38 PM UTC 24
Finished Oct 14 11:27:19 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155811958 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.4155811958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3893630547
Short name T202
Test name
Test status
Simulation time 477188498331 ps
CPU time 2105.66 seconds
Started Oct 14 10:36:00 PM UTC 24
Finished Oct 14 11:11:26 PM UTC 24
Peak memory 223248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893630547 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.3893630547
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.461043573
Short name T268
Test name
Test status
Simulation time 210159378771 ps
CPU time 175.83 seconds
Started Oct 14 10:49:07 PM UTC 24
Finished Oct 14 10:52:06 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461043573 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.461043573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1414870676
Short name T1
Test name
Test status
Simulation time 472291079 ps
CPU time 1.24 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:26:15 PM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414870676 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1414870676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3898327982
Short name T60
Test name
Test status
Simulation time 8693190382 ps
CPU time 21.61 seconds
Started Oct 15 12:27:10 AM UTC 24
Finished Oct 15 12:27:33 AM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898327982 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.3898327982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3231516768
Short name T44
Test name
Test status
Simulation time 30337448020 ps
CPU time 17.43 seconds
Started Oct 14 10:31:22 PM UTC 24
Finished Oct 14 10:31:41 PM UTC 24
Peak memory 210112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3231516768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.adc_ctrl_stress_all_with_rand_reset.3231516768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.485643177
Short name T153
Test name
Test status
Simulation time 197367392353 ps
CPU time 263.94 seconds
Started Oct 14 10:35:24 PM UTC 24
Finished Oct 14 10:39:51 PM UTC 24
Peak memory 210396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485643177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.485643177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3575627241
Short name T269
Test name
Test status
Simulation time 350807665957 ps
CPU time 397.27 seconds
Started Oct 14 10:49:40 PM UTC 24
Finished Oct 14 10:56:22 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575627241 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.3575627241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.910633003
Short name T100
Test name
Test status
Simulation time 565399744 ps
CPU time 1.38 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:11 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910633003 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.910633003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1208665319
Short name T82
Test name
Test status
Simulation time 501270543792 ps
CPU time 427.52 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:33:24 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208665319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1208665319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2625453064
Short name T262
Test name
Test status
Simulation time 170113792706 ps
CPU time 427.13 seconds
Started Oct 14 10:40:09 PM UTC 24
Finished Oct 14 10:47:21 PM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625453064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2625453064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.831955481
Short name T176
Test name
Test status
Simulation time 322613228979 ps
CPU time 743.02 seconds
Started Oct 14 10:48:18 PM UTC 24
Finished Oct 14 11:00:48 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831955481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.831955481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.2223259681
Short name T331
Test name
Test status
Simulation time 159926005111 ps
CPU time 265.95 seconds
Started Oct 14 11:05:25 PM UTC 24
Finished Oct 14 11:09:54 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223259681 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.2223259681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3659492662
Short name T236
Test name
Test status
Simulation time 161562660596 ps
CPU time 134.75 seconds
Started Oct 14 10:34:38 PM UTC 24
Finished Oct 14 10:36:55 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659492662 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.3659492662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1402846024
Short name T319
Test name
Test status
Simulation time 53413147439 ps
CPU time 63.05 seconds
Started Oct 14 10:57:54 PM UTC 24
Finished Oct 14 10:58:58 PM UTC 24
Peak memory 220708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1402846024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.adc_ctrl_stress_all_with_rand_reset.1402846024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3168497787
Short name T301
Test name
Test status
Simulation time 504024630063 ps
CPU time 666.18 seconds
Started Oct 14 11:04:15 PM UTC 24
Finished Oct 14 11:15:29 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168497787 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.3168497787
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.3463163424
Short name T203
Test name
Test status
Simulation time 331946020334 ps
CPU time 118.63 seconds
Started Oct 14 11:20:20 PM UTC 24
Finished Oct 14 11:22:21 PM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463163424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3463163424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.239715979
Short name T167
Test name
Test status
Simulation time 398579717295 ps
CPU time 315.68 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:31:31 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239715979 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.239715979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1624533543
Short name T371
Test name
Test status
Simulation time 119319264401 ps
CPU time 429.28 seconds
Started Oct 14 10:50:30 PM UTC 24
Finished Oct 14 10:57:43 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624533543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1624533543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.81510072
Short name T287
Test name
Test status
Simulation time 211149982708 ps
CPU time 79.13 seconds
Started Oct 14 11:01:30 PM UTC 24
Finished Oct 14 11:02:51 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81510072 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.81510072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.75213111
Short name T235
Test name
Test status
Simulation time 334631314488 ps
CPU time 923.3 seconds
Started Oct 14 11:25:18 PM UTC 24
Finished Oct 14 11:40:51 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75213111 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.75213111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3347016959
Short name T55
Test name
Test status
Simulation time 1257259104516 ps
CPU time 1518.42 seconds
Started Oct 14 10:30:06 PM UTC 24
Finished Oct 14 10:55:38 PM UTC 24
Peak memory 223368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347016959 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.3347016959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1545914176
Short name T63
Test name
Test status
Simulation time 550218287 ps
CPU time 4.78 seconds
Started Oct 15 12:26:58 AM UTC 24
Finished Oct 15 12:27:04 AM UTC 24
Peak memory 221396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545914176 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1545914176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1059808136
Short name T266
Test name
Test status
Simulation time 485692823625 ps
CPU time 884.67 seconds
Started Oct 14 10:46:23 PM UTC 24
Finished Oct 14 11:01:17 PM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059808136 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.1059808136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2469755389
Short name T265
Test name
Test status
Simulation time 599670271858 ps
CPU time 480.38 seconds
Started Oct 14 10:51:48 PM UTC 24
Finished Oct 14 10:59:54 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469755389 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2469755389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2758549054
Short name T234
Test name
Test status
Simulation time 337221010960 ps
CPU time 1000.61 seconds
Started Oct 14 10:53:31 PM UTC 24
Finished Oct 14 11:10:21 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758549054 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.2758549054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1893251074
Short name T221
Test name
Test status
Simulation time 84847138652 ps
CPU time 459.53 seconds
Started Oct 14 11:01:14 PM UTC 24
Finished Oct 14 11:08:59 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893251074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1893251074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.4183855378
Short name T279
Test name
Test status
Simulation time 614192401898 ps
CPU time 2018.19 seconds
Started Oct 14 11:05:15 PM UTC 24
Finished Oct 14 11:39:14 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183855378 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.4183855378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.2102952676
Short name T307
Test name
Test status
Simulation time 499860092963 ps
CPU time 470.2 seconds
Started Oct 14 11:16:00 PM UTC 24
Finished Oct 14 11:23:56 PM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102952676 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.2102952676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1765943190
Short name T320
Test name
Test status
Simulation time 362743427138 ps
CPU time 862.35 seconds
Started Oct 14 11:39:55 PM UTC 24
Finished Oct 14 11:54:26 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765943190 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.1765943190
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.2884593570
Short name T289
Test name
Test status
Simulation time 390088803377 ps
CPU time 949.67 seconds
Started Oct 14 10:55:39 PM UTC 24
Finished Oct 14 11:11:38 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884593570 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.2884593570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.1695227498
Short name T254
Test name
Test status
Simulation time 369154385773 ps
CPU time 919.64 seconds
Started Oct 14 10:58:15 PM UTC 24
Finished Oct 14 11:13:44 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695227498 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.1695227498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.982882874
Short name T293
Test name
Test status
Simulation time 497604656256 ps
CPU time 1125.48 seconds
Started Oct 14 10:59:05 PM UTC 24
Finished Oct 14 11:18:01 PM UTC 24
Peak memory 212800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982882874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.982882874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.3719572983
Short name T325
Test name
Test status
Simulation time 643018945410 ps
CPU time 1555.84 seconds
Started Oct 14 11:06:09 PM UTC 24
Finished Oct 14 11:32:19 PM UTC 24
Peak memory 213016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719572983 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.3719572983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.3872317660
Short name T353
Test name
Test status
Simulation time 324137815542 ps
CPU time 217.68 seconds
Started Oct 14 11:17:12 PM UTC 24
Finished Oct 14 11:20:53 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872317660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3872317660
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.13409334
Short name T323
Test name
Test status
Simulation time 386931208383 ps
CPU time 253.84 seconds
Started Oct 14 11:32:04 PM UTC 24
Finished Oct 14 11:36:21 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13409334 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.13409334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.910148350
Short name T364
Test name
Test status
Simulation time 8550717060 ps
CPU time 12.06 seconds
Started Oct 15 12:27:53 AM UTC 24
Finished Oct 15 12:28:07 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910148350 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.910148350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.980192073
Short name T169
Test name
Test status
Simulation time 541847809933 ps
CPU time 420.24 seconds
Started Oct 14 10:36:27 PM UTC 24
Finished Oct 14 10:43:33 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980192073 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.980192073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.853456631
Short name T295
Test name
Test status
Simulation time 483978549110 ps
CPU time 1224.79 seconds
Started Oct 14 10:44:30 PM UTC 24
Finished Oct 14 11:05:07 PM UTC 24
Peak memory 213000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853456631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.853456631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1642917014
Short name T245
Test name
Test status
Simulation time 164415289519 ps
CPU time 128.23 seconds
Started Oct 14 10:44:12 PM UTC 24
Finished Oct 14 10:46:23 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642917014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1642917014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3881694559
Short name T277
Test name
Test status
Simulation time 498693309070 ps
CPU time 1329.03 seconds
Started Oct 14 10:57:13 PM UTC 24
Finished Oct 14 11:19:34 PM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881694559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3881694559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.4262050820
Short name T368
Test name
Test status
Simulation time 128172008051 ps
CPU time 725.69 seconds
Started Oct 14 11:00:36 PM UTC 24
Finished Oct 14 11:12:50 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262050820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4262050820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3856512774
Short name T288
Test name
Test status
Simulation time 162790818144 ps
CPU time 139.57 seconds
Started Oct 14 11:02:34 PM UTC 24
Finished Oct 14 11:04:56 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856512774 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.3856512774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1998780472
Short name T757
Test name
Test status
Simulation time 119408769475 ps
CPU time 478.96 seconds
Started Oct 14 11:35:05 PM UTC 24
Finished Oct 14 11:43:09 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998780472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1998780472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3109034167
Short name T281
Test name
Test status
Simulation time 339694202661 ps
CPU time 959.3 seconds
Started Oct 14 10:30:58 PM UTC 24
Finished Oct 14 10:47:07 PM UTC 24
Peak memory 212840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109034167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3109034167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3916827245
Short name T362
Test name
Test status
Simulation time 4603877050 ps
CPU time 12.48 seconds
Started Oct 15 12:27:59 AM UTC 24
Finished Oct 15 12:28:13 AM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916827245 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.3916827245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.229840786
Short name T122
Test name
Test status
Simulation time 164735291477 ps
CPU time 500.67 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:34:37 PM UTC 24
Peak memory 212872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229840786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.229840786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2077045367
Short name T125
Test name
Test status
Simulation time 345117348012 ps
CPU time 136.16 seconds
Started Oct 14 10:36:58 PM UTC 24
Finished Oct 14 10:39:16 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077045367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2077045367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1664751244
Short name T145
Test name
Test status
Simulation time 321884548345 ps
CPU time 450.33 seconds
Started Oct 14 10:38:31 PM UTC 24
Finished Oct 14 10:46:06 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664751244 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1664751244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1686703490
Short name T170
Test name
Test status
Simulation time 18979434480 ps
CPU time 33.69 seconds
Started Oct 14 10:43:36 PM UTC 24
Finished Oct 14 10:44:11 PM UTC 24
Peak memory 220792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1686703490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.adc_ctrl_stress_all_with_rand_reset.1686703490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.496142863
Short name T230
Test name
Test status
Simulation time 90552171206 ps
CPU time 579.86 seconds
Started Oct 14 10:46:56 PM UTC 24
Finished Oct 14 10:56:41 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496142863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.496142863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.4226439525
Short name T305
Test name
Test status
Simulation time 364862639219 ps
CPU time 223.56 seconds
Started Oct 14 10:56:55 PM UTC 24
Finished Oct 14 11:00:42 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226439525 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.4226439525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.31089280
Short name T43
Test name
Test status
Simulation time 35438924430 ps
CPU time 20.28 seconds
Started Oct 14 10:30:06 PM UTC 24
Finished Oct 14 10:30:27 PM UTC 24
Peak memory 220448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=31089280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.adc_ctrl_stress_all_with_rand_reset.31089280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3075748144
Short name T102
Test name
Test status
Simulation time 610109268 ps
CPU time 4.64 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:14 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075748144 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.3075748144
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2067758416
Short name T110
Test name
Test status
Simulation time 16653950004 ps
CPU time 22.49 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:33 AM UTC 24
Peak memory 211792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067758416 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.2067758416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4112076670
Short name T101
Test name
Test status
Simulation time 1024927637 ps
CPU time 2.22 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:12 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112076670 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.4112076670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2891121108
Short name T71
Test name
Test status
Simulation time 758044453 ps
CPU time 1.73 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:12 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2891121108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_cs
r_mem_rw_with_rand_reset.2891121108
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1610527095
Short name T796
Test name
Test status
Simulation time 548635049 ps
CPU time 1.54 seconds
Started Oct 15 12:27:01 AM UTC 24
Finished Oct 15 12:27:04 AM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610527095 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1610527095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.820680448
Short name T56
Test name
Test status
Simulation time 4803506988 ps
CPU time 4.21 seconds
Started Oct 15 12:27:09 AM UTC 24
Finished Oct 15 12:27:14 AM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820680448 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.820680448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.511190378
Short name T59
Test name
Test status
Simulation time 7573721278 ps
CPU time 12.21 seconds
Started Oct 15 12:27:00 AM UTC 24
Finished Oct 15 12:27:13 AM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511190378 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.511190378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.459162300
Short name T104
Test name
Test status
Simulation time 477009580 ps
CPU time 2.73 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:20 AM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459162300 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.459162300
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2428236609
Short name T839
Test name
Test status
Simulation time 25068746078 ps
CPU time 39.35 seconds
Started Oct 15 12:27:13 AM UTC 24
Finished Oct 15 12:27:55 AM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428236609 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.2428236609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.907685585
Short name T117
Test name
Test status
Simulation time 1141131189 ps
CPU time 1.77 seconds
Started Oct 15 12:27:12 AM UTC 24
Finished Oct 15 12:27:16 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907685585 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.907685585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3281244784
Short name T77
Test name
Test status
Simulation time 554302436 ps
CPU time 1.99 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:19 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3281244784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs
r_mem_rw_with_rand_reset.3281244784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3349181342
Short name T103
Test name
Test status
Simulation time 413072450 ps
CPU time 0.99 seconds
Started Oct 15 12:27:12 AM UTC 24
Finished Oct 15 12:27:15 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349181342 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3349181342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1419015489
Short name T797
Test name
Test status
Simulation time 439802267 ps
CPU time 1.71 seconds
Started Oct 15 12:27:12 AM UTC 24
Finished Oct 15 12:27:16 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419015489 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1419015489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1520569675
Short name T112
Test name
Test status
Simulation time 2138562478 ps
CPU time 12.05 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:29 AM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520569675 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.1520569675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.507519198
Short name T836
Test name
Test status
Simulation time 404252889 ps
CPU time 3.08 seconds
Started Oct 15 12:27:50 AM UTC 24
Finished Oct 15 12:27:54 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=507519198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_cs
r_mem_rw_with_rand_reset.507519198
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2392788239
Short name T828
Test name
Test status
Simulation time 369847903 ps
CPU time 2.13 seconds
Started Oct 15 12:27:48 AM UTC 24
Finished Oct 15 12:27:51 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392788239 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2392788239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.605840026
Short name T831
Test name
Test status
Simulation time 451316734 ps
CPU time 3.14 seconds
Started Oct 15 12:27:48 AM UTC 24
Finished Oct 15 12:27:52 AM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605840026 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.605840026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.270764045
Short name T833
Test name
Test status
Simulation time 2804810551 ps
CPU time 2.51 seconds
Started Oct 15 12:27:49 AM UTC 24
Finished Oct 15 12:27:52 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270764045 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.270764045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3378630732
Short name T830
Test name
Test status
Simulation time 456391143 ps
CPU time 4.06 seconds
Started Oct 15 12:27:47 AM UTC 24
Finished Oct 15 12:27:52 AM UTC 24
Peak memory 221476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378630732 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3378630732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1938878238
Short name T832
Test name
Test status
Simulation time 5343899514 ps
CPU time 3.26 seconds
Started Oct 15 12:27:48 AM UTC 24
Finished Oct 15 12:27:52 AM UTC 24
Peak memory 211700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938878238 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.1938878238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2427602510
Short name T842
Test name
Test status
Simulation time 563637038 ps
CPU time 1.73 seconds
Started Oct 15 12:27:53 AM UTC 24
Finished Oct 15 12:27:56 AM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2427602510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c
sr_mem_rw_with_rand_reset.2427602510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.200236763
Short name T838
Test name
Test status
Simulation time 433758196 ps
CPU time 1.24 seconds
Started Oct 15 12:27:52 AM UTC 24
Finished Oct 15 12:27:54 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200236763 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.200236763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.4110665115
Short name T837
Test name
Test status
Simulation time 512350273 ps
CPU time 1.19 seconds
Started Oct 15 12:27:52 AM UTC 24
Finished Oct 15 12:27:54 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110665115 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4110665115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2086186094
Short name T852
Test name
Test status
Simulation time 4458341321 ps
CPU time 6.03 seconds
Started Oct 15 12:27:53 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086186094 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.2086186094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.979174123
Short name T66
Test name
Test status
Simulation time 439722776 ps
CPU time 3.81 seconds
Started Oct 15 12:27:51 AM UTC 24
Finished Oct 15 12:27:56 AM UTC 24
Peak memory 211372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979174123 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.979174123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2621132148
Short name T870
Test name
Test status
Simulation time 4271559752 ps
CPU time 17.12 seconds
Started Oct 15 12:27:52 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621132148 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.2621132148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1637240981
Short name T845
Test name
Test status
Simulation time 611501331 ps
CPU time 1.83 seconds
Started Oct 15 12:27:56 AM UTC 24
Finished Oct 15 12:27:59 AM UTC 24
Peak memory 221136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1637240981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
sr_mem_rw_with_rand_reset.1637240981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.100766687
Short name T840
Test name
Test status
Simulation time 511205915 ps
CPU time 2.94 seconds
Started Oct 15 12:27:55 AM UTC 24
Finished Oct 15 12:27:59 AM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100766687 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.100766687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3073471318
Short name T809
Test name
Test status
Simulation time 388780167 ps
CPU time 2.51 seconds
Started Oct 15 12:27:55 AM UTC 24
Finished Oct 15 12:27:58 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073471318 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3073471318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1866544944
Short name T853
Test name
Test status
Simulation time 2595609955 ps
CPU time 4.96 seconds
Started Oct 15 12:27:56 AM UTC 24
Finished Oct 15 12:28:02 AM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866544944 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.1866544944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1655492422
Short name T843
Test name
Test status
Simulation time 640353315 ps
CPU time 4.07 seconds
Started Oct 15 12:27:53 AM UTC 24
Finished Oct 15 12:27:59 AM UTC 24
Peak memory 221668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655492422 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1655492422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2501822743
Short name T856
Test name
Test status
Simulation time 411656155 ps
CPU time 2.93 seconds
Started Oct 15 12:27:59 AM UTC 24
Finished Oct 15 12:28:03 AM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2501822743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c
sr_mem_rw_with_rand_reset.2501822743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3251703664
Short name T846
Test name
Test status
Simulation time 558113685 ps
CPU time 1.18 seconds
Started Oct 15 12:27:57 AM UTC 24
Finished Oct 15 12:27:59 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251703664 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3251703664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2904597046
Short name T850
Test name
Test status
Simulation time 484655134 ps
CPU time 2.28 seconds
Started Oct 15 12:27:57 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904597046 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2904597046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3091834346
Short name T849
Test name
Test status
Simulation time 2447469227 ps
CPU time 1.76 seconds
Started Oct 15 12:27:57 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091834346 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.3091834346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2731481305
Short name T847
Test name
Test status
Simulation time 461992667 ps
CPU time 2.83 seconds
Started Oct 15 12:27:56 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731481305 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2731481305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.817713290
Short name T363
Test name
Test status
Simulation time 4249254994 ps
CPU time 6.2 seconds
Started Oct 15 12:27:56 AM UTC 24
Finished Oct 15 12:28:03 AM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817713290 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.817713290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1336498803
Short name T859
Test name
Test status
Simulation time 517551643 ps
CPU time 2.58 seconds
Started Oct 15 12:28:01 AM UTC 24
Finished Oct 15 12:28:04 AM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1336498803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c
sr_mem_rw_with_rand_reset.1336498803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.518334033
Short name T854
Test name
Test status
Simulation time 480807252 ps
CPU time 1.3 seconds
Started Oct 15 12:27:59 AM UTC 24
Finished Oct 15 12:28:02 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518334033 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.518334033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1719458734
Short name T855
Test name
Test status
Simulation time 496335030 ps
CPU time 1.77 seconds
Started Oct 15 12:27:59 AM UTC 24
Finished Oct 15 12:28:02 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719458734 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1719458734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3910190373
Short name T862
Test name
Test status
Simulation time 1975500426 ps
CPU time 4.76 seconds
Started Oct 15 12:28:01 AM UTC 24
Finished Oct 15 12:28:06 AM UTC 24
Peak memory 211060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910190373 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.3910190373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3425440222
Short name T857
Test name
Test status
Simulation time 347609595 ps
CPU time 3.15 seconds
Started Oct 15 12:27:59 AM UTC 24
Finished Oct 15 12:28:03 AM UTC 24
Peak memory 221732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425440222 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3425440222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.700421071
Short name T865
Test name
Test status
Simulation time 636118305 ps
CPU time 2.03 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:09 AM UTC 24
Peak memory 211164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=700421071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs
r_mem_rw_with_rand_reset.700421071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3753765087
Short name T860
Test name
Test status
Simulation time 491359834 ps
CPU time 1.35 seconds
Started Oct 15 12:28:02 AM UTC 24
Finished Oct 15 12:28:04 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753765087 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3753765087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.971139485
Short name T858
Test name
Test status
Simulation time 311310844 ps
CPU time 1.16 seconds
Started Oct 15 12:28:02 AM UTC 24
Finished Oct 15 12:28:04 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971139485 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.971139485
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3031529260
Short name T883
Test name
Test status
Simulation time 4701235211 ps
CPU time 12.05 seconds
Started Oct 15 12:28:02 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031529260 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.3031529260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3624280481
Short name T861
Test name
Test status
Simulation time 1298746956 ps
CPU time 4.29 seconds
Started Oct 15 12:28:01 AM UTC 24
Finished Oct 15 12:28:06 AM UTC 24
Peak memory 227936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624280481 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3624280481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3498934400
Short name T916
Test name
Test status
Simulation time 8203536615 ps
CPU time 21.1 seconds
Started Oct 15 12:28:01 AM UTC 24
Finished Oct 15 12:28:23 AM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498934400 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.3498934400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2731396635
Short name T868
Test name
Test status
Simulation time 408017469 ps
CPU time 2.83 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2731396635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c
sr_mem_rw_with_rand_reset.2731396635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2460401456
Short name T867
Test name
Test status
Simulation time 473320755 ps
CPU time 2.93 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 210900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460401456 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2460401456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.829925127
Short name T864
Test name
Test status
Simulation time 349844778 ps
CPU time 0.88 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:08 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829925127 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.829925127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.837717064
Short name T874
Test name
Test status
Simulation time 2317650982 ps
CPU time 4.96 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:12 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837717064 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.837717064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.250249632
Short name T871
Test name
Test status
Simulation time 453999935 ps
CPU time 3.6 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 211764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250249632 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.250249632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.435358769
Short name T881
Test name
Test status
Simulation time 4298865396 ps
CPU time 7.56 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 211784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435358769 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.435358769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4043658391
Short name T873
Test name
Test status
Simulation time 416858046 ps
CPU time 3.21 seconds
Started Oct 15 12:28:07 AM UTC 24
Finished Oct 15 12:28:12 AM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4043658391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
sr_mem_rw_with_rand_reset.4043658391
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3642421622
Short name T869
Test name
Test status
Simulation time 575487579 ps
CPU time 1.72 seconds
Started Oct 15 12:28:07 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 210960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642421622 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3642421622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.289158631
Short name T866
Test name
Test status
Simulation time 348443935 ps
CPU time 2.58 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:10 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289158631 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.289158631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.791187266
Short name T875
Test name
Test status
Simulation time 4113353724 ps
CPU time 4.17 seconds
Started Oct 15 12:28:07 AM UTC 24
Finished Oct 15 12:28:13 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791187266 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.791187266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1292662183
Short name T877
Test name
Test status
Simulation time 499982109 ps
CPU time 5.93 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:13 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292662183 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1292662183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.292638728
Short name T889
Test name
Test status
Simulation time 4749652163 ps
CPU time 8.43 seconds
Started Oct 15 12:28:06 AM UTC 24
Finished Oct 15 12:28:16 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292638728 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.292638728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3864516737
Short name T879
Test name
Test status
Simulation time 517640389 ps
CPU time 1.91 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:14 AM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3864516737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c
sr_mem_rw_with_rand_reset.3864516737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.926855891
Short name T876
Test name
Test status
Simulation time 525845845 ps
CPU time 2.11 seconds
Started Oct 15 12:28:10 AM UTC 24
Finished Oct 15 12:28:13 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926855891 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.926855891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4274005644
Short name T872
Test name
Test status
Simulation time 550202238 ps
CPU time 1.43 seconds
Started Oct 15 12:28:09 AM UTC 24
Finished Oct 15 12:28:11 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274005644 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4274005644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1693879313
Short name T915
Test name
Test status
Simulation time 2870055480 ps
CPU time 10.92 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:23 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693879313 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.1693879313
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.90166946
Short name T878
Test name
Test status
Simulation time 523134607 ps
CPU time 3.93 seconds
Started Oct 15 12:28:09 AM UTC 24
Finished Oct 15 12:28:13 AM UTC 24
Peak memory 227728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90166946 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.90166946
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1172475620
Short name T73
Test name
Test status
Simulation time 4818519850 ps
CPU time 4.46 seconds
Started Oct 15 12:28:09 AM UTC 24
Finished Oct 15 12:28:14 AM UTC 24
Peak memory 211700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172475620 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.1172475620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.322748450
Short name T884
Test name
Test status
Simulation time 561515564 ps
CPU time 1.94 seconds
Started Oct 15 12:28:12 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 211164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=322748450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_cs
r_mem_rw_with_rand_reset.322748450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4281278736
Short name T880
Test name
Test status
Simulation time 360822525 ps
CPU time 2.48 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 210960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281278736 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4281278736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1778934087
Short name T885
Test name
Test status
Simulation time 462557138 ps
CPU time 3.09 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778934087 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1778934087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1932093540
Short name T900
Test name
Test status
Simulation time 4310589672 ps
CPU time 5.86 seconds
Started Oct 15 12:28:12 AM UTC 24
Finished Oct 15 12:28:19 AM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932093540 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.1932093540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1345919263
Short name T886
Test name
Test status
Simulation time 492179702 ps
CPU time 3.37 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:15 AM UTC 24
Peak memory 211700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345919263 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1345919263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.308361853
Short name T365
Test name
Test status
Simulation time 8405784274 ps
CPU time 19.14 seconds
Started Oct 15 12:28:11 AM UTC 24
Finished Oct 15 12:28:31 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308361853 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.308361853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3828962806
Short name T106
Test name
Test status
Simulation time 1180570480 ps
CPU time 3.25 seconds
Started Oct 15 12:27:19 AM UTC 24
Finished Oct 15 12:27:24 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828962806 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.3828962806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3918046309
Short name T802
Test name
Test status
Simulation time 26661115711 ps
CPU time 16.75 seconds
Started Oct 15 12:27:17 AM UTC 24
Finished Oct 15 12:27:35 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918046309 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.3918046309
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3935043699
Short name T107
Test name
Test status
Simulation time 1127323205 ps
CPU time 6.48 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:24 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935043699 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.3935043699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2498672822
Short name T70
Test name
Test status
Simulation time 538294037 ps
CPU time 2.97 seconds
Started Oct 15 12:27:20 AM UTC 24
Finished Oct 15 12:27:24 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2498672822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs
r_mem_rw_with_rand_reset.2498672822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1238070892
Short name T105
Test name
Test status
Simulation time 458268970 ps
CPU time 1.33 seconds
Started Oct 15 12:27:17 AM UTC 24
Finished Oct 15 12:27:20 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238070892 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1238070892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2927795506
Short name T798
Test name
Test status
Simulation time 347264438 ps
CPU time 1.17 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:18 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927795506 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2927795506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2946396862
Short name T57
Test name
Test status
Simulation time 1936605448 ps
CPU time 2.25 seconds
Started Oct 15 12:27:19 AM UTC 24
Finished Oct 15 12:27:23 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946396862 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.2946396862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1744953135
Short name T67
Test name
Test status
Simulation time 639002889 ps
CPU time 3.18 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:20 AM UTC 24
Peak memory 211364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744953135 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1744953135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1857153670
Short name T815
Test name
Test status
Simulation time 8159370446 ps
CPU time 25.71 seconds
Started Oct 15 12:27:16 AM UTC 24
Finished Oct 15 12:27:43 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857153670 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.1857153670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3678412512
Short name T887
Test name
Test status
Simulation time 378840752 ps
CPU time 1.37 seconds
Started Oct 15 12:28:13 AM UTC 24
Finished Oct 15 12:28:16 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678412512 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3678412512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2220349026
Short name T888
Test name
Test status
Simulation time 475950689 ps
CPU time 1.42 seconds
Started Oct 15 12:28:13 AM UTC 24
Finished Oct 15 12:28:16 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220349026 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2220349026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1026391083
Short name T891
Test name
Test status
Simulation time 480751803 ps
CPU time 1.97 seconds
Started Oct 15 12:28:13 AM UTC 24
Finished Oct 15 12:28:16 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026391083 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1026391083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2395704016
Short name T890
Test name
Test status
Simulation time 335856763 ps
CPU time 1.32 seconds
Started Oct 15 12:28:13 AM UTC 24
Finished Oct 15 12:28:16 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395704016 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2395704016
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3394626414
Short name T893
Test name
Test status
Simulation time 355835543 ps
CPU time 1.05 seconds
Started Oct 15 12:28:15 AM UTC 24
Finished Oct 15 12:28:17 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394626414 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3394626414
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.4007334789
Short name T895
Test name
Test status
Simulation time 442531596 ps
CPU time 2.18 seconds
Started Oct 15 12:28:15 AM UTC 24
Finished Oct 15 12:28:18 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007334789 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4007334789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2660429143
Short name T894
Test name
Test status
Simulation time 484912051 ps
CPU time 1.13 seconds
Started Oct 15 12:28:15 AM UTC 24
Finished Oct 15 12:28:17 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660429143 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2660429143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.607556009
Short name T892
Test name
Test status
Simulation time 323886004 ps
CPU time 0.9 seconds
Started Oct 15 12:28:15 AM UTC 24
Finished Oct 15 12:28:17 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607556009 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.607556009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1871706075
Short name T899
Test name
Test status
Simulation time 329618096 ps
CPU time 1.7 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:19 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871706075 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1871706075
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.428216616
Short name T903
Test name
Test status
Simulation time 449963284 ps
CPU time 2.71 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428216616 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.428216616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.475306923
Short name T801
Test name
Test status
Simulation time 1233500498 ps
CPU time 6.42 seconds
Started Oct 15 12:27:26 AM UTC 24
Finished Oct 15 12:27:34 AM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475306923 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.475306923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2649040880
Short name T109
Test name
Test status
Simulation time 1041298624 ps
CPU time 4.7 seconds
Started Oct 15 12:27:24 AM UTC 24
Finished Oct 15 12:27:29 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649040880 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.2649040880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.749990072
Short name T88
Test name
Test status
Simulation time 372118495 ps
CPU time 2.04 seconds
Started Oct 15 12:27:27 AM UTC 24
Finished Oct 15 12:27:30 AM UTC 24
Peak memory 211096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=749990072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr
_mem_rw_with_rand_reset.749990072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2082214796
Short name T108
Test name
Test status
Simulation time 544905004 ps
CPU time 2.84 seconds
Started Oct 15 12:27:25 AM UTC 24
Finished Oct 15 12:27:29 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082214796 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2082214796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3168397311
Short name T799
Test name
Test status
Simulation time 468788850 ps
CPU time 2.91 seconds
Started Oct 15 12:27:23 AM UTC 24
Finished Oct 15 12:27:27 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168397311 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3168397311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.117539755
Short name T113
Test name
Test status
Simulation time 2405825110 ps
CPU time 3.95 seconds
Started Oct 15 12:27:26 AM UTC 24
Finished Oct 15 12:27:31 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117539755 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.117539755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1975182538
Short name T68
Test name
Test status
Simulation time 550932369 ps
CPU time 3.5 seconds
Started Oct 15 12:27:20 AM UTC 24
Finished Oct 15 12:27:25 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975182538 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1975182538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3712541039
Short name T61
Test name
Test status
Simulation time 4226671089 ps
CPU time 12.21 seconds
Started Oct 15 12:27:21 AM UTC 24
Finished Oct 15 12:27:35 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712541039 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.3712541039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.4156852526
Short name T896
Test name
Test status
Simulation time 621286696 ps
CPU time 0.97 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:18 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156852526 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4156852526
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.2517525352
Short name T897
Test name
Test status
Simulation time 479229723 ps
CPU time 1.2 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:18 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517525352 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2517525352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3411152535
Short name T898
Test name
Test status
Simulation time 536641117 ps
CPU time 1.38 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:18 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411152535 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3411152535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4025882332
Short name T902
Test name
Test status
Simulation time 319794670 ps
CPU time 2.28 seconds
Started Oct 15 12:28:16 AM UTC 24
Finished Oct 15 12:28:19 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025882332 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4025882332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3364868216
Short name T905
Test name
Test status
Simulation time 500848519 ps
CPU time 1.57 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364868216 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3364868216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.1386003122
Short name T904
Test name
Test status
Simulation time 518925344 ps
CPU time 1.45 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386003122 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1386003122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.810676838
Short name T909
Test name
Test status
Simulation time 526440927 ps
CPU time 1.7 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810676838 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.810676838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.3600267646
Short name T901
Test name
Test status
Simulation time 340924191 ps
CPU time 0.95 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:19 AM UTC 24
Peak memory 209548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600267646 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3600267646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1789468180
Short name T910
Test name
Test status
Simulation time 555064584 ps
CPU time 1.63 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789468180 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1789468180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3034671937
Short name T906
Test name
Test status
Simulation time 390661583 ps
CPU time 1.28 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034671937 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3034671937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4118729360
Short name T806
Test name
Test status
Simulation time 2045056507 ps
CPU time 4.09 seconds
Started Oct 15 12:27:32 AM UTC 24
Finished Oct 15 12:27:38 AM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118729360 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.4118729360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2835400655
Short name T919
Test name
Test status
Simulation time 53169730245 ps
CPU time 119.94 seconds
Started Oct 15 12:27:31 AM UTC 24
Finished Oct 15 12:29:34 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835400655 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.2835400655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2470912961
Short name T111
Test name
Test status
Simulation time 1140573303 ps
CPU time 2.67 seconds
Started Oct 15 12:27:30 AM UTC 24
Finished Oct 15 12:27:34 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470912961 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.2470912961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2821190687
Short name T803
Test name
Test status
Simulation time 625399233 ps
CPU time 1.76 seconds
Started Oct 15 12:27:33 AM UTC 24
Finished Oct 15 12:27:36 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2821190687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs
r_mem_rw_with_rand_reset.2821190687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3912585372
Short name T114
Test name
Test status
Simulation time 489284327 ps
CPU time 1.49 seconds
Started Oct 15 12:27:30 AM UTC 24
Finished Oct 15 12:27:33 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912585372 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3912585372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3737088820
Short name T800
Test name
Test status
Simulation time 516309194 ps
CPU time 1.35 seconds
Started Oct 15 12:27:29 AM UTC 24
Finished Oct 15 12:27:32 AM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737088820 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3737088820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.371950424
Short name T116
Test name
Test status
Simulation time 4600011395 ps
CPU time 6.13 seconds
Started Oct 15 12:27:33 AM UTC 24
Finished Oct 15 12:27:40 AM UTC 24
Peak memory 211700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371950424 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.371950424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4173065113
Short name T69
Test name
Test status
Simulation time 490098934 ps
CPU time 2.64 seconds
Started Oct 15 12:27:28 AM UTC 24
Finished Oct 15 12:27:32 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173065113 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.4173065113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3786459117
Short name T64
Test name
Test status
Simulation time 4502519162 ps
CPU time 4.54 seconds
Started Oct 15 12:27:29 AM UTC 24
Finished Oct 15 12:27:35 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786459117 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.3786459117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3306219136
Short name T908
Test name
Test status
Simulation time 481167836 ps
CPU time 1.36 seconds
Started Oct 15 12:28:17 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306219136 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3306219136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3143376708
Short name T907
Test name
Test status
Simulation time 367067744 ps
CPU time 1.26 seconds
Started Oct 15 12:28:18 AM UTC 24
Finished Oct 15 12:28:20 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143376708 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3143376708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2083054037
Short name T913
Test name
Test status
Simulation time 462544504 ps
CPU time 1.82 seconds
Started Oct 15 12:28:19 AM UTC 24
Finished Oct 15 12:28:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083054037 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2083054037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3369216140
Short name T911
Test name
Test status
Simulation time 391004816 ps
CPU time 1.26 seconds
Started Oct 15 12:28:19 AM UTC 24
Finished Oct 15 12:28:21 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369216140 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3369216140
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3591148859
Short name T912
Test name
Test status
Simulation time 381515814 ps
CPU time 1.7 seconds
Started Oct 15 12:28:19 AM UTC 24
Finished Oct 15 12:28:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591148859 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3591148859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.4165142145
Short name T914
Test name
Test status
Simulation time 466428112 ps
CPU time 1.08 seconds
Started Oct 15 12:28:20 AM UTC 24
Finished Oct 15 12:28:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165142145 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4165142145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.4116542903
Short name T844
Test name
Test status
Simulation time 473045426 ps
CPU time 1.29 seconds
Started Oct 15 12:28:20 AM UTC 24
Finished Oct 15 12:28:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116542903 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4116542903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.913468057
Short name T918
Test name
Test status
Simulation time 475448279 ps
CPU time 2.84 seconds
Started Oct 15 12:28:20 AM UTC 24
Finished Oct 15 12:28:24 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913468057 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.913468057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1406049406
Short name T917
Test name
Test status
Simulation time 402964673 ps
CPU time 2.03 seconds
Started Oct 15 12:28:20 AM UTC 24
Finished Oct 15 12:28:23 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406049406 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1406049406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2863746160
Short name T882
Test name
Test status
Simulation time 419904815 ps
CPU time 1.19 seconds
Started Oct 15 12:28:20 AM UTC 24
Finished Oct 15 12:28:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863746160 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2863746160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.671264845
Short name T808
Test name
Test status
Simulation time 437489979 ps
CPU time 2.65 seconds
Started Oct 15 12:27:35 AM UTC 24
Finished Oct 15 12:27:39 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=671264845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr
_mem_rw_with_rand_reset.671264845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3929191412
Short name T115
Test name
Test status
Simulation time 351177869 ps
CPU time 3.12 seconds
Started Oct 15 12:27:34 AM UTC 24
Finished Oct 15 12:27:38 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929191412 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3929191412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.4060364626
Short name T805
Test name
Test status
Simulation time 436625894 ps
CPU time 2.74 seconds
Started Oct 15 12:27:34 AM UTC 24
Finished Oct 15 12:27:38 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060364626 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4060364626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3349427312
Short name T841
Test name
Test status
Simulation time 4833419300 ps
CPU time 18.69 seconds
Started Oct 15 12:27:35 AM UTC 24
Finished Oct 15 12:27:55 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349427312 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.3349427312
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3437026833
Short name T804
Test name
Test status
Simulation time 993826762 ps
CPU time 3 seconds
Started Oct 15 12:27:33 AM UTC 24
Finished Oct 15 12:27:37 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437026833 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3437026833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.944874278
Short name T863
Test name
Test status
Simulation time 8203187855 ps
CPU time 32.06 seconds
Started Oct 15 12:27:34 AM UTC 24
Finished Oct 15 12:28:07 AM UTC 24
Peak memory 211768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944874278 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.944874278
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3222082649
Short name T812
Test name
Test status
Simulation time 325440815 ps
CPU time 2.57 seconds
Started Oct 15 12:27:37 AM UTC 24
Finished Oct 15 12:27:41 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3222082649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs
r_mem_rw_with_rand_reset.3222082649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3761000617
Short name T810
Test name
Test status
Simulation time 402505321 ps
CPU time 2.98 seconds
Started Oct 15 12:27:36 AM UTC 24
Finished Oct 15 12:27:40 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761000617 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3761000617
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.898361466
Short name T807
Test name
Test status
Simulation time 463269878 ps
CPU time 1.37 seconds
Started Oct 15 12:27:36 AM UTC 24
Finished Oct 15 12:27:39 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898361466 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.898361466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3005343318
Short name T819
Test name
Test status
Simulation time 2764122039 ps
CPU time 7.75 seconds
Started Oct 15 12:27:36 AM UTC 24
Finished Oct 15 12:27:45 AM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005343318 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3005343318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.819542829
Short name T813
Test name
Test status
Simulation time 485672160 ps
CPU time 4.95 seconds
Started Oct 15 12:27:36 AM UTC 24
Finished Oct 15 12:27:42 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819542829 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.819542829
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3872061822
Short name T72
Test name
Test status
Simulation time 4451839935 ps
CPU time 21.28 seconds
Started Oct 15 12:27:36 AM UTC 24
Finished Oct 15 12:27:59 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872061822 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.3872061822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.175644369
Short name T818
Test name
Test status
Simulation time 334488836 ps
CPU time 2.01 seconds
Started Oct 15 12:27:41 AM UTC 24
Finished Oct 15 12:27:44 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=175644369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr
_mem_rw_with_rand_reset.175644369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4233950214
Short name T814
Test name
Test status
Simulation time 373158916 ps
CPU time 1.61 seconds
Started Oct 15 12:27:40 AM UTC 24
Finished Oct 15 12:27:42 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233950214 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4233950214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1006872569
Short name T811
Test name
Test status
Simulation time 497046032 ps
CPU time 1.37 seconds
Started Oct 15 12:27:39 AM UTC 24
Finished Oct 15 12:27:41 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006872569 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1006872569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.578299804
Short name T816
Test name
Test status
Simulation time 4641568969 ps
CPU time 2.34 seconds
Started Oct 15 12:27:40 AM UTC 24
Finished Oct 15 12:27:43 AM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578299804 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.578299804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2974009453
Short name T817
Test name
Test status
Simulation time 435541638 ps
CPU time 3.57 seconds
Started Oct 15 12:27:38 AM UTC 24
Finished Oct 15 12:27:43 AM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974009453 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2974009453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1190151839
Short name T835
Test name
Test status
Simulation time 4139393233 ps
CPU time 13.63 seconds
Started Oct 15 12:27:38 AM UTC 24
Finished Oct 15 12:27:53 AM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190151839 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.1190151839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2944067014
Short name T825
Test name
Test status
Simulation time 542366108 ps
CPU time 3.11 seconds
Started Oct 15 12:27:43 AM UTC 24
Finished Oct 15 12:27:47 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2944067014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs
r_mem_rw_with_rand_reset.2944067014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2755922987
Short name T821
Test name
Test status
Simulation time 536218128 ps
CPU time 1.94 seconds
Started Oct 15 12:27:43 AM UTC 24
Finished Oct 15 12:27:46 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755922987 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2755922987
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2925420427
Short name T820
Test name
Test status
Simulation time 349751904 ps
CPU time 2.37 seconds
Started Oct 15 12:27:42 AM UTC 24
Finished Oct 15 12:27:45 AM UTC 24
Peak memory 211256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925420427 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2925420427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1014470756
Short name T827
Test name
Test status
Simulation time 4233941260 ps
CPU time 6.24 seconds
Started Oct 15 12:27:43 AM UTC 24
Finished Oct 15 12:27:50 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014470756 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.1014470756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1266317693
Short name T822
Test name
Test status
Simulation time 789765954 ps
CPU time 4.49 seconds
Started Oct 15 12:27:41 AM UTC 24
Finished Oct 15 12:27:46 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266317693 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1266317693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4199326994
Short name T851
Test name
Test status
Simulation time 4527965795 ps
CPU time 17.32 seconds
Started Oct 15 12:27:42 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199326994 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.4199326994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3863579912
Short name T829
Test name
Test status
Simulation time 545695096 ps
CPU time 3.95 seconds
Started Oct 15 12:27:47 AM UTC 24
Finished Oct 15 12:27:52 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3863579912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs
r_mem_rw_with_rand_reset.3863579912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2946400014
Short name T824
Test name
Test status
Simulation time 492802039 ps
CPU time 1.42 seconds
Started Oct 15 12:27:44 AM UTC 24
Finished Oct 15 12:27:47 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946400014 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2946400014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.3890097967
Short name T823
Test name
Test status
Simulation time 405022832 ps
CPU time 1.17 seconds
Started Oct 15 12:27:44 AM UTC 24
Finished Oct 15 12:27:47 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890097967 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3890097967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.465279508
Short name T834
Test name
Test status
Simulation time 4554657396 ps
CPU time 6.1 seconds
Started Oct 15 12:27:45 AM UTC 24
Finished Oct 15 12:27:53 AM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465279508 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.465279508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1662512442
Short name T826
Test name
Test status
Simulation time 1272198392 ps
CPU time 3.65 seconds
Started Oct 15 12:27:44 AM UTC 24
Finished Oct 15 12:27:49 AM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662512442 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1662512442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1847403889
Short name T848
Test name
Test status
Simulation time 4485169130 ps
CPU time 14.14 seconds
Started Oct 15 12:27:44 AM UTC 24
Finished Oct 15 12:28:00 AM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847403889 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.1847403889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1485717351
Short name T11
Test name
Test status
Simulation time 166594805200 ps
CPU time 31.18 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:26:44 PM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485717351 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.1485717351
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.260591236
Short name T382
Test name
Test status
Simulation time 486930091752 ps
CPU time 682.38 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:37:41 PM UTC 24
Peak memory 212872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260591236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.260591236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1411692445
Short name T16
Test name
Test status
Simulation time 165466666334 ps
CPU time 91.25 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:27:44 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411692445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1411692445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1670041699
Short name T375
Test name
Test status
Simulation time 159370674904 ps
CPU time 573.56 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:35:51 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670041699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.1670041699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.19886694
Short name T272
Test name
Test status
Simulation time 369307819235 ps
CPU time 1088.47 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:44:30 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19886694 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.19886694
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.127209146
Short name T79
Test name
Test status
Simulation time 81145008546 ps
CPU time 406.8 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:33:04 PM UTC 24
Peak memory 210556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127209146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.127209146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2305460874
Short name T6
Test name
Test status
Simulation time 24473007642 ps
CPU time 14.04 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:26:28 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305460874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2305460874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4255305913
Short name T7
Test name
Test status
Simulation time 5306542915 ps
CPU time 15.38 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:26:28 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255305913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4255305913
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1360723808
Short name T2
Test name
Test status
Simulation time 6022217244 ps
CPU time 4.72 seconds
Started Oct 14 10:26:11 PM UTC 24
Finished Oct 14 10:26:17 PM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360723808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1360723808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1294853228
Short name T47
Test name
Test status
Simulation time 129801288996 ps
CPU time 371.45 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:32:28 PM UTC 24
Peak memory 220680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294853228 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.1294853228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1443508766
Short name T4
Test name
Test status
Simulation time 1133027449 ps
CPU time 9.59 seconds
Started Oct 14 10:26:12 PM UTC 24
Finished Oct 14 10:26:23 PM UTC 24
Peak memory 220564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1443508766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.adc_ctrl_stress_all_with_rand_reset.1443508766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3263425068
Short name T21
Test name
Test status
Simulation time 427615798 ps
CPU time 1.35 seconds
Started Oct 14 10:26:23 PM UTC 24
Finished Oct 14 10:26:26 PM UTC 24
Peak memory 208940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263425068 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3263425068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1862606145
Short name T46
Test name
Test status
Simulation time 166751652950 ps
CPU time 233.76 seconds
Started Oct 14 10:26:14 PM UTC 24
Finished Oct 14 10:30:11 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862606145 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.1862606145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3466405200
Short name T240
Test name
Test status
Simulation time 162413858177 ps
CPU time 612.23 seconds
Started Oct 14 10:26:15 PM UTC 24
Finished Oct 14 10:36:34 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466405200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3466405200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1155947286
Short name T238
Test name
Test status
Simulation time 326091653084 ps
CPU time 974.75 seconds
Started Oct 14 10:26:14 PM UTC 24
Finished Oct 14 10:42:38 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155947286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1155947286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.936725689
Short name T304
Test name
Test status
Simulation time 489609836232 ps
CPU time 599.6 seconds
Started Oct 14 10:26:14 PM UTC 24
Finished Oct 14 10:36:19 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936725689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.936725689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1792029247
Short name T168
Test name
Test status
Simulation time 494172980025 ps
CPU time 314.95 seconds
Started Oct 14 10:26:13 PM UTC 24
Finished Oct 14 10:31:31 PM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792029247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1792029247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.4094284677
Short name T134
Test name
Test status
Simulation time 162041729399 ps
CPU time 383.95 seconds
Started Oct 14 10:26:13 PM UTC 24
Finished Oct 14 10:32:41 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094284677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.4094284677
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4168705560
Short name T20
Test name
Test status
Simulation time 598455450545 ps
CPU time 168.61 seconds
Started Oct 14 10:26:14 PM UTC 24
Finished Oct 14 10:29:05 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168705560 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.4168705560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2999002223
Short name T52
Test name
Test status
Simulation time 69411391716 ps
CPU time 276.59 seconds
Started Oct 14 10:26:17 PM UTC 24
Finished Oct 14 10:30:57 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999002223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2999002223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3580348646
Short name T8
Test name
Test status
Simulation time 22583285504 ps
CPU time 12.16 seconds
Started Oct 14 10:26:16 PM UTC 24
Finished Oct 14 10:26:29 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580348646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3580348646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2559824431
Short name T23
Test name
Test status
Simulation time 8203263720 ps
CPU time 26.44 seconds
Started Oct 14 10:26:21 PM UTC 24
Finished Oct 14 10:26:49 PM UTC 24
Peak memory 242368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559824431 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2559824431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3096368507
Short name T3
Test name
Test status
Simulation time 5635091653 ps
CPU time 6.24 seconds
Started Oct 14 10:26:13 PM UTC 24
Finished Oct 14 10:26:20 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096368507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3096368507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1845503864
Short name T123
Test name
Test status
Simulation time 394484970816 ps
CPU time 572.57 seconds
Started Oct 14 10:26:20 PM UTC 24
Finished Oct 14 10:35:59 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845503864 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.1845503864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2773895186
Short name T383
Test name
Test status
Simulation time 454642726 ps
CPU time 2.6 seconds
Started Oct 14 10:37:39 PM UTC 24
Finished Oct 14 10:37:43 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773895186 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2773895186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.169810963
Short name T253
Test name
Test status
Simulation time 502308200719 ps
CPU time 1239.85 seconds
Started Oct 14 10:36:56 PM UTC 24
Finished Oct 14 10:57:47 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169810963 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.169810963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3677230319
Short name T239
Test name
Test status
Simulation time 168819892485 ps
CPU time 558.43 seconds
Started Oct 14 10:36:21 PM UTC 24
Finished Oct 14 10:45:46 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677230319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3677230319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.598388173
Short name T185
Test name
Test status
Simulation time 330135964828 ps
CPU time 67.12 seconds
Started Oct 14 10:36:21 PM UTC 24
Finished Oct 14 10:37:30 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598388173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.598388173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.4007467761
Short name T237
Test name
Test status
Simulation time 500425388675 ps
CPU time 356.42 seconds
Started Oct 14 10:36:18 PM UTC 24
Finished Oct 14 10:42:18 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007467761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4007467761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.4051432397
Short name T488
Test name
Test status
Simulation time 495669428669 ps
CPU time 1605.51 seconds
Started Oct 14 10:36:20 PM UTC 24
Finished Oct 14 11:03:22 PM UTC 24
Peak memory 212992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051432397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.4051432397
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3369613675
Short name T400
Test name
Test status
Simulation time 386093924807 ps
CPU time 437.75 seconds
Started Oct 14 10:36:35 PM UTC 24
Finished Oct 14 10:43:58 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369613675 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.3369613675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.4264698170
Short name T404
Test name
Test status
Simulation time 81198280409 ps
CPU time 437.28 seconds
Started Oct 14 10:37:17 PM UTC 24
Finished Oct 14 10:44:39 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264698170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4264698170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1723165797
Short name T196
Test name
Test status
Simulation time 36052021747 ps
CPU time 77.56 seconds
Started Oct 14 10:37:11 PM UTC 24
Finished Oct 14 10:38:30 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723165797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1723165797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3748657352
Short name T380
Test name
Test status
Simulation time 4686257012 ps
CPU time 10.27 seconds
Started Oct 14 10:36:59 PM UTC 24
Finished Oct 14 10:37:10 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748657352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3748657352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.604623658
Short name T379
Test name
Test status
Simulation time 5718128489 ps
CPU time 7.75 seconds
Started Oct 14 10:36:18 PM UTC 24
Finished Oct 14 10:36:27 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604623658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.604623658
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2186706335
Short name T303
Test name
Test status
Simulation time 332660474417 ps
CPU time 1360.84 seconds
Started Oct 14 10:37:31 PM UTC 24
Finished Oct 14 11:00:25 PM UTC 24
Peak memory 223444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186706335 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.2186706335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2423674172
Short name T255
Test name
Test status
Simulation time 3138046920 ps
CPU time 10.79 seconds
Started Oct 14 10:37:26 PM UTC 24
Finished Oct 14 10:37:38 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2423674172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.adc_ctrl_stress_all_with_rand_reset.2423674172
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.197578810
Short name T385
Test name
Test status
Simulation time 524007539 ps
CPU time 2.92 seconds
Started Oct 14 10:39:57 PM UTC 24
Finished Oct 14 10:40:02 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197578810 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.197578810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3054891980
Short name T127
Test name
Test status
Simulation time 526002794866 ps
CPU time 510.09 seconds
Started Oct 14 10:38:48 PM UTC 24
Finished Oct 14 10:47:23 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054891980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3054891980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1059790906
Short name T275
Test name
Test status
Simulation time 333137721262 ps
CPU time 1191.13 seconds
Started Oct 14 10:38:10 PM UTC 24
Finished Oct 14 10:58:14 PM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059790906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1059790906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4009879168
Short name T473
Test name
Test status
Simulation time 487704504552 ps
CPU time 1339.41 seconds
Started Oct 14 10:38:11 PM UTC 24
Finished Oct 14 11:00:43 PM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009879168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.4009879168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.542915435
Short name T241
Test name
Test status
Simulation time 329707602536 ps
CPU time 467.84 seconds
Started Oct 14 10:37:43 PM UTC 24
Finished Oct 14 10:45:37 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542915435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.542915435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3978303005
Short name T386
Test name
Test status
Simulation time 166690537817 ps
CPU time 117.55 seconds
Started Oct 14 10:38:08 PM UTC 24
Finished Oct 14 10:40:08 PM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978303005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.3978303005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3622525384
Short name T283
Test name
Test status
Simulation time 379102812652 ps
CPU time 561.65 seconds
Started Oct 14 10:38:14 PM UTC 24
Finished Oct 14 10:47:41 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622525384 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.3622525384
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.664813127
Short name T398
Test name
Test status
Simulation time 600527036051 ps
CPU time 306.64 seconds
Started Oct 14 10:38:21 PM UTC 24
Finished Oct 14 10:43:31 PM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664813127 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.664813127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.546364425
Short name T219
Test name
Test status
Simulation time 105765543208 ps
CPU time 390.26 seconds
Started Oct 14 10:39:21 PM UTC 24
Finished Oct 14 10:45:55 PM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546364425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.546364425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.3457788903
Short name T388
Test name
Test status
Simulation time 37473941340 ps
CPU time 91.28 seconds
Started Oct 14 10:39:17 PM UTC 24
Finished Oct 14 10:40:50 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457788903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3457788903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.520451370
Short name T199
Test name
Test status
Simulation time 3626371574 ps
CPU time 14.43 seconds
Started Oct 14 10:39:05 PM UTC 24
Finished Oct 14 10:39:20 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520451370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.520451370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2691050566
Short name T194
Test name
Test status
Simulation time 6005691937 ps
CPU time 26.69 seconds
Started Oct 14 10:37:42 PM UTC 24
Finished Oct 14 10:38:10 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691050566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2691050566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.687087348
Short name T189
Test name
Test status
Simulation time 750657490619 ps
CPU time 2209.38 seconds
Started Oct 14 10:39:52 PM UTC 24
Finished Oct 14 11:17:02 PM UTC 24
Peak memory 223348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687087348 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.687087348
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.637274256
Short name T247
Test name
Test status
Simulation time 244092818825 ps
CPU time 28.88 seconds
Started Oct 14 10:39:28 PM UTC 24
Finished Oct 14 10:39:58 PM UTC 24
Peak memory 220436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=637274256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.adc_ctrl_stress_all_with_rand_reset.637274256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2658601953
Short name T392
Test name
Test status
Simulation time 492890215 ps
CPU time 1.5 seconds
Started Oct 14 10:42:10 PM UTC 24
Finished Oct 14 10:42:12 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658601953 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2658601953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1559701329
Short name T417
Test name
Test status
Simulation time 167193098012 ps
CPU time 441.51 seconds
Started Oct 14 10:40:10 PM UTC 24
Finished Oct 14 10:47:36 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559701329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.1559701329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1958221493
Short name T161
Test name
Test status
Simulation time 491109845866 ps
CPU time 1307.41 seconds
Started Oct 14 10:40:02 PM UTC 24
Finished Oct 14 11:02:02 PM UTC 24
Peak memory 212864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958221493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1958221493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3807741609
Short name T416
Test name
Test status
Simulation time 163180784967 ps
CPU time 434.17 seconds
Started Oct 14 10:40:03 PM UTC 24
Finished Oct 14 10:47:22 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807741609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3807741609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.816844830
Short name T207
Test name
Test status
Simulation time 366555699286 ps
CPU time 462 seconds
Started Oct 14 10:40:49 PM UTC 24
Finished Oct 14 10:48:36 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816844830 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.816844830
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2840250802
Short name T397
Test name
Test status
Simulation time 613685212532 ps
CPU time 150.49 seconds
Started Oct 14 10:40:50 PM UTC 24
Finished Oct 14 10:43:23 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840250802 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.2840250802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3132180170
Short name T227
Test name
Test status
Simulation time 80284145432 ps
CPU time 471.88 seconds
Started Oct 14 10:41:42 PM UTC 24
Finished Oct 14 10:49:39 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132180170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3132180170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1173124312
Short name T396
Test name
Test status
Simulation time 43830855009 ps
CPU time 99.85 seconds
Started Oct 14 10:41:37 PM UTC 24
Finished Oct 14 10:43:18 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173124312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1173124312
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2862575363
Short name T391
Test name
Test status
Simulation time 4073789852 ps
CPU time 18.19 seconds
Started Oct 14 10:41:21 PM UTC 24
Finished Oct 14 10:41:41 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862575363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2862575363
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.223036741
Short name T387
Test name
Test status
Simulation time 6107406359 ps
CPU time 7.99 seconds
Started Oct 14 10:39:59 PM UTC 24
Finished Oct 14 10:40:09 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223036741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.223036741
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2787403317
Short name T261
Test name
Test status
Simulation time 502621347667 ps
CPU time 578.11 seconds
Started Oct 14 10:41:58 PM UTC 24
Finished Oct 14 10:51:42 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787403317 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.2787403317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4134728086
Short name T30
Test name
Test status
Simulation time 4589443131 ps
CPU time 10.73 seconds
Started Oct 14 10:41:45 PM UTC 24
Finished Oct 14 10:41:57 PM UTC 24
Peak memory 220736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4134728086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.adc_ctrl_stress_all_with_rand_reset.4134728086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1765032700
Short name T401
Test name
Test status
Simulation time 337400307 ps
CPU time 2.2 seconds
Started Oct 14 10:43:59 PM UTC 24
Finished Oct 14 10:44:02 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765032700 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1765032700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1389387508
Short name T300
Test name
Test status
Simulation time 169813929597 ps
CPU time 218.96 seconds
Started Oct 14 10:43:20 PM UTC 24
Finished Oct 14 10:47:02 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389387508 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.1389387508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.249354739
Short name T257
Test name
Test status
Simulation time 168599738306 ps
CPU time 134.6 seconds
Started Oct 14 10:42:28 PM UTC 24
Finished Oct 14 10:44:45 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249354739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.249354739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3492553847
Short name T411
Test name
Test status
Simulation time 326424620250 ps
CPU time 255.18 seconds
Started Oct 14 10:42:33 PM UTC 24
Finished Oct 14 10:46:52 PM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492553847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.3492553847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.3646690310
Short name T438
Test name
Test status
Simulation time 168066067742 ps
CPU time 589.15 seconds
Started Oct 14 10:42:19 PM UTC 24
Finished Oct 14 10:52:15 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646690310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3646690310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.3285159696
Short name T509
Test name
Test status
Simulation time 490581815611 ps
CPU time 1446.88 seconds
Started Oct 14 10:42:28 PM UTC 24
Finished Oct 14 11:06:49 PM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285159696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.3285159696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2978719264
Short name T427
Test name
Test status
Simulation time 603392433420 ps
CPU time 383.47 seconds
Started Oct 14 10:43:14 PM UTC 24
Finished Oct 14 10:49:42 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978719264 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.2978719264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2177028569
Short name T224
Test name
Test status
Simulation time 136320911569 ps
CPU time 646.03 seconds
Started Oct 14 10:43:34 PM UTC 24
Finished Oct 14 10:54:26 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177028569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2177028569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3984866897
Short name T403
Test name
Test status
Simulation time 35458702794 ps
CPU time 56.04 seconds
Started Oct 14 10:43:32 PM UTC 24
Finished Oct 14 10:44:29 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984866897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3984866897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3909585148
Short name T399
Test name
Test status
Simulation time 3900515567 ps
CPU time 9.55 seconds
Started Oct 14 10:43:24 PM UTC 24
Finished Oct 14 10:43:35 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909585148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3909585148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2803121606
Short name T393
Test name
Test status
Simulation time 5879636444 ps
CPU time 13.4 seconds
Started Oct 14 10:42:13 PM UTC 24
Finished Oct 14 10:42:28 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803121606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2803121606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2804197052
Short name T233
Test name
Test status
Simulation time 135911934173 ps
CPU time 494.13 seconds
Started Oct 14 10:43:59 PM UTC 24
Finished Oct 14 10:52:18 PM UTC 24
Peak memory 220800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804197052 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.2804197052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.1840312673
Short name T406
Test name
Test status
Simulation time 427470048 ps
CPU time 1.29 seconds
Started Oct 14 10:45:47 PM UTC 24
Finished Oct 14 10:45:49 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840312673 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1840312673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2120305221
Short name T213
Test name
Test status
Simulation time 588564946447 ps
CPU time 100.06 seconds
Started Oct 14 10:45:05 PM UTC 24
Finished Oct 14 10:46:47 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120305221 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.2120305221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.4134157904
Short name T309
Test name
Test status
Simulation time 167133450462 ps
CPU time 246.66 seconds
Started Oct 14 10:45:08 PM UTC 24
Finished Oct 14 10:49:18 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134157904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4134157904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3721514730
Short name T487
Test name
Test status
Simulation time 483000128251 ps
CPU time 1111.2 seconds
Started Oct 14 10:44:31 PM UTC 24
Finished Oct 14 11:03:13 PM UTC 24
Peak memory 212984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721514730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.3721514730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.1558992873
Short name T464
Test name
Test status
Simulation time 496276195785 ps
CPU time 789.43 seconds
Started Oct 14 10:44:29 PM UTC 24
Finished Oct 14 10:57:48 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558992873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.1558992873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2788107727
Short name T297
Test name
Test status
Simulation time 374342674036 ps
CPU time 952.9 seconds
Started Oct 14 10:44:40 PM UTC 24
Finished Oct 14 11:00:41 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788107727 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.2788107727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2473726401
Short name T430
Test name
Test status
Simulation time 409005411023 ps
CPU time 335.63 seconds
Started Oct 14 10:44:46 PM UTC 24
Finished Oct 14 10:50:26 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473726401 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.2473726401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2315106195
Short name T225
Test name
Test status
Simulation time 131320006446 ps
CPU time 648.67 seconds
Started Oct 14 10:45:18 PM UTC 24
Finished Oct 14 10:56:13 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315106195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2315106195
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.642945889
Short name T409
Test name
Test status
Simulation time 27131884709 ps
CPU time 51.38 seconds
Started Oct 14 10:45:15 PM UTC 24
Finished Oct 14 10:46:08 PM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642945889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.642945889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2246050041
Short name T405
Test name
Test status
Simulation time 4947008329 ps
CPU time 20.97 seconds
Started Oct 14 10:45:10 PM UTC 24
Finished Oct 14 10:45:33 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246050041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2246050041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1442377555
Short name T402
Test name
Test status
Simulation time 5823707560 ps
CPU time 24.36 seconds
Started Oct 14 10:44:03 PM UTC 24
Finished Oct 14 10:44:29 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442377555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1442377555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1410488831
Short name T232
Test name
Test status
Simulation time 279330351706 ps
CPU time 444.59 seconds
Started Oct 14 10:45:38 PM UTC 24
Finished Oct 14 10:53:07 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410488831 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.1410488831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1072823777
Short name T407
Test name
Test status
Simulation time 1476391886 ps
CPU time 17.51 seconds
Started Oct 14 10:45:34 PM UTC 24
Finished Oct 14 10:45:52 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1072823777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.adc_ctrl_stress_all_with_rand_reset.1072823777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2441667422
Short name T413
Test name
Test status
Simulation time 354043791 ps
CPU time 2.3 seconds
Started Oct 14 10:47:03 PM UTC 24
Finished Oct 14 10:47:06 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441667422 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2441667422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.3450786988
Short name T324
Test name
Test status
Simulation time 325699560220 ps
CPU time 820.33 seconds
Started Oct 14 10:45:58 PM UTC 24
Finished Oct 14 10:59:47 PM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450786988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3450786988
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2768905279
Short name T172
Test name
Test status
Simulation time 320047304963 ps
CPU time 142.1 seconds
Started Oct 14 10:46:07 PM UTC 24
Finished Oct 14 10:48:32 PM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768905279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.2768905279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.3201341678
Short name T302
Test name
Test status
Simulation time 487851366692 ps
CPU time 401.82 seconds
Started Oct 14 10:45:53 PM UTC 24
Finished Oct 14 10:52:40 PM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201341678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3201341678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.512806826
Short name T437
Test name
Test status
Simulation time 490914815217 ps
CPU time 336.5 seconds
Started Oct 14 10:45:56 PM UTC 24
Finished Oct 14 10:51:36 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512806826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.512806826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.2276518531
Short name T299
Test name
Test status
Simulation time 344673367632 ps
CPU time 1067.17 seconds
Started Oct 14 10:46:08 PM UTC 24
Finished Oct 14 11:04:06 PM UTC 24
Peak memory 212928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276518531 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.2276518531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.657913932
Short name T500
Test name
Test status
Simulation time 390697044679 ps
CPU time 1142.53 seconds
Started Oct 14 10:46:09 PM UTC 24
Finished Oct 14 11:05:23 PM UTC 24
Peak memory 212856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657913932 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.657913932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2113896766
Short name T425
Test name
Test status
Simulation time 39750229454 ps
CPU time 147.76 seconds
Started Oct 14 10:46:53 PM UTC 24
Finished Oct 14 10:49:23 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113896766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2113896766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1025530135
Short name T412
Test name
Test status
Simulation time 3555997946 ps
CPU time 9.81 seconds
Started Oct 14 10:46:48 PM UTC 24
Finished Oct 14 10:46:58 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025530135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1025530135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3044860477
Short name T408
Test name
Test status
Simulation time 5622225505 ps
CPU time 5.32 seconds
Started Oct 14 10:45:50 PM UTC 24
Finished Oct 14 10:45:57 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044860477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3044860477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2904196152
Short name T414
Test name
Test status
Simulation time 8064296714 ps
CPU time 10.19 seconds
Started Oct 14 10:47:01 PM UTC 24
Finished Oct 14 10:47:12 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904196152 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.2904196152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1082035113
Short name T76
Test name
Test status
Simulation time 7641168750 ps
CPU time 8.21 seconds
Started Oct 14 10:46:59 PM UTC 24
Finished Oct 14 10:47:08 PM UTC 24
Peak memory 220456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1082035113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.adc_ctrl_stress_all_with_rand_reset.1082035113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2753054067
Short name T420
Test name
Test status
Simulation time 309996354 ps
CPU time 1.06 seconds
Started Oct 14 10:48:02 PM UTC 24
Finished Oct 14 10:48:04 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753054067 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2753054067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.1853794623
Short name T264
Test name
Test status
Simulation time 347118164597 ps
CPU time 853.23 seconds
Started Oct 14 10:47:24 PM UTC 24
Finished Oct 14 11:01:46 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853794623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1853794623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3691129999
Short name T214
Test name
Test status
Simulation time 486461270485 ps
CPU time 303.31 seconds
Started Oct 14 10:47:10 PM UTC 24
Finished Oct 14 10:52:17 PM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691129999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3691129999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2354883137
Short name T435
Test name
Test status
Simulation time 333323591442 ps
CPU time 246.14 seconds
Started Oct 14 10:47:13 PM UTC 24
Finished Oct 14 10:51:23 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354883137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.2354883137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.964025307
Short name T157
Test name
Test status
Simulation time 332421732898 ps
CPU time 153.26 seconds
Started Oct 14 10:47:08 PM UTC 24
Finished Oct 14 10:49:44 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964025307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.964025307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.3910412053
Short name T423
Test name
Test status
Simulation time 164970634133 ps
CPU time 120.76 seconds
Started Oct 14 10:47:09 PM UTC 24
Finished Oct 14 10:49:12 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910412053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.3910412053
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.1107159221
Short name T178
Test name
Test status
Simulation time 637668021909 ps
CPU time 1503.65 seconds
Started Oct 14 10:47:16 PM UTC 24
Finished Oct 14 11:12:35 PM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107159221 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.1107159221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2353165667
Short name T453
Test name
Test status
Simulation time 598267363428 ps
CPU time 490.1 seconds
Started Oct 14 10:47:21 PM UTC 24
Finished Oct 14 10:55:37 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353165667 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.2353165667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.3583204529
Short name T455
Test name
Test status
Simulation time 75888152444 ps
CPU time 493.66 seconds
Started Oct 14 10:47:42 PM UTC 24
Finished Oct 14 10:56:00 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583204529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3583204529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.4165887949
Short name T206
Test name
Test status
Simulation time 27517431646 ps
CPU time 45.57 seconds
Started Oct 14 10:47:37 PM UTC 24
Finished Oct 14 10:48:24 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165887949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4165887949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2172385996
Short name T418
Test name
Test status
Simulation time 2859065593 ps
CPU time 6.81 seconds
Started Oct 14 10:47:37 PM UTC 24
Finished Oct 14 10:47:44 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172385996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2172385996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1360130728
Short name T415
Test name
Test status
Simulation time 5825910949 ps
CPU time 7.24 seconds
Started Oct 14 10:47:07 PM UTC 24
Finished Oct 14 10:47:15 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360130728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1360130728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.1794704455
Short name T36
Test name
Test status
Simulation time 519128592328 ps
CPU time 1387.17 seconds
Started Oct 14 10:47:49 PM UTC 24
Finished Oct 14 11:11:09 PM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794704455 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.1794704455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3820516315
Short name T419
Test name
Test status
Simulation time 2920445930 ps
CPU time 13.75 seconds
Started Oct 14 10:47:46 PM UTC 24
Finished Oct 14 10:48:01 PM UTC 24
Peak memory 210112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3820516315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.adc_ctrl_stress_all_with_rand_reset.3820516315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2795143210
Short name T424
Test name
Test status
Simulation time 433082958 ps
CPU time 1.75 seconds
Started Oct 14 10:49:11 PM UTC 24
Finished Oct 14 10:49:13 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795143210 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2795143210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3421771982
Short name T294
Test name
Test status
Simulation time 513758925963 ps
CPU time 1625.8 seconds
Started Oct 14 10:48:24 PM UTC 24
Finished Oct 14 11:15:45 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421771982 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.3421771982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.3624269074
Short name T263
Test name
Test status
Simulation time 331847963370 ps
CPU time 754.36 seconds
Started Oct 14 10:48:27 PM UTC 24
Finished Oct 14 11:01:09 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624269074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3624269074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.108802614
Short name T521
Test name
Test status
Simulation time 502711889835 ps
CPU time 1274.28 seconds
Started Oct 14 10:48:19 PM UTC 24
Finished Oct 14 11:09:45 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108802614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.108802614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3299394598
Short name T160
Test name
Test status
Simulation time 488529687386 ps
CPU time 799.46 seconds
Started Oct 14 10:48:06 PM UTC 24
Finished Oct 14 11:01:34 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299394598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3299394598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1942373199
Short name T432
Test name
Test status
Simulation time 159240850885 ps
CPU time 152.6 seconds
Started Oct 14 10:48:10 PM UTC 24
Finished Oct 14 10:50:44 PM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942373199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1942373199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3723063250
Short name T332
Test name
Test status
Simulation time 174444554425 ps
CPU time 316.38 seconds
Started Oct 14 10:48:19 PM UTC 24
Finished Oct 14 10:53:39 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723063250 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.3723063250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1339708428
Short name T475
Test name
Test status
Simulation time 605590478442 ps
CPU time 736.57 seconds
Started Oct 14 10:48:24 PM UTC 24
Finished Oct 14 11:00:48 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339708428 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.1339708428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1032363340
Short name T510
Test name
Test status
Simulation time 129160590652 ps
CPU time 1102.29 seconds
Started Oct 14 10:48:49 PM UTC 24
Finished Oct 14 11:07:23 PM UTC 24
Peak memory 213064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032363340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1032363340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1469875163
Short name T210
Test name
Test status
Simulation time 39630165024 ps
CPU time 27.99 seconds
Started Oct 14 10:48:37 PM UTC 24
Finished Oct 14 10:49:07 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469875163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1469875163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.4029211542
Short name T208
Test name
Test status
Simulation time 3017429266 ps
CPU time 14.2 seconds
Started Oct 14 10:48:33 PM UTC 24
Finished Oct 14 10:48:49 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029211542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4029211542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1302602250
Short name T421
Test name
Test status
Simulation time 6031381908 ps
CPU time 3.84 seconds
Started Oct 14 10:48:04 PM UTC 24
Finished Oct 14 10:48:09 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302602250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1302602250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3914548345
Short name T31
Test name
Test status
Simulation time 4233315680 ps
CPU time 18.32 seconds
Started Oct 14 10:48:50 PM UTC 24
Finished Oct 14 10:49:10 PM UTC 24
Peak memory 220460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3914548345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.adc_ctrl_stress_all_with_rand_reset.3914548345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1507286141
Short name T434
Test name
Test status
Simulation time 434160868 ps
CPU time 1.19 seconds
Started Oct 14 10:51:19 PM UTC 24
Finished Oct 14 10:51:21 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507286141 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1507286141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3716264508
Short name T260
Test name
Test status
Simulation time 164787799175 ps
CPU time 120.51 seconds
Started Oct 14 10:49:45 PM UTC 24
Finished Oct 14 10:51:48 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716264508 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3716264508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.389065290
Short name T158
Test name
Test status
Simulation time 520117866886 ps
CPU time 629.07 seconds
Started Oct 14 10:50:02 PM UTC 24
Finished Oct 14 11:00:38 PM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389065290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.389065290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1339223369
Short name T271
Test name
Test status
Simulation time 326855957110 ps
CPU time 271.03 seconds
Started Oct 14 10:49:24 PM UTC 24
Finished Oct 14 10:53:59 PM UTC 24
Peak memory 210076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339223369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1339223369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.495739473
Short name T462
Test name
Test status
Simulation time 484269737226 ps
CPU time 426.55 seconds
Started Oct 14 10:49:26 PM UTC 24
Finished Oct 14 10:56:38 PM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495739473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.495739473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.1185006069
Short name T529
Test name
Test status
Simulation time 497590465120 ps
CPU time 1334.01 seconds
Started Oct 14 10:49:14 PM UTC 24
Finished Oct 14 11:11:40 PM UTC 24
Peak memory 212992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185006069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1185006069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.92711287
Short name T433
Test name
Test status
Simulation time 162779774979 ps
CPU time 117.56 seconds
Started Oct 14 10:49:19 PM UTC 24
Finished Oct 14 10:51:19 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92711287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.92711287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3098170040
Short name T569
Test name
Test status
Simulation time 586691430833 ps
CPU time 1697.24 seconds
Started Oct 14 10:49:43 PM UTC 24
Finished Oct 14 11:18:16 PM UTC 24
Peak memory 212764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098170040 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.3098170040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1117482826
Short name T443
Test name
Test status
Simulation time 39502454302 ps
CPU time 158.46 seconds
Started Oct 14 10:50:26 PM UTC 24
Finished Oct 14 10:53:07 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117482826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1117482826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1887596595
Short name T431
Test name
Test status
Simulation time 4343228419 ps
CPU time 18.37 seconds
Started Oct 14 10:50:09 PM UTC 24
Finished Oct 14 10:50:29 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887596595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1887596595
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.333492668
Short name T426
Test name
Test status
Simulation time 5639302276 ps
CPU time 10.99 seconds
Started Oct 14 10:49:13 PM UTC 24
Finished Oct 14 10:49:25 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333492668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.333492668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.3296904492
Short name T339
Test name
Test status
Simulation time 370862222711 ps
CPU time 297.15 seconds
Started Oct 14 10:51:04 PM UTC 24
Finished Oct 14 10:56:05 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296904492 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.3296904492
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1758252620
Short name T270
Test name
Test status
Simulation time 21135351414 ps
CPU time 16.28 seconds
Started Oct 14 10:50:46 PM UTC 24
Finished Oct 14 10:51:03 PM UTC 24
Peak memory 220576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1758252620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.adc_ctrl_stress_all_with_rand_reset.1758252620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.593377430
Short name T441
Test name
Test status
Simulation time 519375301 ps
CPU time 2.91 seconds
Started Oct 14 10:52:46 PM UTC 24
Finished Oct 14 10:52:50 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593377430 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.593377430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3497304542
Short name T284
Test name
Test status
Simulation time 327537295280 ps
CPU time 81.35 seconds
Started Oct 14 10:52:07 PM UTC 24
Finished Oct 14 10:53:30 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497304542 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.3497304542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.3556056531
Short name T292
Test name
Test status
Simulation time 158461375370 ps
CPU time 21.65 seconds
Started Oct 14 10:52:16 PM UTC 24
Finished Oct 14 10:52:39 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556056531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3556056531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3492239048
Short name T351
Test name
Test status
Simulation time 494851612627 ps
CPU time 1524.8 seconds
Started Oct 14 10:51:37 PM UTC 24
Finished Oct 14 11:17:17 PM UTC 24
Peak memory 212816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492239048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3492239048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1923027703
Short name T466
Test name
Test status
Simulation time 487276816940 ps
CPU time 411.17 seconds
Started Oct 14 10:51:43 PM UTC 24
Finished Oct 14 10:58:40 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923027703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.1923027703
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.2626841012
Short name T460
Test name
Test status
Simulation time 340224396262 ps
CPU time 300.01 seconds
Started Oct 14 10:51:24 PM UTC 24
Finished Oct 14 10:56:28 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626841012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2626841012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.732321495
Short name T535
Test name
Test status
Simulation time 495711066903 ps
CPU time 1264.22 seconds
Started Oct 14 10:51:28 PM UTC 24
Finished Oct 14 11:12:45 PM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732321495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.732321495
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1676635217
Short name T458
Test name
Test status
Simulation time 385210965412 ps
CPU time 261.06 seconds
Started Oct 14 10:51:52 PM UTC 24
Finished Oct 14 10:56:16 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676635217 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.1676635217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.3502819339
Short name T220
Test name
Test status
Simulation time 92852551175 ps
CPU time 421.31 seconds
Started Oct 14 10:52:39 PM UTC 24
Finished Oct 14 10:59:44 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502819339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3502819339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2573823873
Short name T449
Test name
Test status
Simulation time 44628843766 ps
CPU time 170.22 seconds
Started Oct 14 10:52:19 PM UTC 24
Finished Oct 14 10:55:12 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573823873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2573823873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.4030029705
Short name T439
Test name
Test status
Simulation time 4874585756 ps
CPU time 20.61 seconds
Started Oct 14 10:52:18 PM UTC 24
Finished Oct 14 10:52:40 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030029705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4030029705
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.2733666953
Short name T436
Test name
Test status
Simulation time 5915599004 ps
CPU time 3.51 seconds
Started Oct 14 10:51:22 PM UTC 24
Finished Oct 14 10:51:27 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733666953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2733666953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.4092182074
Short name T273
Test name
Test status
Simulation time 399171786331 ps
CPU time 673.34 seconds
Started Oct 14 10:52:40 PM UTC 24
Finished Oct 14 11:04:00 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092182074 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.4092182074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2135264290
Short name T440
Test name
Test status
Simulation time 832385817 ps
CPU time 4.42 seconds
Started Oct 14 10:52:40 PM UTC 24
Finished Oct 14 10:52:46 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2135264290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.adc_ctrl_stress_all_with_rand_reset.2135264290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1102166838
Short name T24
Test name
Test status
Simulation time 505636171 ps
CPU time 1.83 seconds
Started Oct 14 10:26:50 PM UTC 24
Finished Oct 14 10:26:52 PM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102166838 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1102166838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1100850456
Short name T126
Test name
Test status
Simulation time 361001904281 ps
CPU time 1110.37 seconds
Started Oct 14 10:26:33 PM UTC 24
Finished Oct 14 10:45:15 PM UTC 24
Peak memory 213064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100850456 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.1100850456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1422819273
Short name T39
Test name
Test status
Simulation time 177444251309 ps
CPU time 178.08 seconds
Started Oct 14 10:26:34 PM UTC 24
Finished Oct 14 10:29:35 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422819273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1422819273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.1544055415
Short name T173
Test name
Test status
Simulation time 164233271656 ps
CPU time 214.59 seconds
Started Oct 14 10:26:28 PM UTC 24
Finished Oct 14 10:30:05 PM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544055415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1544055415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2770807591
Short name T198
Test name
Test status
Simulation time 330823236828 ps
CPU time 747.67 seconds
Started Oct 14 10:26:29 PM UTC 24
Finished Oct 14 10:39:04 PM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770807591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.2770807591
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1406290118
Short name T258
Test name
Test status
Simulation time 493738268097 ps
CPU time 1230.21 seconds
Started Oct 14 10:26:27 PM UTC 24
Finished Oct 14 10:47:09 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406290118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1406290118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2488673302
Short name T37
Test name
Test status
Simulation time 163889274268 ps
CPU time 155.53 seconds
Started Oct 14 10:26:28 PM UTC 24
Finished Oct 14 10:29:06 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488673302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.2488673302
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2600076925
Short name T140
Test name
Test status
Simulation time 461425653826 ps
CPU time 323.03 seconds
Started Oct 14 10:26:29 PM UTC 24
Finished Oct 14 10:31:56 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600076925 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.2600076925
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3400059186
Short name T164
Test name
Test status
Simulation time 199389712241 ps
CPU time 288.46 seconds
Started Oct 14 10:26:30 PM UTC 24
Finished Oct 14 10:31:22 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400059186 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.3400059186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.351473427
Short name T51
Test name
Test status
Simulation time 78499115672 ps
CPU time 421.01 seconds
Started Oct 14 10:26:44 PM UTC 24
Finished Oct 14 10:33:50 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351473427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.351473427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.685062091
Short name T40
Test name
Test status
Simulation time 33176190539 ps
CPU time 33.55 seconds
Started Oct 14 10:26:42 PM UTC 24
Finished Oct 14 10:27:17 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685062091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.685062091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1799194912
Short name T12
Test name
Test status
Simulation time 4760610195 ps
CPU time 3.43 seconds
Started Oct 14 10:26:41 PM UTC 24
Finished Oct 14 10:26:46 PM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799194912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1799194912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1231718106
Short name T27
Test name
Test status
Simulation time 4333668678 ps
CPU time 19.47 seconds
Started Oct 14 10:26:50 PM UTC 24
Finished Oct 14 10:27:10 PM UTC 24
Peak memory 242368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231718106 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1231718106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.702193318
Short name T9
Test name
Test status
Simulation time 5888957992 ps
CPU time 6.54 seconds
Started Oct 14 10:26:25 PM UTC 24
Finished Oct 14 10:26:32 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702193318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.702193318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2926640109
Short name T25
Test name
Test status
Simulation time 1254849016 ps
CPU time 5.73 seconds
Started Oct 14 10:26:46 PM UTC 24
Finished Oct 14 10:26:53 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926640109 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.2926640109
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1477444030
Short name T13
Test name
Test status
Simulation time 8618961435 ps
CPU time 11.85 seconds
Started Oct 14 10:26:46 PM UTC 24
Finished Oct 14 10:26:59 PM UTC 24
Peak memory 220444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1477444030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.adc_ctrl_stress_all_with_rand_reset.1477444030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.3740540403
Short name T450
Test name
Test status
Simulation time 387058226 ps
CPU time 1.71 seconds
Started Oct 14 10:55:12 PM UTC 24
Finished Oct 14 10:55:14 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740540403 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3740540403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2073280360
Short name T347
Test name
Test status
Simulation time 163197911080 ps
CPU time 416.77 seconds
Started Oct 14 10:54:00 PM UTC 24
Finished Oct 14 11:01:02 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073280360 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.2073280360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.3052309863
Short name T175
Test name
Test status
Simulation time 162345890135 ps
CPU time 95.65 seconds
Started Oct 14 10:53:09 PM UTC 24
Finished Oct 14 10:54:46 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052309863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3052309863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3080000061
Short name T448
Test name
Test status
Simulation time 169613718250 ps
CPU time 95.01 seconds
Started Oct 14 10:53:12 PM UTC 24
Finished Oct 14 10:54:48 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080000061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.3080000061
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.2444136721
Short name T456
Test name
Test status
Simulation time 326473144262 ps
CPU time 188.63 seconds
Started Oct 14 10:52:53 PM UTC 24
Finished Oct 14 10:56:05 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444136721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2444136721
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.1262426436
Short name T511
Test name
Test status
Simulation time 336000252061 ps
CPU time 859.76 seconds
Started Oct 14 10:53:07 PM UTC 24
Finished Oct 14 11:07:35 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262426436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.1262426436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3137934550
Short name T523
Test name
Test status
Simulation time 407070562633 ps
CPU time 1014.28 seconds
Started Oct 14 10:53:40 PM UTC 24
Finished Oct 14 11:10:44 PM UTC 24
Peak memory 212768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137934550 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.3137934550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1389946291
Short name T228
Test name
Test status
Simulation time 121229546360 ps
CPU time 790.06 seconds
Started Oct 14 10:54:27 PM UTC 24
Finished Oct 14 11:07:46 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389946291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1389946291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.1429934886
Short name T454
Test name
Test status
Simulation time 31340781553 ps
CPU time 95.92 seconds
Started Oct 14 10:54:16 PM UTC 24
Finished Oct 14 10:55:54 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429934886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1429934886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.1792444403
Short name T447
Test name
Test status
Simulation time 4913996857 ps
CPU time 3.56 seconds
Started Oct 14 10:54:11 PM UTC 24
Finished Oct 14 10:54:16 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792444403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1792444403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.2456961126
Short name T444
Test name
Test status
Simulation time 5737421673 ps
CPU time 17.96 seconds
Started Oct 14 10:52:51 PM UTC 24
Finished Oct 14 10:53:10 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456961126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2456961126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.1490842793
Short name T495
Test name
Test status
Simulation time 195417880615 ps
CPU time 594.91 seconds
Started Oct 14 10:54:50 PM UTC 24
Finished Oct 14 11:04:51 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490842793 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.1490842793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1612629587
Short name T86
Test name
Test status
Simulation time 16976501092 ps
CPU time 22.9 seconds
Started Oct 14 10:54:46 PM UTC 24
Finished Oct 14 10:55:11 PM UTC 24
Peak memory 220376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1612629587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.adc_ctrl_stress_all_with_rand_reset.1612629587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.388339181
Short name T459
Test name
Test status
Simulation time 496428152 ps
CPU time 2.84 seconds
Started Oct 14 10:56:23 PM UTC 24
Finished Oct 14 10:56:27 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388339181 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.388339181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.483695502
Short name T296
Test name
Test status
Simulation time 514089534343 ps
CPU time 1338.01 seconds
Started Oct 14 10:56:01 PM UTC 24
Finished Oct 14 11:18:32 PM UTC 24
Peak memory 212792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483695502 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.483695502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.232137677
Short name T479
Test name
Test status
Simulation time 165535049480 ps
CPU time 332.04 seconds
Started Oct 14 10:55:37 PM UTC 24
Finished Oct 14 11:01:13 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232137677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.232137677
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.968977432
Short name T516
Test name
Test status
Simulation time 338376473912 ps
CPU time 764.3 seconds
Started Oct 14 10:55:38 PM UTC 24
Finished Oct 14 11:08:30 PM UTC 24
Peak memory 210172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968977432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.968977432
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.2296971767
Short name T215
Test name
Test status
Simulation time 327445874852 ps
CPU time 65.9 seconds
Started Oct 14 10:55:15 PM UTC 24
Finished Oct 14 10:56:22 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296971767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2296971767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.1471537767
Short name T470
Test name
Test status
Simulation time 166625335438 ps
CPU time 239.83 seconds
Started Oct 14 10:55:30 PM UTC 24
Finished Oct 14 10:59:33 PM UTC 24
Peak memory 210044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471537767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.1471537767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1313043175
Short name T635
Test name
Test status
Simulation time 600885967181 ps
CPU time 1829.47 seconds
Started Oct 14 10:55:55 PM UTC 24
Finished Oct 14 11:26:42 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313043175 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.1313043175
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.468517243
Short name T370
Test name
Test status
Simulation time 110413531160 ps
CPU time 447.01 seconds
Started Oct 14 10:56:14 PM UTC 24
Finished Oct 14 11:03:45 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468517243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.468517243
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.3809565642
Short name T463
Test name
Test status
Simulation time 33299120155 ps
CPU time 39.96 seconds
Started Oct 14 10:56:14 PM UTC 24
Finished Oct 14 10:56:55 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809565642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3809565642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.4045776361
Short name T457
Test name
Test status
Simulation time 5609526535 ps
CPU time 6.73 seconds
Started Oct 14 10:56:05 PM UTC 24
Finished Oct 14 10:56:13 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045776361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4045776361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.1671747224
Short name T451
Test name
Test status
Simulation time 6105990521 ps
CPU time 14.95 seconds
Started Oct 14 10:55:13 PM UTC 24
Finished Oct 14 10:55:29 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671747224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1671747224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1135778387
Short name T274
Test name
Test status
Simulation time 367181656524 ps
CPU time 159.36 seconds
Started Oct 14 10:56:23 PM UTC 24
Finished Oct 14 10:59:04 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135778387 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.1135778387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.327243979
Short name T32
Test name
Test status
Simulation time 17419290859 ps
CPU time 29.28 seconds
Started Oct 14 10:56:17 PM UTC 24
Finished Oct 14 10:56:47 PM UTC 24
Peak memory 226936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=327243979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
21.adc_ctrl_stress_all_with_rand_reset.327243979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.3071198323
Short name T467
Test name
Test status
Simulation time 454531442 ps
CPU time 1.37 seconds
Started Oct 14 10:58:40 PM UTC 24
Finished Oct 14 10:58:43 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071198323 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3071198323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3791414163
Short name T276
Test name
Test status
Simulation time 493781358808 ps
CPU time 438.12 seconds
Started Oct 14 10:56:38 PM UTC 24
Finished Oct 14 11:04:02 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791414163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3791414163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.446133403
Short name T494
Test name
Test status
Simulation time 160782404897 ps
CPU time 482.2 seconds
Started Oct 14 10:56:42 PM UTC 24
Finished Oct 14 11:04:49 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446133403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.446133403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.146320967
Short name T314
Test name
Test status
Simulation time 492172355998 ps
CPU time 333.52 seconds
Started Oct 14 10:56:29 PM UTC 24
Finished Oct 14 11:02:06 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146320967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.146320967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.3022627737
Short name T471
Test name
Test status
Simulation time 505521021436 ps
CPU time 230.9 seconds
Started Oct 14 10:56:36 PM UTC 24
Finished Oct 14 11:00:30 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022627737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.3022627737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.3699590031
Short name T333
Test name
Test status
Simulation time 428522701080 ps
CPU time 503.83 seconds
Started Oct 14 10:56:45 PM UTC 24
Finished Oct 14 11:05:15 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699590031 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.3699590031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1789838817
Short name T586
Test name
Test status
Simulation time 597830567372 ps
CPU time 1409.22 seconds
Started Oct 14 10:56:48 PM UTC 24
Finished Oct 14 11:20:32 PM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789838817 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.1789838817
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.1412851320
Short name T231
Test name
Test status
Simulation time 86947256366 ps
CPU time 379.79 seconds
Started Oct 14 10:57:49 PM UTC 24
Finished Oct 14 11:04:13 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412851320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1412851320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.2634675939
Short name T469
Test name
Test status
Simulation time 45904761519 ps
CPU time 85.52 seconds
Started Oct 14 10:57:48 PM UTC 24
Finished Oct 14 10:59:15 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634675939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2634675939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.4272336807
Short name T465
Test name
Test status
Simulation time 3784731668 ps
CPU time 8.42 seconds
Started Oct 14 10:57:44 PM UTC 24
Finished Oct 14 10:57:53 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272336807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4272336807
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.1429146264
Short name T461
Test name
Test status
Simulation time 6225103017 ps
CPU time 6.41 seconds
Started Oct 14 10:56:28 PM UTC 24
Finished Oct 14 10:56:35 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429146264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1429146264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.1497528123
Short name T474
Test name
Test status
Simulation time 466106210 ps
CPU time 2.48 seconds
Started Oct 14 11:00:42 PM UTC 24
Finished Oct 14 11:00:46 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497528123 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1497528123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.451263770
Short name T567
Test name
Test status
Simulation time 463150597340 ps
CPU time 1083.39 seconds
Started Oct 14 10:59:48 PM UTC 24
Finished Oct 14 11:18:02 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451263770 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.451263770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3955688570
Short name T483
Test name
Test status
Simulation time 325290754780 ps
CPU time 189.9 seconds
Started Oct 14 10:59:16 PM UTC 24
Finished Oct 14 11:02:28 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955688570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.3955688570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.3451112706
Short name T290
Test name
Test status
Simulation time 323764350265 ps
CPU time 241.55 seconds
Started Oct 14 10:58:59 PM UTC 24
Finished Oct 14 11:03:04 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451112706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3451112706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1677362663
Short name T484
Test name
Test status
Simulation time 492145603465 ps
CPU time 205.43 seconds
Started Oct 14 10:59:05 PM UTC 24
Finished Oct 14 11:02:34 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677362663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1677362663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.683136316
Short name T286
Test name
Test status
Simulation time 543474929568 ps
CPU time 1195.89 seconds
Started Oct 14 10:59:34 PM UTC 24
Finished Oct 14 11:19:41 PM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683136316 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.683136316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.698176758
Short name T596
Test name
Test status
Simulation time 403025612364 ps
CPU time 1270.13 seconds
Started Oct 14 10:59:46 PM UTC 24
Finished Oct 14 11:21:09 PM UTC 24
Peak memory 212704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698176758 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.698176758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.1930507530
Short name T477
Test name
Test status
Simulation time 45496930297 ps
CPU time 21.96 seconds
Started Oct 14 11:00:31 PM UTC 24
Finished Oct 14 11:00:54 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930507530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1930507530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.4191447803
Short name T472
Test name
Test status
Simulation time 3478660779 ps
CPU time 8.21 seconds
Started Oct 14 11:00:26 PM UTC 24
Finished Oct 14 11:00:35 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191447803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4191447803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.3355077419
Short name T468
Test name
Test status
Simulation time 5861850309 ps
CPU time 19.94 seconds
Started Oct 14 10:58:43 PM UTC 24
Finished Oct 14 10:59:04 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355077419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3355077419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.889668170
Short name T249
Test name
Test status
Simulation time 371522245163 ps
CPU time 218.08 seconds
Started Oct 14 11:00:42 PM UTC 24
Finished Oct 14 11:04:23 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889668170 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.889668170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2586572287
Short name T33
Test name
Test status
Simulation time 1918104063 ps
CPU time 4.42 seconds
Started Oct 14 11:00:38 PM UTC 24
Finished Oct 14 11:00:44 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2586572287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.adc_ctrl_stress_all_with_rand_reset.2586572287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.3378441497
Short name T481
Test name
Test status
Simulation time 287253352 ps
CPU time 2.14 seconds
Started Oct 14 11:01:35 PM UTC 24
Finished Oct 14 11:01:38 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378441497 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3378441497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.3320761090
Short name T329
Test name
Test status
Simulation time 191089493377 ps
CPU time 201.26 seconds
Started Oct 14 11:01:06 PM UTC 24
Finished Oct 14 11:04:30 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320761090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3320761090
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.1730884308
Short name T336
Test name
Test status
Simulation time 328678751763 ps
CPU time 304.65 seconds
Started Oct 14 11:00:49 PM UTC 24
Finished Oct 14 11:05:57 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730884308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1730884308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2411097048
Short name T664
Test name
Test status
Simulation time 493643848881 ps
CPU time 1795.13 seconds
Started Oct 14 11:00:49 PM UTC 24
Finished Oct 14 11:31:01 PM UTC 24
Peak memory 213032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411097048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.2411097048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.356985346
Short name T613
Test name
Test status
Simulation time 494569241750 ps
CPU time 1362.34 seconds
Started Oct 14 11:00:45 PM UTC 24
Finished Oct 14 11:23:40 PM UTC 24
Peak memory 212708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356985346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.356985346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2038567480
Short name T504
Test name
Test status
Simulation time 167816649704 ps
CPU time 305.86 seconds
Started Oct 14 11:00:47 PM UTC 24
Finished Oct 14 11:05:56 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038567480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.2038567480
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.2321658355
Short name T187
Test name
Test status
Simulation time 566570548909 ps
CPU time 470.23 seconds
Started Oct 14 11:00:52 PM UTC 24
Finished Oct 14 11:08:48 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321658355 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.2321658355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1670605600
Short name T660
Test name
Test status
Simulation time 598652586685 ps
CPU time 1703.7 seconds
Started Oct 14 11:00:55 PM UTC 24
Finished Oct 14 11:29:34 PM UTC 24
Peak memory 213052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670605600 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.1670605600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.666045548
Short name T485
Test name
Test status
Simulation time 43161622619 ps
CPU time 85.65 seconds
Started Oct 14 11:01:14 PM UTC 24
Finished Oct 14 11:02:42 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666045548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.666045548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2011017670
Short name T480
Test name
Test status
Simulation time 4691630701 ps
CPU time 18.48 seconds
Started Oct 14 11:01:09 PM UTC 24
Finished Oct 14 11:01:29 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011017670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2011017670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.296606022
Short name T476
Test name
Test status
Simulation time 5731013245 ps
CPU time 6.48 seconds
Started Oct 14 11:00:43 PM UTC 24
Finished Oct 14 11:00:51 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296606022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.296606022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.246564944
Short name T340
Test name
Test status
Simulation time 86645654467 ps
CPU time 24.73 seconds
Started Oct 14 11:01:18 PM UTC 24
Finished Oct 14 11:01:44 PM UTC 24
Peak memory 220456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=246564944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
24.adc_ctrl_stress_all_with_rand_reset.246564944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2244939895
Short name T490
Test name
Test status
Simulation time 305242444 ps
CPU time 2.07 seconds
Started Oct 14 11:03:28 PM UTC 24
Finished Oct 14 11:03:31 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244939895 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2244939895
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3459236180
Short name T291
Test name
Test status
Simulation time 177115272588 ps
CPU time 202.7 seconds
Started Oct 14 11:02:42 PM UTC 24
Finished Oct 14 11:06:08 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459236180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3459236180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.878804901
Short name T524
Test name
Test status
Simulation time 163661649104 ps
CPU time 532.91 seconds
Started Oct 14 11:01:47 PM UTC 24
Finished Oct 14 11:10:46 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878804901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.878804901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1390826245
Short name T501
Test name
Test status
Simulation time 324833740257 ps
CPU time 197.96 seconds
Started Oct 14 11:02:03 PM UTC 24
Finished Oct 14 11:05:24 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390826245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.1390826245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1523799629
Short name T576
Test name
Test status
Simulation time 328632652007 ps
CPU time 1040.91 seconds
Started Oct 14 11:01:44 PM UTC 24
Finished Oct 14 11:19:15 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523799629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1523799629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.2691547217
Short name T496
Test name
Test status
Simulation time 159722085736 ps
CPU time 184.85 seconds
Started Oct 14 11:01:45 PM UTC 24
Finished Oct 14 11:04:52 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691547217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.2691547217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.2228605214
Short name T312
Test name
Test status
Simulation time 165877429888 ps
CPU time 179.57 seconds
Started Oct 14 11:02:07 PM UTC 24
Finished Oct 14 11:05:10 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228605214 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.2228605214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.949308783
Short name T512
Test name
Test status
Simulation time 399702137105 ps
CPU time 322.77 seconds
Started Oct 14 11:02:29 PM UTC 24
Finished Oct 14 11:07:56 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949308783 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.949308783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.1252871253
Short name T557
Test name
Test status
Simulation time 114146976890 ps
CPU time 763 seconds
Started Oct 14 11:03:05 PM UTC 24
Finished Oct 14 11:15:55 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252871253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1252871253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.3131278303
Short name T492
Test name
Test status
Simulation time 34488816521 ps
CPU time 75.84 seconds
Started Oct 14 11:02:58 PM UTC 24
Finished Oct 14 11:04:15 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131278303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3131278303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1434744533
Short name T486
Test name
Test status
Simulation time 3688121976 ps
CPU time 4.43 seconds
Started Oct 14 11:02:51 PM UTC 24
Finished Oct 14 11:02:57 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434744533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1434744533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.1259552980
Short name T482
Test name
Test status
Simulation time 5911132478 ps
CPU time 3.4 seconds
Started Oct 14 11:01:39 PM UTC 24
Finished Oct 14 11:01:43 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259552980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1259552980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.664290374
Short name T285
Test name
Test status
Simulation time 517065862611 ps
CPU time 311.38 seconds
Started Oct 14 11:03:23 PM UTC 24
Finished Oct 14 11:08:39 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664290374 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.664290374
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3213434587
Short name T489
Test name
Test status
Simulation time 1976995697 ps
CPU time 11.83 seconds
Started Oct 14 11:03:14 PM UTC 24
Finished Oct 14 11:03:27 PM UTC 24
Peak memory 220380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3213434587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.adc_ctrl_stress_all_with_rand_reset.3213434587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.1475367038
Short name T497
Test name
Test status
Simulation time 430035899 ps
CPU time 2.61 seconds
Started Oct 14 11:04:57 PM UTC 24
Finished Oct 14 11:05:01 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475367038 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1475367038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.3842431415
Short name T359
Test name
Test status
Simulation time 338528069410 ps
CPU time 1184.66 seconds
Started Oct 14 11:04:25 PM UTC 24
Finished Oct 14 11:24:21 PM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842431415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3842431415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.2401063843
Short name T315
Test name
Test status
Simulation time 489307263106 ps
CPU time 449.23 seconds
Started Oct 14 11:04:01 PM UTC 24
Finished Oct 14 11:11:36 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401063843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2401063843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2463807055
Short name T503
Test name
Test status
Simulation time 334311049248 ps
CPU time 110.82 seconds
Started Oct 14 11:04:02 PM UTC 24
Finished Oct 14 11:05:55 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463807055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.2463807055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.1132890748
Short name T542
Test name
Test status
Simulation time 168842809891 ps
CPU time 581.4 seconds
Started Oct 14 11:03:36 PM UTC 24
Finished Oct 14 11:13:24 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132890748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1132890748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.812274168
Short name T581
Test name
Test status
Simulation time 327748262986 ps
CPU time 973.2 seconds
Started Oct 14 11:03:46 PM UTC 24
Finished Oct 14 11:20:09 PM UTC 24
Peak memory 212848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812274168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.812274168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.1047899694
Short name T628
Test name
Test status
Simulation time 599510598331 ps
CPU time 1257.42 seconds
Started Oct 14 11:04:07 PM UTC 24
Finished Oct 14 11:25:16 PM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047899694 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.1047899694
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1134460743
Short name T550
Test name
Test status
Simulation time 209048665452 ps
CPU time 624.64 seconds
Started Oct 14 11:04:13 PM UTC 24
Finished Oct 14 11:14:45 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134460743 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.1134460743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.1902207875
Short name T548
Test name
Test status
Simulation time 114044461020 ps
CPU time 556.33 seconds
Started Oct 14 11:04:50 PM UTC 24
Finished Oct 14 11:14:12 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902207875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1902207875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.4101485999
Short name T502
Test name
Test status
Simulation time 31118469623 ps
CPU time 65.08 seconds
Started Oct 14 11:04:37 PM UTC 24
Finished Oct 14 11:05:43 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101485999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4101485999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1600815849
Short name T493
Test name
Test status
Simulation time 3622539209 ps
CPU time 4.41 seconds
Started Oct 14 11:04:31 PM UTC 24
Finished Oct 14 11:04:36 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600815849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1600815849
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.3828528027
Short name T491
Test name
Test status
Simulation time 5878423429 ps
CPU time 2.36 seconds
Started Oct 14 11:03:32 PM UTC 24
Finished Oct 14 11:03:36 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828528027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3828528027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.181464264
Short name T250
Test name
Test status
Simulation time 497633542358 ps
CPU time 302.44 seconds
Started Oct 14 11:04:53 PM UTC 24
Finished Oct 14 11:09:59 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181464264 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.181464264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1620726254
Short name T499
Test name
Test status
Simulation time 98798945182 ps
CPU time 20.9 seconds
Started Oct 14 11:04:52 PM UTC 24
Finished Oct 14 11:05:14 PM UTC 24
Peak memory 220456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1620726254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.adc_ctrl_stress_all_with_rand_reset.1620726254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.1003726921
Short name T507
Test name
Test status
Simulation time 294939426 ps
CPU time 1.98 seconds
Started Oct 14 11:06:11 PM UTC 24
Finished Oct 14 11:06:14 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003726921 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1003726921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.663853779
Short name T343
Test name
Test status
Simulation time 381241024657 ps
CPU time 838.56 seconds
Started Oct 14 11:05:44 PM UTC 24
Finished Oct 14 11:19:50 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663853779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.663853779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.3606835979
Short name T211
Test name
Test status
Simulation time 485519240825 ps
CPU time 936.35 seconds
Started Oct 14 11:05:12 PM UTC 24
Finished Oct 14 11:20:58 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606835979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3606835979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.853931074
Short name T530
Test name
Test status
Simulation time 492851116334 ps
CPU time 408.1 seconds
Started Oct 14 11:05:14 PM UTC 24
Finished Oct 14 11:12:07 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853931074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.853931074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.470022165
Short name T177
Test name
Test status
Simulation time 488963809133 ps
CPU time 215.28 seconds
Started Oct 14 11:05:08 PM UTC 24
Finished Oct 14 11:08:47 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470022165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.470022165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.432218923
Short name T526
Test name
Test status
Simulation time 488136443149 ps
CPU time 331.86 seconds
Started Oct 14 11:05:10 PM UTC 24
Finished Oct 14 11:10:46 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432218923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.432218923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3801068637
Short name T549
Test name
Test status
Simulation time 203804442297 ps
CPU time 545.88 seconds
Started Oct 14 11:05:24 PM UTC 24
Finished Oct 14 11:14:35 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801068637 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.3801068637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3593925769
Short name T367
Test name
Test status
Simulation time 114883800566 ps
CPU time 662.48 seconds
Started Oct 14 11:05:57 PM UTC 24
Finished Oct 14 11:17:06 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593925769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3593925769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.2165243257
Short name T513
Test name
Test status
Simulation time 37150433817 ps
CPU time 124.54 seconds
Started Oct 14 11:05:56 PM UTC 24
Finished Oct 14 11:08:03 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165243257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2165243257
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2742579935
Short name T506
Test name
Test status
Simulation time 5419747185 ps
CPU time 23.71 seconds
Started Oct 14 11:05:48 PM UTC 24
Finished Oct 14 11:06:13 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742579935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2742579935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.1777296986
Short name T498
Test name
Test status
Simulation time 5951200055 ps
CPU time 7.64 seconds
Started Oct 14 11:05:02 PM UTC 24
Finished Oct 14 11:05:11 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777296986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1777296986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1165692260
Short name T505
Test name
Test status
Simulation time 3949199876 ps
CPU time 11.35 seconds
Started Oct 14 11:05:58 PM UTC 24
Finished Oct 14 11:06:11 PM UTC 24
Peak memory 221048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1165692260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.adc_ctrl_stress_all_with_rand_reset.1165692260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.3348247875
Short name T518
Test name
Test status
Simulation time 283881646 ps
CPU time 2.03 seconds
Started Oct 14 11:08:45 PM UTC 24
Finished Oct 14 11:08:48 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348247875 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3348247875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2496018768
Short name T534
Test name
Test status
Simulation time 174330287929 ps
CPU time 289.69 seconds
Started Oct 14 11:07:47 PM UTC 24
Finished Oct 14 11:12:40 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496018768 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.2496018768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.3627106154
Short name T306
Test name
Test status
Simulation time 516294844292 ps
CPU time 328.56 seconds
Started Oct 14 11:07:57 PM UTC 24
Finished Oct 14 11:13:30 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627106154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3627106154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.3690356370
Short name T566
Test name
Test status
Simulation time 323579625318 ps
CPU time 641.73 seconds
Started Oct 14 11:06:29 PM UTC 24
Finished Oct 14 11:17:18 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690356370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3690356370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3675658367
Short name T539
Test name
Test status
Simulation time 490711395285 ps
CPU time 379.46 seconds
Started Oct 14 11:06:51 PM UTC 24
Finished Oct 14 11:13:15 PM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675658367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.3675658367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.3897341858
Short name T517
Test name
Test status
Simulation time 166308237911 ps
CPU time 146.03 seconds
Started Oct 14 11:06:15 PM UTC 24
Finished Oct 14 11:08:44 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897341858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3897341858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.1531798632
Short name T525
Test name
Test status
Simulation time 331391851323 ps
CPU time 262.16 seconds
Started Oct 14 11:06:20 PM UTC 24
Finished Oct 14 11:10:46 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531798632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.1531798632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4151038466
Short name T179
Test name
Test status
Simulation time 542215896756 ps
CPU time 333.85 seconds
Started Oct 14 11:07:24 PM UTC 24
Finished Oct 14 11:13:02 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151038466 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4151038466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1103771405
Short name T541
Test name
Test status
Simulation time 405146343919 ps
CPU time 341.21 seconds
Started Oct 14 11:07:36 PM UTC 24
Finished Oct 14 11:13:21 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103771405 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.1103771405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.1194646928
Short name T584
Test name
Test status
Simulation time 116403632626 ps
CPU time 709.59 seconds
Started Oct 14 11:08:22 PM UTC 24
Finished Oct 14 11:20:19 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194646928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1194646928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.665304169
Short name T515
Test name
Test status
Simulation time 24157275635 ps
CPU time 12.69 seconds
Started Oct 14 11:08:07 PM UTC 24
Finished Oct 14 11:08:21 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665304169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.665304169
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.1739123410
Short name T514
Test name
Test status
Simulation time 4238305659 ps
CPU time 2.52 seconds
Started Oct 14 11:08:03 PM UTC 24
Finished Oct 14 11:08:07 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739123410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1739123410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2394667756
Short name T508
Test name
Test status
Simulation time 5716565340 ps
CPU time 12.88 seconds
Started Oct 14 11:06:13 PM UTC 24
Finished Oct 14 11:06:27 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394667756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2394667756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.2502662149
Short name T583
Test name
Test status
Simulation time 214797250697 ps
CPU time 691.63 seconds
Started Oct 14 11:08:40 PM UTC 24
Finished Oct 14 11:20:19 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502662149 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.2502662149
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2029702858
Short name T280
Test name
Test status
Simulation time 56041626355 ps
CPU time 14.08 seconds
Started Oct 14 11:08:31 PM UTC 24
Finished Oct 14 11:08:47 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2029702858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.adc_ctrl_stress_all_with_rand_reset.2029702858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.4051379152
Short name T527
Test name
Test status
Simulation time 438695268 ps
CPU time 1.1 seconds
Started Oct 14 11:10:47 PM UTC 24
Finished Oct 14 11:10:49 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051379152 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4051379152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.4050185310
Short name T344
Test name
Test status
Simulation time 475187685541 ps
CPU time 1071.01 seconds
Started Oct 14 11:09:55 PM UTC 24
Finished Oct 14 11:27:57 PM UTC 24
Peak memory 212912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050185310 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.4050185310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.3400677488
Short name T578
Test name
Test status
Simulation time 336238878282 ps
CPU time 639.07 seconds
Started Oct 14 11:08:49 PM UTC 24
Finished Oct 14 11:19:35 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400677488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3400677488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2840323673
Short name T559
Test name
Test status
Simulation time 325439093462 ps
CPU time 446.82 seconds
Started Oct 14 11:08:52 PM UTC 24
Finished Oct 14 11:16:24 PM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840323673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.2840323673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.2776911578
Short name T188
Test name
Test status
Simulation time 323952010421 ps
CPU time 276.61 seconds
Started Oct 14 11:08:48 PM UTC 24
Finished Oct 14 11:13:28 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776911578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2776911578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1535979204
Short name T528
Test name
Test status
Simulation time 494962505932 ps
CPU time 137.59 seconds
Started Oct 14 11:08:49 PM UTC 24
Finished Oct 14 11:11:09 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535979204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.1535979204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.3119867623
Short name T695
Test name
Test status
Simulation time 590121092324 ps
CPU time 1500.45 seconds
Started Oct 14 11:09:00 PM UTC 24
Finished Oct 14 11:34:14 PM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119867623 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.3119867623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3802649346
Short name T595
Test name
Test status
Simulation time 412752504026 ps
CPU time 674.49 seconds
Started Oct 14 11:09:46 PM UTC 24
Finished Oct 14 11:21:09 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802649346 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.3802649346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.3351514998
Short name T229
Test name
Test status
Simulation time 109994854665 ps
CPU time 540.17 seconds
Started Oct 14 11:10:45 PM UTC 24
Finished Oct 14 11:19:50 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351514998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3351514998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.3619094683
Short name T537
Test name
Test status
Simulation time 35676792169 ps
CPU time 129.16 seconds
Started Oct 14 11:10:45 PM UTC 24
Finished Oct 14 11:12:56 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619094683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3619094683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.996896312
Short name T522
Test name
Test status
Simulation time 5174094782 ps
CPU time 20.44 seconds
Started Oct 14 11:10:22 PM UTC 24
Finished Oct 14 11:10:44 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996896312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.996896312
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.137186937
Short name T519
Test name
Test status
Simulation time 5903188162 ps
CPU time 2.31 seconds
Started Oct 14 11:08:48 PM UTC 24
Finished Oct 14 11:08:51 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137186937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.137186937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3265521627
Short name T357
Test name
Test status
Simulation time 321279439847 ps
CPU time 571.8 seconds
Started Oct 14 11:10:47 PM UTC 24
Finished Oct 14 11:20:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265521627 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.3265521627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.150631789
Short name T34
Test name
Test status
Simulation time 27380110994 ps
CPU time 34.19 seconds
Started Oct 14 11:10:47 PM UTC 24
Finished Oct 14 11:11:22 PM UTC 24
Peak memory 227052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=150631789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
29.adc_ctrl_stress_all_with_rand_reset.150631789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2985620678
Short name T217
Test name
Test status
Simulation time 391784668 ps
CPU time 1.05 seconds
Started Oct 14 10:27:27 PM UTC 24
Finished Oct 14 10:27:29 PM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985620678 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2985620678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.4250478227
Short name T14
Test name
Test status
Simulation time 161891443820 ps
CPU time 13.81 seconds
Started Oct 14 10:27:11 PM UTC 24
Finished Oct 14 10:27:26 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250478227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.4250478227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2285524090
Short name T121
Test name
Test status
Simulation time 498740606476 ps
CPU time 315.16 seconds
Started Oct 14 10:27:00 PM UTC 24
Finished Oct 14 10:32:19 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285524090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2285524090
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.962248336
Short name T165
Test name
Test status
Simulation time 492991146912 ps
CPU time 257.61 seconds
Started Oct 14 10:27:03 PM UTC 24
Finished Oct 14 10:31:24 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962248336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.962248336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.1993566983
Short name T17
Test name
Test status
Simulation time 164487102319 ps
CPU time 103.02 seconds
Started Oct 14 10:26:54 PM UTC 24
Finished Oct 14 10:28:39 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993566983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1993566983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.533423164
Short name T38
Test name
Test status
Simulation time 162096501552 ps
CPU time 131.74 seconds
Started Oct 14 10:26:58 PM UTC 24
Finished Oct 14 10:29:12 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533423164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.533423164
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1914062366
Short name T429
Test name
Test status
Simulation time 401411862701 ps
CPU time 1371.12 seconds
Started Oct 14 10:27:04 PM UTC 24
Finished Oct 14 10:50:09 PM UTC 24
Peak memory 212904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914062366 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.1914062366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.2983804424
Short name T154
Test name
Test status
Simulation time 33909516188 ps
CPU time 68.63 seconds
Started Oct 14 10:27:18 PM UTC 24
Finished Oct 14 10:28:28 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983804424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2983804424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.834345754
Short name T41
Test name
Test status
Simulation time 5485124666 ps
CPU time 5.88 seconds
Started Oct 14 10:27:15 PM UTC 24
Finished Oct 14 10:27:21 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834345754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.834345754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.868011233
Short name T74
Test name
Test status
Simulation time 8179449953 ps
CPU time 24.99 seconds
Started Oct 14 10:27:23 PM UTC 24
Finished Oct 14 10:27:49 PM UTC 24
Peak memory 242368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868011233 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.868011233
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.371120903
Short name T26
Test name
Test status
Simulation time 5793105008 ps
CPU time 2.32 seconds
Started Oct 14 10:26:54 PM UTC 24
Finished Oct 14 10:26:57 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371120903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.371120903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2134534687
Short name T48
Test name
Test status
Simulation time 89139186039 ps
CPU time 569.4 seconds
Started Oct 14 10:27:22 PM UTC 24
Finished Oct 14 10:36:57 PM UTC 24
Peak memory 220672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134534687 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.2134534687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.3628746615
Short name T533
Test name
Test status
Simulation time 321313031 ps
CPU time 1.12 seconds
Started Oct 14 11:12:38 PM UTC 24
Finished Oct 14 11:12:40 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628746615 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3628746615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.2951175677
Short name T330
Test name
Test status
Simulation time 489989054754 ps
CPU time 1213.52 seconds
Started Oct 14 11:11:38 PM UTC 24
Finished Oct 14 11:32:03 PM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951175677 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.2951175677
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.3992327932
Short name T193
Test name
Test status
Simulation time 499747285394 ps
CPU time 1357.62 seconds
Started Oct 14 11:11:41 PM UTC 24
Finished Oct 14 11:34:32 PM UTC 24
Peak memory 212860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992327932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3992327932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1630374306
Short name T181
Test name
Test status
Simulation time 493715041127 ps
CPU time 248.42 seconds
Started Oct 14 11:11:10 PM UTC 24
Finished Oct 14 11:15:22 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630374306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1630374306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3286034698
Short name T625
Test name
Test status
Simulation time 317399833258 ps
CPU time 807.85 seconds
Started Oct 14 11:11:23 PM UTC 24
Finished Oct 14 11:24:59 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286034698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.3286034698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.2690144234
Short name T180
Test name
Test status
Simulation time 333701344216 ps
CPU time 121.13 seconds
Started Oct 14 11:10:59 PM UTC 24
Finished Oct 14 11:13:03 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690144234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2690144234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.2217068828
Short name T532
Test name
Test status
Simulation time 498279043857 ps
CPU time 85.07 seconds
Started Oct 14 11:11:10 PM UTC 24
Finished Oct 14 11:12:37 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217068828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.2217068828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3436355409
Short name T663
Test name
Test status
Simulation time 555118942797 ps
CPU time 1125.67 seconds
Started Oct 14 11:11:26 PM UTC 24
Finished Oct 14 11:30:23 PM UTC 24
Peak memory 212928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436355409 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3436355409
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2365160811
Short name T577
Test name
Test status
Simulation time 602949411292 ps
CPU time 453.99 seconds
Started Oct 14 11:11:36 PM UTC 24
Finished Oct 14 11:19:15 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365160811 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.2365160811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.1226763403
Short name T588
Test name
Test status
Simulation time 78966047016 ps
CPU time 512.89 seconds
Started Oct 14 11:12:09 PM UTC 24
Finished Oct 14 11:20:47 PM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226763403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1226763403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.143467375
Short name T546
Test name
Test status
Simulation time 30893479206 ps
CPU time 85.96 seconds
Started Oct 14 11:12:08 PM UTC 24
Finished Oct 14 11:13:35 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143467375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.143467375
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.1140995652
Short name T531
Test name
Test status
Simulation time 3882398892 ps
CPU time 3.75 seconds
Started Oct 14 11:12:03 PM UTC 24
Finished Oct 14 11:12:07 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140995652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1140995652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.1813411350
Short name T520
Test name
Test status
Simulation time 5746321802 ps
CPU time 7.23 seconds
Started Oct 14 11:10:50 PM UTC 24
Finished Oct 14 11:10:58 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813411350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1813411350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.794818842
Short name T259
Test name
Test status
Simulation time 308077131867 ps
CPU time 1685.44 seconds
Started Oct 14 11:12:36 PM UTC 24
Finished Oct 14 11:40:59 PM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794818842 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.794818842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.709903078
Short name T538
Test name
Test status
Simulation time 2170087632 ps
CPU time 19.35 seconds
Started Oct 14 11:12:35 PM UTC 24
Finished Oct 14 11:12:56 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=709903078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
30.adc_ctrl_stress_all_with_rand_reset.709903078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.220181603
Short name T545
Test name
Test status
Simulation time 319028554 ps
CPU time 2.17 seconds
Started Oct 14 11:13:29 PM UTC 24
Finished Oct 14 11:13:33 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220181603 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.220181603
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1409725775
Short name T553
Test name
Test status
Simulation time 163358620857 ps
CPU time 130.47 seconds
Started Oct 14 11:13:03 PM UTC 24
Finished Oct 14 11:15:15 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409725775 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.1409725775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2544548088
Short name T646
Test name
Test status
Simulation time 344729086817 ps
CPU time 867.91 seconds
Started Oct 14 11:13:04 PM UTC 24
Finished Oct 14 11:27:41 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544548088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2544548088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.462359136
Short name T552
Test name
Test status
Simulation time 162616136679 ps
CPU time 141.32 seconds
Started Oct 14 11:12:51 PM UTC 24
Finished Oct 14 11:15:15 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462359136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.462359136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1481448233
Short name T575
Test name
Test status
Simulation time 163333050109 ps
CPU time 351.01 seconds
Started Oct 14 11:12:56 PM UTC 24
Finished Oct 14 11:18:51 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481448233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.1481448233
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.1121908051
Short name T543
Test name
Test status
Simulation time 164965607384 ps
CPU time 44.18 seconds
Started Oct 14 11:12:41 PM UTC 24
Finished Oct 14 11:13:27 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121908051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1121908051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2748731806
Short name T676
Test name
Test status
Simulation time 494616532067 ps
CPU time 1177.14 seconds
Started Oct 14 11:12:46 PM UTC 24
Finished Oct 14 11:32:34 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748731806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2748731806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2057728193
Short name T555
Test name
Test status
Simulation time 218510035852 ps
CPU time 161.03 seconds
Started Oct 14 11:12:56 PM UTC 24
Finished Oct 14 11:15:40 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057728193 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.2057728193
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2146228167
Short name T629
Test name
Test status
Simulation time 206044508851 ps
CPU time 730.53 seconds
Started Oct 14 11:12:58 PM UTC 24
Finished Oct 14 11:25:16 PM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146228167 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.2146228167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.2844627942
Short name T604
Test name
Test status
Simulation time 78095663721 ps
CPU time 562.96 seconds
Started Oct 14 11:13:22 PM UTC 24
Finished Oct 14 11:22:51 PM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844627942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2844627942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3842087163
Short name T544
Test name
Test status
Simulation time 22614579166 ps
CPU time 9.2 seconds
Started Oct 14 11:13:20 PM UTC 24
Finished Oct 14 11:13:30 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842087163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3842087163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.2848858021
Short name T540
Test name
Test status
Simulation time 5108045861 ps
CPU time 2.13 seconds
Started Oct 14 11:13:16 PM UTC 24
Finished Oct 14 11:13:19 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848858021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2848858021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.3039651841
Short name T536
Test name
Test status
Simulation time 5976856082 ps
CPU time 12.88 seconds
Started Oct 14 11:12:41 PM UTC 24
Finished Oct 14 11:12:55 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039651841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3039651841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.4143757834
Short name T607
Test name
Test status
Simulation time 119441243538 ps
CPU time 562.42 seconds
Started Oct 14 11:13:27 PM UTC 24
Finished Oct 14 11:22:55 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143757834 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.4143757834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2220073934
Short name T356
Test name
Test status
Simulation time 23901999735 ps
CPU time 21.58 seconds
Started Oct 14 11:13:25 PM UTC 24
Finished Oct 14 11:13:48 PM UTC 24
Peak memory 220656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2220073934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.adc_ctrl_stress_all_with_rand_reset.2220073934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.324233782
Short name T554
Test name
Test status
Simulation time 410028518 ps
CPU time 2.61 seconds
Started Oct 14 11:15:29 PM UTC 24
Finished Oct 14 11:15:33 PM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324233782 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.324233782
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2437795915
Short name T570
Test name
Test status
Simulation time 353610534717 ps
CPU time 240.56 seconds
Started Oct 14 11:14:13 PM UTC 24
Finished Oct 14 11:18:16 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437795915 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.2437795915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.1653127206
Short name T619
Test name
Test status
Simulation time 164785177406 ps
CPU time 607.63 seconds
Started Oct 14 11:14:36 PM UTC 24
Finished Oct 14 11:24:50 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653127206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1653127206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3970717804
Short name T361
Test name
Test status
Simulation time 324611968790 ps
CPU time 133.74 seconds
Started Oct 14 11:13:36 PM UTC 24
Finished Oct 14 11:15:52 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970717804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3970717804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3843397764
Short name T591
Test name
Test status
Simulation time 173433960106 ps
CPU time 427.2 seconds
Started Oct 14 11:13:44 PM UTC 24
Finished Oct 14 11:20:56 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843397764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.3843397764
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2087861287
Short name T313
Test name
Test status
Simulation time 161007538771 ps
CPU time 144.99 seconds
Started Oct 14 11:13:31 PM UTC 24
Finished Oct 14 11:15:59 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087861287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2087861287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.1065870944
Short name T700
Test name
Test status
Simulation time 490664553809 ps
CPU time 1277.52 seconds
Started Oct 14 11:13:33 PM UTC 24
Finished Oct 14 11:35:04 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065870944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.1065870944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1114447794
Short name T346
Test name
Test status
Simulation time 205530633989 ps
CPU time 199.22 seconds
Started Oct 14 11:13:48 PM UTC 24
Finished Oct 14 11:17:11 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114447794 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.1114447794
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.152367703
Short name T561
Test name
Test status
Simulation time 201166561893 ps
CPU time 161.21 seconds
Started Oct 14 11:14:00 PM UTC 24
Finished Oct 14 11:16:43 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152367703 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.152367703
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.534240908
Short name T602
Test name
Test status
Simulation time 72598008845 ps
CPU time 432.39 seconds
Started Oct 14 11:15:16 PM UTC 24
Finished Oct 14 11:22:33 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534240908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.534240908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.968104024
Short name T558
Test name
Test status
Simulation time 28221001515 ps
CPU time 67.02 seconds
Started Oct 14 11:15:00 PM UTC 24
Finished Oct 14 11:16:09 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968104024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.968104024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.1567041449
Short name T551
Test name
Test status
Simulation time 4365679146 ps
CPU time 11.43 seconds
Started Oct 14 11:14:46 PM UTC 24
Finished Oct 14 11:14:58 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567041449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1567041449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.3975676080
Short name T547
Test name
Test status
Simulation time 5717466381 ps
CPU time 26.23 seconds
Started Oct 14 11:13:31 PM UTC 24
Finished Oct 14 11:13:59 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975676080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3975676080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2623960821
Short name T321
Test name
Test status
Simulation time 8858819756 ps
CPU time 32.67 seconds
Started Oct 14 11:15:16 PM UTC 24
Finished Oct 14 11:15:50 PM UTC 24
Peak memory 220800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2623960821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.adc_ctrl_stress_all_with_rand_reset.2623960821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.108765880
Short name T563
Test name
Test status
Simulation time 450937813 ps
CPU time 2.71 seconds
Started Oct 14 11:17:03 PM UTC 24
Finished Oct 14 11:17:06 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108765880 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.108765880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3857746350
Short name T670
Test name
Test status
Simulation time 336211261130 ps
CPU time 913.45 seconds
Started Oct 14 11:16:09 PM UTC 24
Finished Oct 14 11:31:31 PM UTC 24
Peak memory 210112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857746350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3857746350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.4139005482
Short name T683
Test name
Test status
Simulation time 327571621294 ps
CPU time 1029.21 seconds
Started Oct 14 11:15:46 PM UTC 24
Finished Oct 14 11:33:05 PM UTC 24
Peak memory 212808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139005482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4139005482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.381853105
Short name T694
Test name
Test status
Simulation time 328290318566 ps
CPU time 1091.35 seconds
Started Oct 14 11:15:51 PM UTC 24
Finished Oct 14 11:34:14 PM UTC 24
Peak memory 212992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381853105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.381853105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1036630838
Short name T322
Test name
Test status
Simulation time 505272482413 ps
CPU time 388.9 seconds
Started Oct 14 11:15:41 PM UTC 24
Finished Oct 14 11:22:14 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036630838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1036630838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.613386437
Short name T580
Test name
Test status
Simulation time 326389879788 ps
CPU time 263.14 seconds
Started Oct 14 11:15:42 PM UTC 24
Finished Oct 14 11:20:08 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613386437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.613386437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.2788415801
Short name T684
Test name
Test status
Simulation time 364866600536 ps
CPU time 1039.03 seconds
Started Oct 14 11:15:53 PM UTC 24
Finished Oct 14 11:33:22 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788415801 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.2788415801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1791691120
Short name T716
Test name
Test status
Simulation time 392743995124 ps
CPU time 1240.33 seconds
Started Oct 14 11:15:56 PM UTC 24
Finished Oct 14 11:36:48 PM UTC 24
Peak memory 212708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791691120 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1791691120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.983433414
Short name T600
Test name
Test status
Simulation time 83211044627 ps
CPU time 320.14 seconds
Started Oct 14 11:16:42 PM UTC 24
Finished Oct 14 11:22:06 PM UTC 24
Peak memory 210612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983433414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.983433414
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3845266736
Short name T565
Test name
Test status
Simulation time 29749813387 ps
CPU time 35.69 seconds
Started Oct 14 11:16:40 PM UTC 24
Finished Oct 14 11:17:17 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845266736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3845266736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.2929122486
Short name T560
Test name
Test status
Simulation time 3691693305 ps
CPU time 15.12 seconds
Started Oct 14 11:16:25 PM UTC 24
Finished Oct 14 11:16:42 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929122486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2929122486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.948756507
Short name T556
Test name
Test status
Simulation time 6091394094 ps
CPU time 6.46 seconds
Started Oct 14 11:15:33 PM UTC 24
Finished Oct 14 11:15:41 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948756507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.948756507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3578426446
Short name T776
Test name
Test status
Simulation time 533008936071 ps
CPU time 1946.75 seconds
Started Oct 14 11:16:58 PM UTC 24
Finished Oct 14 11:49:43 PM UTC 24
Peak memory 223364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578426446 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.3578426446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1973129570
Short name T562
Test name
Test status
Simulation time 10106218735 ps
CPU time 11.13 seconds
Started Oct 14 11:16:44 PM UTC 24
Finished Oct 14 11:16:57 PM UTC 24
Peak memory 220376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1973129570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.adc_ctrl_stress_all_with_rand_reset.1973129570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.2980776524
Short name T572
Test name
Test status
Simulation time 309403147 ps
CPU time 1.2 seconds
Started Oct 14 11:18:33 PM UTC 24
Finished Oct 14 11:18:35 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980776524 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2980776524
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.174542937
Short name T318
Test name
Test status
Simulation time 163838176536 ps
CPU time 143.26 seconds
Started Oct 14 11:17:18 PM UTC 24
Finished Oct 14 11:19:44 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174542937 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.174542937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.2036393218
Short name T692
Test name
Test status
Simulation time 516868636794 ps
CPU time 946.15 seconds
Started Oct 14 11:18:02 PM UTC 24
Finished Oct 14 11:33:58 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036393218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2036393218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3505009239
Short name T589
Test name
Test status
Simulation time 326719689065 ps
CPU time 210.86 seconds
Started Oct 14 11:17:16 PM UTC 24
Finished Oct 14 11:20:50 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505009239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3505009239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.1606452191
Short name T671
Test name
Test status
Simulation time 325192572759 ps
CPU time 867.8 seconds
Started Oct 14 11:17:07 PM UTC 24
Finished Oct 14 11:31:44 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606452191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1606452191
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.1978683955
Short name T610
Test name
Test status
Simulation time 162566198444 ps
CPU time 370.61 seconds
Started Oct 14 11:17:11 PM UTC 24
Finished Oct 14 11:23:26 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978683955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.1978683955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3770553958
Short name T190
Test name
Test status
Simulation time 671451741103 ps
CPU time 298.3 seconds
Started Oct 14 11:17:18 PM UTC 24
Finished Oct 14 11:22:21 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770553958 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.3770553958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.954203339
Short name T704
Test name
Test status
Simulation time 403928484183 ps
CPU time 1065.57 seconds
Started Oct 14 11:17:18 PM UTC 24
Finished Oct 14 11:35:14 PM UTC 24
Peak memory 212888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954203339 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.954203339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3169611633
Short name T618
Test name
Test status
Simulation time 72208560162 ps
CPU time 369.09 seconds
Started Oct 14 11:18:17 PM UTC 24
Finished Oct 14 11:24:30 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169611633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3169611633
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.1322561344
Short name T573
Test name
Test status
Simulation time 25751489358 ps
CPU time 29.85 seconds
Started Oct 14 11:18:09 PM UTC 24
Finished Oct 14 11:18:40 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322561344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1322561344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.3568481437
Short name T568
Test name
Test status
Simulation time 4230998317 ps
CPU time 2.85 seconds
Started Oct 14 11:18:03 PM UTC 24
Finished Oct 14 11:18:07 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568481437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3568481437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.1158982870
Short name T564
Test name
Test status
Simulation time 5879251928 ps
CPU time 2.19 seconds
Started Oct 14 11:17:07 PM UTC 24
Finished Oct 14 11:17:10 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158982870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1158982870
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3011490723
Short name T696
Test name
Test status
Simulation time 353594294588 ps
CPU time 947.51 seconds
Started Oct 14 11:18:27 PM UTC 24
Finished Oct 14 11:34:24 PM UTC 24
Peak memory 210076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011490723 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3011490723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.211425937
Short name T571
Test name
Test status
Simulation time 1503690039 ps
CPU time 7.09 seconds
Started Oct 14 11:18:18 PM UTC 24
Finished Oct 14 11:18:26 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=211425937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.adc_ctrl_stress_all_with_rand_reset.211425937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.3289215222
Short name T582
Test name
Test status
Simulation time 490354059 ps
CPU time 1.5 seconds
Started Oct 14 11:20:09 PM UTC 24
Finished Oct 14 11:20:11 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289215222 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3289215222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.1140230630
Short name T615
Test name
Test status
Simulation time 332188084112 ps
CPU time 281.51 seconds
Started Oct 14 11:19:35 PM UTC 24
Finished Oct 14 11:24:21 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140230630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.1140230630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.2027768491
Short name T609
Test name
Test status
Simulation time 158732629620 ps
CPU time 213.01 seconds
Started Oct 14 11:19:42 PM UTC 24
Finished Oct 14 11:23:17 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027768491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2027768491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.100823039
Short name T587
Test name
Test status
Simulation time 166313356238 ps
CPU time 101.9 seconds
Started Oct 14 11:18:52 PM UTC 24
Finished Oct 14 11:20:36 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100823039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.100823039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2234544170
Short name T633
Test name
Test status
Simulation time 164966231500 ps
CPU time 403.63 seconds
Started Oct 14 11:19:16 PM UTC 24
Finished Oct 14 11:26:05 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234544170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.2234544170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2049352424
Short name T597
Test name
Test status
Simulation time 326116781837 ps
CPU time 145.61 seconds
Started Oct 14 11:18:41 PM UTC 24
Finished Oct 14 11:21:09 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049352424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2049352424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.3936660821
Short name T622
Test name
Test status
Simulation time 164183851623 ps
CPU time 365.84 seconds
Started Oct 14 11:18:47 PM UTC 24
Finished Oct 14 11:24:57 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936660821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.3936660821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2696276412
Short name T720
Test name
Test status
Simulation time 654241224369 ps
CPU time 1062.08 seconds
Started Oct 14 11:19:16 PM UTC 24
Finished Oct 14 11:37:09 PM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696276412 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2696276412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2027027246
Short name T637
Test name
Test status
Simulation time 618407249499 ps
CPU time 436.43 seconds
Started Oct 14 11:19:34 PM UTC 24
Finished Oct 14 11:26:56 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027027246 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.2027027246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.422526353
Short name T689
Test name
Test status
Simulation time 118389232201 ps
CPU time 831.79 seconds
Started Oct 14 11:19:51 PM UTC 24
Finished Oct 14 11:33:51 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422526353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.422526353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1927126525
Short name T590
Test name
Test status
Simulation time 27453112411 ps
CPU time 60.07 seconds
Started Oct 14 11:19:49 PM UTC 24
Finished Oct 14 11:20:50 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927126525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1927126525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.2460360367
Short name T579
Test name
Test status
Simulation time 5097913295 ps
CPU time 2.36 seconds
Started Oct 14 11:19:45 PM UTC 24
Finished Oct 14 11:19:48 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460360367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2460360367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.891033559
Short name T574
Test name
Test status
Simulation time 5633320151 ps
CPU time 9.07 seconds
Started Oct 14 11:18:36 PM UTC 24
Finished Oct 14 11:18:46 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891033559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.891033559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2884828031
Short name T795
Test name
Test status
Simulation time 2537496390149 ps
CPU time 4690.86 seconds
Started Oct 14 11:19:59 PM UTC 24
Finished Oct 15 12:38:54 AM UTC 24
Peak memory 223504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884828031 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.2884828031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3528067976
Short name T349
Test name
Test status
Simulation time 8640458224 ps
CPU time 4.78 seconds
Started Oct 14 11:19:52 PM UTC 24
Finished Oct 14 11:19:58 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3528067976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.adc_ctrl_stress_all_with_rand_reset.3528067976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3034659135
Short name T594
Test name
Test status
Simulation time 333272596 ps
CPU time 1.14 seconds
Started Oct 14 11:21:05 PM UTC 24
Finished Oct 14 11:21:07 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034659135 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3034659135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.1228711589
Short name T623
Test name
Test status
Simulation time 187555953499 ps
CPU time 246.65 seconds
Started Oct 14 11:20:48 PM UTC 24
Finished Oct 14 11:24:57 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228711589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1228711589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3750919130
Short name T751
Test name
Test status
Simulation time 488481308248 ps
CPU time 1226.81 seconds
Started Oct 14 11:20:20 PM UTC 24
Finished Oct 14 11:40:59 PM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750919130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.3750919130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.3431741926
Short name T348
Test name
Test status
Simulation time 325740543105 ps
CPU time 902.14 seconds
Started Oct 14 11:20:12 PM UTC 24
Finished Oct 14 11:35:24 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431741926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3431741926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.69472475
Short name T606
Test name
Test status
Simulation time 162307861623 ps
CPU time 152.3 seconds
Started Oct 14 11:20:20 PM UTC 24
Finished Oct 14 11:22:55 PM UTC 24
Peak memory 210012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69472475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.69472475
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.2470558790
Short name T631
Test name
Test status
Simulation time 167200973291 ps
CPU time 304.45 seconds
Started Oct 14 11:20:25 PM UTC 24
Finished Oct 14 11:25:33 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470558790 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.2470558790
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.96573955
Short name T611
Test name
Test status
Simulation time 205828557249 ps
CPU time 179.46 seconds
Started Oct 14 11:20:33 PM UTC 24
Finished Oct 14 11:23:35 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96573955 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.96573955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.1183748353
Short name T653
Test name
Test status
Simulation time 110957530237 ps
CPU time 462.47 seconds
Started Oct 14 11:20:54 PM UTC 24
Finished Oct 14 11:28:41 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183748353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1183748353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.1577978076
Short name T598
Test name
Test status
Simulation time 26633646283 ps
CPU time 39.37 seconds
Started Oct 14 11:20:51 PM UTC 24
Finished Oct 14 11:21:32 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577978076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1577978076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.3313793212
Short name T593
Test name
Test status
Simulation time 4035411971 ps
CPU time 15.34 seconds
Started Oct 14 11:20:51 PM UTC 24
Finished Oct 14 11:21:07 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313793212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3313793212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.2177413356
Short name T585
Test name
Test status
Simulation time 5689091424 ps
CPU time 8.4 seconds
Started Oct 14 11:20:10 PM UTC 24
Finished Oct 14 11:20:20 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177413356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2177413356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.4275735386
Short name T686
Test name
Test status
Simulation time 348544465848 ps
CPU time 751.6 seconds
Started Oct 14 11:20:58 PM UTC 24
Finished Oct 14 11:33:37 PM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275735386 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.4275735386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3638217636
Short name T592
Test name
Test status
Simulation time 4449048724 ps
CPU time 5.89 seconds
Started Oct 14 11:20:57 PM UTC 24
Finished Oct 14 11:21:04 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3638217636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.adc_ctrl_stress_all_with_rand_reset.3638217636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.270951536
Short name T605
Test name
Test status
Simulation time 517154700 ps
CPU time 1.38 seconds
Started Oct 14 11:22:51 PM UTC 24
Finished Oct 14 11:22:54 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270951536 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.270951536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2031690502
Short name T337
Test name
Test status
Simulation time 328306876113 ps
CPU time 190.68 seconds
Started Oct 14 11:22:07 PM UTC 24
Finished Oct 14 11:25:20 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031690502 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.2031690502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.3229265491
Short name T621
Test name
Test status
Simulation time 441413392561 ps
CPU time 158.24 seconds
Started Oct 14 11:22:15 PM UTC 24
Finished Oct 14 11:24:56 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229265491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3229265491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.3911982602
Short name T662
Test name
Test status
Simulation time 163230544543 ps
CPU time 543.9 seconds
Started Oct 14 11:21:09 PM UTC 24
Finished Oct 14 11:30:19 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911982602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3911982602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1023040527
Short name T685
Test name
Test status
Simulation time 486502410079 ps
CPU time 740.19 seconds
Started Oct 14 11:21:09 PM UTC 24
Finished Oct 14 11:33:37 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023040527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.1023040527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.510187419
Short name T612
Test name
Test status
Simulation time 491260599544 ps
CPU time 147.79 seconds
Started Oct 14 11:21:08 PM UTC 24
Finished Oct 14 11:23:38 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510187419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.510187419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.982217846
Short name T652
Test name
Test status
Simulation time 164086865482 ps
CPU time 439.33 seconds
Started Oct 14 11:21:09 PM UTC 24
Finished Oct 14 11:28:33 PM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982217846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.982217846
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.4148663128
Short name T697
Test name
Test status
Simulation time 537923957122 ps
CPU time 766.34 seconds
Started Oct 14 11:21:33 PM UTC 24
Finished Oct 14 11:34:27 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148663128 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.4148663128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2653795221
Short name T710
Test name
Test status
Simulation time 599715309663 ps
CPU time 838.29 seconds
Started Oct 14 11:21:35 PM UTC 24
Finished Oct 14 11:35:41 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653795221 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.2653795221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.1328460556
Short name T93
Test name
Test status
Simulation time 136222334446 ps
CPU time 1118.76 seconds
Started Oct 14 11:22:30 PM UTC 24
Finished Oct 14 11:41:21 PM UTC 24
Peak memory 213116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328460556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1328460556
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.3393218645
Short name T603
Test name
Test status
Simulation time 43554194038 ps
CPU time 21.8 seconds
Started Oct 14 11:22:22 PM UTC 24
Finished Oct 14 11:22:45 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393218645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3393218645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.2298250238
Short name T601
Test name
Test status
Simulation time 5445273781 ps
CPU time 6.17 seconds
Started Oct 14 11:22:22 PM UTC 24
Finished Oct 14 11:22:29 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298250238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2298250238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.3500490164
Short name T599
Test name
Test status
Simulation time 5971032724 ps
CPU time 24.34 seconds
Started Oct 14 11:21:08 PM UTC 24
Finished Oct 14 11:21:34 PM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500490164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3500490164
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.2457696843
Short name T641
Test name
Test status
Simulation time 202526934858 ps
CPU time 263.61 seconds
Started Oct 14 11:22:46 PM UTC 24
Finished Oct 14 11:27:13 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457696843 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.2457696843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.823387104
Short name T278
Test name
Test status
Simulation time 26155076822 ps
CPU time 26.54 seconds
Started Oct 14 11:22:34 PM UTC 24
Finished Oct 14 11:23:02 PM UTC 24
Peak memory 227060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=823387104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
37.adc_ctrl_stress_all_with_rand_reset.823387104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.857847570
Short name T617
Test name
Test status
Simulation time 296236238 ps
CPU time 1.45 seconds
Started Oct 14 11:24:27 PM UTC 24
Finished Oct 14 11:24:29 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857847570 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.857847570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.2982502274
Short name T191
Test name
Test status
Simulation time 323304074691 ps
CPU time 76.96 seconds
Started Oct 14 11:23:36 PM UTC 24
Finished Oct 14 11:24:55 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982502274 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.2982502274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3385333691
Short name T649
Test name
Test status
Simulation time 168464726044 ps
CPU time 252.24 seconds
Started Oct 14 11:23:39 PM UTC 24
Finished Oct 14 11:27:55 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385333691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3385333691
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.987243381
Short name T616
Test name
Test status
Simulation time 157578372781 ps
CPU time 81.38 seconds
Started Oct 14 11:23:03 PM UTC 24
Finished Oct 14 11:24:26 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987243381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.987243381
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.189151354
Short name T640
Test name
Test status
Simulation time 161798850987 ps
CPU time 244.95 seconds
Started Oct 14 11:23:04 PM UTC 24
Finished Oct 14 11:27:12 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189151354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.189151354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.100198125
Short name T620
Test name
Test status
Simulation time 157078312574 ps
CPU time 112.38 seconds
Started Oct 14 11:22:56 PM UTC 24
Finished Oct 14 11:24:51 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100198125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.100198125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2288079928
Short name T650
Test name
Test status
Simulation time 327102567833 ps
CPU time 306.56 seconds
Started Oct 14 11:22:57 PM UTC 24
Finished Oct 14 11:28:07 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288079928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.2288079928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.3839924334
Short name T740
Test name
Test status
Simulation time 358182198964 ps
CPU time 959.54 seconds
Started Oct 14 11:23:18 PM UTC 24
Finished Oct 14 11:39:27 PM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839924334 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.3839924334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1917884666
Short name T659
Test name
Test status
Simulation time 197361458793 ps
CPU time 343.39 seconds
Started Oct 14 11:23:27 PM UTC 24
Finished Oct 14 11:29:14 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917884666 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.1917884666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3652190178
Short name T226
Test name
Test status
Simulation time 110055335159 ps
CPU time 437.33 seconds
Started Oct 14 11:23:56 PM UTC 24
Finished Oct 14 11:31:18 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652190178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3652190178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.3174939168
Short name T636
Test name
Test status
Simulation time 44728548967 ps
CPU time 177.02 seconds
Started Oct 14 11:23:46 PM UTC 24
Finished Oct 14 11:26:46 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174939168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3174939168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.2481224072
Short name T614
Test name
Test status
Simulation time 3343532002 ps
CPU time 3.05 seconds
Started Oct 14 11:23:41 PM UTC 24
Finished Oct 14 11:23:45 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481224072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2481224072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.4060693139
Short name T608
Test name
Test status
Simulation time 5819814030 ps
CPU time 6.1 seconds
Started Oct 14 11:22:54 PM UTC 24
Finished Oct 14 11:23:02 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060693139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4060693139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.3870515655
Short name T317
Test name
Test status
Simulation time 298719246139 ps
CPU time 615.67 seconds
Started Oct 14 11:24:22 PM UTC 24
Finished Oct 14 11:34:43 PM UTC 24
Peak memory 220604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870515655 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.3870515655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1324739168
Short name T626
Test name
Test status
Simulation time 71696541691 ps
CPU time 41.48 seconds
Started Oct 14 11:24:21 PM UTC 24
Finished Oct 14 11:25:04 PM UTC 24
Peak memory 220988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1324739168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.adc_ctrl_stress_all_with_rand_reset.1324739168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.1267654893
Short name T630
Test name
Test status
Simulation time 501472971 ps
CPU time 1.11 seconds
Started Oct 14 11:25:21 PM UTC 24
Finished Oct 14 11:25:23 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267654893 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1267654893
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.1853381167
Short name T768
Test name
Test status
Simulation time 495897660063 ps
CPU time 1342.46 seconds
Started Oct 14 11:24:58 PM UTC 24
Finished Oct 14 11:47:34 PM UTC 24
Peak memory 212984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853381167 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.1853381167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.3042991887
Short name T690
Test name
Test status
Simulation time 214996240369 ps
CPU time 526.77 seconds
Started Oct 14 11:24:59 PM UTC 24
Finished Oct 14 11:33:52 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042991887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3042991887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.505833159
Short name T342
Test name
Test status
Simulation time 485772030942 ps
CPU time 758.06 seconds
Started Oct 14 11:24:52 PM UTC 24
Finished Oct 14 11:37:38 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505833159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.505833159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1614326106
Short name T731
Test name
Test status
Simulation time 329384630951 ps
CPU time 801.23 seconds
Started Oct 14 11:24:56 PM UTC 24
Finished Oct 14 11:38:26 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614326106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.1614326106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.21024855
Short name T192
Test name
Test status
Simulation time 497324430981 ps
CPU time 121.36 seconds
Started Oct 14 11:24:31 PM UTC 24
Finished Oct 14 11:26:35 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21024855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.21024855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.3634434250
Short name T642
Test name
Test status
Simulation time 328352003995 ps
CPU time 144.64 seconds
Started Oct 14 11:24:51 PM UTC 24
Finished Oct 14 11:27:18 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634434250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.3634434250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.477109670
Short name T634
Test name
Test status
Simulation time 177842454864 ps
CPU time 103.33 seconds
Started Oct 14 11:24:56 PM UTC 24
Finished Oct 14 11:26:41 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477109670 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.477109670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2712044553
Short name T783
Test name
Test status
Simulation time 616451712056 ps
CPU time 1590.11 seconds
Started Oct 14 11:24:58 PM UTC 24
Finished Oct 14 11:51:44 PM UTC 24
Peak memory 212848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712044553 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.2712044553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.534792539
Short name T678
Test name
Test status
Simulation time 112358471952 ps
CPU time 451.12 seconds
Started Oct 14 11:25:07 PM UTC 24
Finished Oct 14 11:32:43 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534792539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.534792539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.4088031038
Short name T648
Test name
Test status
Simulation time 37162753413 ps
CPU time 154.26 seconds
Started Oct 14 11:25:05 PM UTC 24
Finished Oct 14 11:27:42 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088031038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4088031038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.4121075736
Short name T627
Test name
Test status
Simulation time 4065312114 ps
CPU time 5.67 seconds
Started Oct 14 11:25:00 PM UTC 24
Finished Oct 14 11:25:07 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121075736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4121075736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.3487824545
Short name T624
Test name
Test status
Simulation time 5948656941 ps
CPU time 27.09 seconds
Started Oct 14 11:24:30 PM UTC 24
Finished Oct 14 11:24:58 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487824545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3487824545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3911404890
Short name T35
Test name
Test status
Simulation time 21468902134 ps
CPU time 21.33 seconds
Started Oct 14 11:25:17 PM UTC 24
Finished Oct 14 11:25:39 PM UTC 24
Peak memory 220712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3911404890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.adc_ctrl_stress_all_with_rand_reset.3911404890
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.4126756946
Short name T148
Test name
Test status
Simulation time 468817435 ps
CPU time 2.09 seconds
Started Oct 14 10:28:49 PM UTC 24
Finished Oct 14 10:28:52 PM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126756946 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4126756946
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.2764300996
Short name T78
Test name
Test status
Simulation time 191517928488 ps
CPU time 281.03 seconds
Started Oct 14 10:28:12 PM UTC 24
Finished Oct 14 10:32:56 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764300996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2764300996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.161018970
Short name T143
Test name
Test status
Simulation time 326000758864 ps
CPU time 825.64 seconds
Started Oct 14 10:27:50 PM UTC 24
Finished Oct 14 10:41:44 PM UTC 24
Peak memory 212800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161018970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.161018970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.1523732884
Short name T137
Test name
Test status
Simulation time 332333183759 ps
CPU time 234.22 seconds
Started Oct 14 10:27:34 PM UTC 24
Finished Oct 14 10:31:31 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523732884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1523732884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3359046638
Short name T381
Test name
Test status
Simulation time 493656262978 ps
CPU time 564.82 seconds
Started Oct 14 10:27:45 PM UTC 24
Finished Oct 14 10:37:16 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359046638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3359046638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.4193779577
Short name T186
Test name
Test status
Simulation time 197114545461 ps
CPU time 173.6 seconds
Started Oct 14 10:27:57 PM UTC 24
Finished Oct 14 10:30:53 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193779577 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.4193779577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2546898685
Short name T394
Test name
Test status
Simulation time 605775308628 ps
CPU time 860.72 seconds
Started Oct 14 10:27:59 PM UTC 24
Finished Oct 14 10:42:28 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546898685 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.2546898685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3310054172
Short name T53
Test name
Test status
Simulation time 76062847285 ps
CPU time 354.42 seconds
Started Oct 14 10:28:24 PM UTC 24
Finished Oct 14 10:34:23 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310054172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3310054172
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2334396218
Short name T149
Test name
Test status
Simulation time 41762027209 ps
CPU time 41.39 seconds
Started Oct 14 10:28:23 PM UTC 24
Finished Oct 14 10:29:06 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334396218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2334396218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.3371277141
Short name T99
Test name
Test status
Simulation time 3312718135 ps
CPU time 5.87 seconds
Started Oct 14 10:28:16 PM UTC 24
Finished Oct 14 10:28:23 PM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371277141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3371277141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1351017272
Short name T75
Test name
Test status
Simulation time 8572961218 ps
CPU time 22.43 seconds
Started Oct 14 10:28:40 PM UTC 24
Finished Oct 14 10:29:03 PM UTC 24
Peak memory 242364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351017272 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1351017272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.1143092989
Short name T119
Test name
Test status
Simulation time 5875957613 ps
CPU time 26.56 seconds
Started Oct 14 10:27:30 PM UTC 24
Finished Oct 14 10:27:58 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143092989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1143092989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4239657977
Short name T42
Test name
Test status
Simulation time 40756132082 ps
CPU time 74.37 seconds
Started Oct 14 10:28:28 PM UTC 24
Finished Oct 14 10:29:45 PM UTC 24
Peak memory 220980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4239657977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.adc_ctrl_stress_all_with_rand_reset.4239657977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.825289211
Short name T643
Test name
Test status
Simulation time 331185740 ps
CPU time 1.13 seconds
Started Oct 14 11:27:19 PM UTC 24
Finished Oct 14 11:27:21 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825289211 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.825289211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.900479439
Short name T328
Test name
Test status
Simulation time 376683706499 ps
CPU time 175.78 seconds
Started Oct 14 11:26:42 PM UTC 24
Finished Oct 14 11:29:41 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900479439 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.900479439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.2344856019
Short name T754
Test name
Test status
Simulation time 367590097039 ps
CPU time 950.21 seconds
Started Oct 14 11:26:46 PM UTC 24
Finished Oct 14 11:42:46 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344856019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2344856019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.3473390243
Short name T638
Test name
Test status
Simulation time 336371915827 ps
CPU time 68.68 seconds
Started Oct 14 11:25:49 PM UTC 24
Finished Oct 14 11:26:59 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473390243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3473390243
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3183400601
Short name T654
Test name
Test status
Simulation time 167938558832 ps
CPU time 165.83 seconds
Started Oct 14 11:26:05 PM UTC 24
Finished Oct 14 11:28:54 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183400601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.3183400601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.1420091681
Short name T204
Test name
Test status
Simulation time 495602721084 ps
CPU time 330.59 seconds
Started Oct 14 11:25:34 PM UTC 24
Finished Oct 14 11:31:08 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420091681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1420091681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.1875041413
Short name T770
Test name
Test status
Simulation time 497716491965 ps
CPU time 1343.52 seconds
Started Oct 14 11:25:40 PM UTC 24
Finished Oct 14 11:48:17 PM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875041413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.1875041413
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1675883219
Short name T355
Test name
Test status
Simulation time 514358861304 ps
CPU time 1290.78 seconds
Started Oct 14 11:26:35 PM UTC 24
Finished Oct 14 11:48:18 PM UTC 24
Peak memory 213044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675883219 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.1675883219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.625797709
Short name T666
Test name
Test status
Simulation time 421729686150 ps
CPU time 265.91 seconds
Started Oct 14 11:26:42 PM UTC 24
Finished Oct 14 11:31:12 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625797709 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.625797709
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.1536159965
Short name T712
Test name
Test status
Simulation time 110215896873 ps
CPU time 553.9 seconds
Started Oct 14 11:27:05 PM UTC 24
Finished Oct 14 11:36:24 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536159965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1536159965
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.138954531
Short name T647
Test name
Test status
Simulation time 40286463173 ps
CPU time 39.15 seconds
Started Oct 14 11:27:01 PM UTC 24
Finished Oct 14 11:27:41 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138954531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.138954531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.4294607206
Short name T639
Test name
Test status
Simulation time 3405667854 ps
CPU time 6.5 seconds
Started Oct 14 11:26:57 PM UTC 24
Finished Oct 14 11:27:04 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294607206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4294607206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.4057671655
Short name T632
Test name
Test status
Simulation time 5929847620 ps
CPU time 23.28 seconds
Started Oct 14 11:25:24 PM UTC 24
Finished Oct 14 11:25:48 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057671655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4057671655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.4085585443
Short name T672
Test name
Test status
Simulation time 200994102216 ps
CPU time 291.42 seconds
Started Oct 14 11:27:14 PM UTC 24
Finished Oct 14 11:32:09 PM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085585443 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.4085585443
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4001174235
Short name T645
Test name
Test status
Simulation time 3786472511 ps
CPU time 21.01 seconds
Started Oct 14 11:27:13 PM UTC 24
Finished Oct 14 11:27:35 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4001174235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.adc_ctrl_stress_all_with_rand_reset.4001174235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.3747650930
Short name T656
Test name
Test status
Simulation time 498058020 ps
CPU time 1.78 seconds
Started Oct 14 11:28:55 PM UTC 24
Finished Oct 14 11:28:58 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747650930 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3747650930
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.4151396252
Short name T674
Test name
Test status
Simulation time 325653029619 ps
CPU time 257.44 seconds
Started Oct 14 11:27:56 PM UTC 24
Finished Oct 14 11:32:16 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151396252 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.4151396252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.4094826917
Short name T687
Test name
Test status
Simulation time 517414989667 ps
CPU time 342.86 seconds
Started Oct 14 11:27:58 PM UTC 24
Finished Oct 14 11:33:45 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094826917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4094826917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.1245329157
Short name T703
Test name
Test status
Simulation time 487495154744 ps
CPU time 446.86 seconds
Started Oct 14 11:27:36 PM UTC 24
Finished Oct 14 11:35:08 PM UTC 24
Peak memory 210360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245329157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1245329157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1095801020
Short name T775
Test name
Test status
Simulation time 493707526641 ps
CPU time 1282.08 seconds
Started Oct 14 11:27:41 PM UTC 24
Finished Oct 14 11:49:16 PM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095801020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.1095801020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.1082194048
Short name T667
Test name
Test status
Simulation time 163899145133 ps
CPU time 230.31 seconds
Started Oct 14 11:27:22 PM UTC 24
Finished Oct 14 11:31:15 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082194048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1082194048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.220095894
Short name T722
Test name
Test status
Simulation time 327304328446 ps
CPU time 589.97 seconds
Started Oct 14 11:27:28 PM UTC 24
Finished Oct 14 11:37:25 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220095894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.220095894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.140683498
Short name T658
Test name
Test status
Simulation time 171366109850 ps
CPU time 87.33 seconds
Started Oct 14 11:27:42 PM UTC 24
Finished Oct 14 11:29:11 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140683498 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.140683498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1892169792
Short name T714
Test name
Test status
Simulation time 408075820374 ps
CPU time 538.04 seconds
Started Oct 14 11:27:43 PM UTC 24
Finished Oct 14 11:36:48 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892169792 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1892169792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.1358080692
Short name T735
Test name
Test status
Simulation time 94589778082 ps
CPU time 626.16 seconds
Started Oct 14 11:28:34 PM UTC 24
Finished Oct 14 11:39:07 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358080692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1358080692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.3543276137
Short name T661
Test name
Test status
Simulation time 40179408532 ps
CPU time 113.8 seconds
Started Oct 14 11:28:13 PM UTC 24
Finished Oct 14 11:30:09 PM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543276137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3543276137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.731974217
Short name T651
Test name
Test status
Simulation time 2674588980 ps
CPU time 3.67 seconds
Started Oct 14 11:28:08 PM UTC 24
Finished Oct 14 11:28:12 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731974217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.731974217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.1723296646
Short name T644
Test name
Test status
Simulation time 6151439391 ps
CPU time 7.09 seconds
Started Oct 14 11:27:19 PM UTC 24
Finished Oct 14 11:27:27 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723296646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1723296646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.3083168386
Short name T721
Test name
Test status
Simulation time 162969562384 ps
CPU time 503.63 seconds
Started Oct 14 11:28:54 PM UTC 24
Finished Oct 14 11:37:23 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083168386 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.3083168386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.671284715
Short name T655
Test name
Test status
Simulation time 7123399006 ps
CPU time 10.81 seconds
Started Oct 14 11:28:42 PM UTC 24
Finished Oct 14 11:28:54 PM UTC 24
Peak memory 220716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=671284715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
41.adc_ctrl_stress_all_with_rand_reset.671284715
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.170792059
Short name T668
Test name
Test status
Simulation time 421032135 ps
CPU time 1.32 seconds
Started Oct 14 11:31:19 PM UTC 24
Finished Oct 14 11:31:21 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170792059 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.170792059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.352179173
Short name T733
Test name
Test status
Simulation time 181393470716 ps
CPU time 502.81 seconds
Started Oct 14 11:30:20 PM UTC 24
Finished Oct 14 11:38:49 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352179173 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.352179173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.2591665419
Short name T341
Test name
Test status
Simulation time 518645342967 ps
CPU time 530.01 seconds
Started Oct 14 11:30:24 PM UTC 24
Finished Oct 14 11:39:20 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591665419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2591665419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2433767111
Short name T673
Test name
Test status
Simulation time 165226870513 ps
CPU time 171.29 seconds
Started Oct 14 11:29:15 PM UTC 24
Finished Oct 14 11:32:09 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433767111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2433767111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3867147843
Short name T730
Test name
Test status
Simulation time 324640080246 ps
CPU time 515.81 seconds
Started Oct 14 11:29:35 PM UTC 24
Finished Oct 14 11:38:16 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867147843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3867147843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.2610716173
Short name T771
Test name
Test status
Simulation time 485647357295 ps
CPU time 1183.15 seconds
Started Oct 14 11:29:04 PM UTC 24
Finished Oct 14 11:48:58 PM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610716173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2610716173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.718911653
Short name T736
Test name
Test status
Simulation time 497600298174 ps
CPU time 597.58 seconds
Started Oct 14 11:29:12 PM UTC 24
Finished Oct 14 11:39:16 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718911653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.718911653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3150603280
Short name T744
Test name
Test status
Simulation time 513386985701 ps
CPU time 605.18 seconds
Started Oct 14 11:29:42 PM UTC 24
Finished Oct 14 11:39:53 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150603280 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3150603280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.67076769
Short name T792
Test name
Test status
Simulation time 620781224226 ps
CPU time 1758.66 seconds
Started Oct 14 11:30:10 PM UTC 24
Finished Oct 14 11:59:46 PM UTC 24
Peak memory 212768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67076769 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.67076769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.623195314
Short name T366
Test name
Test status
Simulation time 79215719273 ps
CPU time 459.14 seconds
Started Oct 14 11:31:09 PM UTC 24
Finished Oct 14 11:38:53 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623195314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.623195314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3358883473
Short name T677
Test name
Test status
Simulation time 36227592361 ps
CPU time 86 seconds
Started Oct 14 11:31:07 PM UTC 24
Finished Oct 14 11:32:35 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358883473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3358883473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.185795524
Short name T665
Test name
Test status
Simulation time 4009200709 ps
CPU time 3.02 seconds
Started Oct 14 11:31:02 PM UTC 24
Finished Oct 14 11:31:06 PM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185795524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.185795524
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.2309668454
Short name T657
Test name
Test status
Simulation time 6031390534 ps
CPU time 3.42 seconds
Started Oct 14 11:28:59 PM UTC 24
Finished Oct 14 11:29:04 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309668454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2309668454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2817131148
Short name T352
Test name
Test status
Simulation time 359268462060 ps
CPU time 278.04 seconds
Started Oct 14 11:31:16 PM UTC 24
Finished Oct 14 11:35:58 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817131148 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.2817131148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.720429370
Short name T62
Test name
Test status
Simulation time 9436985836 ps
CPU time 49.44 seconds
Started Oct 14 11:31:12 PM UTC 24
Finished Oct 14 11:32:03 PM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=720429370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
42.adc_ctrl_stress_all_with_rand_reset.720429370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.4177235698
Short name T679
Test name
Test status
Simulation time 538300944 ps
CPU time 1.29 seconds
Started Oct 14 11:32:44 PM UTC 24
Finished Oct 14 11:32:46 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177235698 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4177235698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.456252960
Short name T334
Test name
Test status
Simulation time 156909655638 ps
CPU time 155.75 seconds
Started Oct 14 11:32:09 PM UTC 24
Finished Oct 14 11:34:47 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456252960 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.456252960
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.2054304695
Short name T702
Test name
Test status
Simulation time 496134864462 ps
CPU time 174.72 seconds
Started Oct 14 11:32:10 PM UTC 24
Finished Oct 14 11:35:08 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054304695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2054304695
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.148542973
Short name T743
Test name
Test status
Simulation time 485762959817 ps
CPU time 476.56 seconds
Started Oct 14 11:31:45 PM UTC 24
Finished Oct 14 11:39:47 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148542973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.148542973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2321501579
Short name T737
Test name
Test status
Simulation time 163493484186 ps
CPU time 437.26 seconds
Started Oct 14 11:32:01 PM UTC 24
Finished Oct 14 11:39:23 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321501579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.2321501579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.3300113369
Short name T723
Test name
Test status
Simulation time 487810669734 ps
CPU time 350.56 seconds
Started Oct 14 11:31:31 PM UTC 24
Finished Oct 14 11:37:26 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300113369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3300113369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.2298138377
Short name T709
Test name
Test status
Simulation time 328309008868 ps
CPU time 232.35 seconds
Started Oct 14 11:31:32 PM UTC 24
Finished Oct 14 11:35:27 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298138377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.2298138377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2500086291
Short name T682
Test name
Test status
Simulation time 192898115443 ps
CPU time 59.09 seconds
Started Oct 14 11:32:04 PM UTC 24
Finished Oct 14 11:33:05 PM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500086291 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.2500086291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.1846694632
Short name T734
Test name
Test status
Simulation time 75616079404 ps
CPU time 396.47 seconds
Started Oct 14 11:32:21 PM UTC 24
Finished Oct 14 11:39:02 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846694632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1846694632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.1945681798
Short name T688
Test name
Test status
Simulation time 42290862292 ps
CPU time 86.93 seconds
Started Oct 14 11:32:20 PM UTC 24
Finished Oct 14 11:33:49 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945681798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1945681798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.1359938554
Short name T675
Test name
Test status
Simulation time 2834854653 ps
CPU time 2.15 seconds
Started Oct 14 11:32:17 PM UTC 24
Finished Oct 14 11:32:20 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359938554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1359938554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.502913740
Short name T669
Test name
Test status
Simulation time 5842638031 ps
CPU time 7.38 seconds
Started Oct 14 11:31:22 PM UTC 24
Finished Oct 14 11:31:30 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502913740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.502913740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.2067647013
Short name T784
Test name
Test status
Simulation time 504728116727 ps
CPU time 1140.9 seconds
Started Oct 14 11:32:36 PM UTC 24
Finished Oct 14 11:51:48 PM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067647013 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.2067647013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2954235001
Short name T680
Test name
Test status
Simulation time 2152148709 ps
CPU time 9.55 seconds
Started Oct 14 11:32:36 PM UTC 24
Finished Oct 14 11:32:46 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2954235001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.adc_ctrl_stress_all_with_rand_reset.2954235001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.848804975
Short name T693
Test name
Test status
Simulation time 483149320 ps
CPU time 1.85 seconds
Started Oct 14 11:34:06 PM UTC 24
Finished Oct 14 11:34:09 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848804975 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.848804975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1776903834
Short name T311
Test name
Test status
Simulation time 478659593548 ps
CPU time 536.49 seconds
Started Oct 14 11:33:38 PM UTC 24
Finished Oct 14 11:42:41 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776903834 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.1776903834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.3060595474
Short name T95
Test name
Test status
Simulation time 167140073468 ps
CPU time 486.4 seconds
Started Oct 14 11:33:45 PM UTC 24
Finished Oct 14 11:41:57 PM UTC 24
Peak memory 210112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060595474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3060595474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.3654136231
Short name T772
Test name
Test status
Simulation time 323649039900 ps
CPU time 945.57 seconds
Started Oct 14 11:33:05 PM UTC 24
Finished Oct 14 11:49:01 PM UTC 24
Peak memory 212740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654136231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3654136231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3279343325
Short name T708
Test name
Test status
Simulation time 329284804236 ps
CPU time 136.15 seconds
Started Oct 14 11:33:06 PM UTC 24
Finished Oct 14 11:35:25 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279343325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.3279343325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.348440498
Short name T738
Test name
Test status
Simulation time 492039891657 ps
CPU time 392.97 seconds
Started Oct 14 11:32:47 PM UTC 24
Finished Oct 14 11:39:24 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348440498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.348440498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.4101380288
Short name T762
Test name
Test status
Simulation time 495720212463 ps
CPU time 764.02 seconds
Started Oct 14 11:32:56 PM UTC 24
Finished Oct 14 11:45:49 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101380288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.4101380288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.4043969605
Short name T711
Test name
Test status
Simulation time 176716104126 ps
CPU time 170.57 seconds
Started Oct 14 11:33:23 PM UTC 24
Finished Oct 14 11:36:16 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043969605 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.4043969605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4175869525
Short name T725
Test name
Test status
Simulation time 591229657915 ps
CPU time 235.33 seconds
Started Oct 14 11:33:38 PM UTC 24
Finished Oct 14 11:37:37 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175869525 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.4175869525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.974429063
Short name T769
Test name
Test status
Simulation time 139569448420 ps
CPU time 854.03 seconds
Started Oct 14 11:33:53 PM UTC 24
Finished Oct 14 11:48:15 PM UTC 24
Peak memory 213132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974429063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.974429063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.2735787509
Short name T698
Test name
Test status
Simulation time 33102759463 ps
CPU time 35.29 seconds
Started Oct 14 11:33:52 PM UTC 24
Finished Oct 14 11:34:28 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735787509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2735787509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.290206569
Short name T691
Test name
Test status
Simulation time 2984607151 ps
CPU time 4.05 seconds
Started Oct 14 11:33:50 PM UTC 24
Finished Oct 14 11:33:55 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290206569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.290206569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.760728848
Short name T681
Test name
Test status
Simulation time 6074670224 ps
CPU time 7.54 seconds
Started Oct 14 11:32:47 PM UTC 24
Finished Oct 14 11:32:55 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760728848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.760728848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.2161226247
Short name T778
Test name
Test status
Simulation time 249178323949 ps
CPU time 967.55 seconds
Started Oct 14 11:33:59 PM UTC 24
Finished Oct 14 11:50:16 PM UTC 24
Peak memory 223628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161226247 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.2161226247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2286163011
Short name T98
Test name
Test status
Simulation time 1774726898 ps
CPU time 8.16 seconds
Started Oct 14 11:33:56 PM UTC 24
Finished Oct 14 11:34:05 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2286163011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.adc_ctrl_stress_all_with_rand_reset.2286163011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.3682925405
Short name T705
Test name
Test status
Simulation time 472844929 ps
CPU time 1.37 seconds
Started Oct 14 11:35:15 PM UTC 24
Finished Oct 14 11:35:17 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682925405 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3682925405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.1168801557
Short name T335
Test name
Test status
Simulation time 368490122008 ps
CPU time 327.48 seconds
Started Oct 14 11:34:37 PM UTC 24
Finished Oct 14 11:40:08 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168801557 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.1168801557
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.2856006730
Short name T358
Test name
Test status
Simulation time 368311188513 ps
CPU time 204.98 seconds
Started Oct 14 11:34:44 PM UTC 24
Finished Oct 14 11:38:12 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856006730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2856006730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.2870371238
Short name T92
Test name
Test status
Simulation time 169393881941 ps
CPU time 411.68 seconds
Started Oct 14 11:34:24 PM UTC 24
Finished Oct 14 11:41:21 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870371238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2870371238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1046960651
Short name T96
Test name
Test status
Simulation time 163649471352 ps
CPU time 451.02 seconds
Started Oct 14 11:34:27 PM UTC 24
Finished Oct 14 11:42:04 PM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046960651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.1046960651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.1070224544
Short name T715
Test name
Test status
Simulation time 325408021205 ps
CPU time 150.47 seconds
Started Oct 14 11:34:15 PM UTC 24
Finished Oct 14 11:36:48 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070224544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1070224544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.381266929
Short name T766
Test name
Test status
Simulation time 320205363151 ps
CPU time 759.27 seconds
Started Oct 14 11:34:15 PM UTC 24
Finished Oct 14 11:47:02 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381266929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.381266929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.988482012
Short name T316
Test name
Test status
Simulation time 562033783962 ps
CPU time 1061.41 seconds
Started Oct 14 11:34:29 PM UTC 24
Finished Oct 14 11:52:22 PM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988482012 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.988482012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3676017924
Short name T765
Test name
Test status
Simulation time 400620251527 ps
CPU time 720.13 seconds
Started Oct 14 11:34:33 PM UTC 24
Finished Oct 14 11:46:41 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676017924 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.3676017924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2280692032
Short name T724
Test name
Test status
Simulation time 46177899287 ps
CPU time 139.5 seconds
Started Oct 14 11:35:05 PM UTC 24
Finished Oct 14 11:37:27 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280692032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2280692032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.425353387
Short name T701
Test name
Test status
Simulation time 3214172131 ps
CPU time 13.97 seconds
Started Oct 14 11:34:49 PM UTC 24
Finished Oct 14 11:35:04 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425353387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.425353387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.1332258944
Short name T699
Test name
Test status
Simulation time 5717518361 ps
CPU time 24.04 seconds
Started Oct 14 11:34:10 PM UTC 24
Finished Oct 14 11:34:35 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332258944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1332258944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.1562531814
Short name T763
Test name
Test status
Simulation time 414627406524 ps
CPU time 635.12 seconds
Started Oct 14 11:35:09 PM UTC 24
Finished Oct 14 11:45:51 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562531814 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.1562531814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3120097307
Short name T706
Test name
Test status
Simulation time 965147625 ps
CPU time 9.05 seconds
Started Oct 14 11:35:08 PM UTC 24
Finished Oct 14 11:35:18 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3120097307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.adc_ctrl_stress_all_with_rand_reset.3120097307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.3960856557
Short name T717
Test name
Test status
Simulation time 470984001 ps
CPU time 2.83 seconds
Started Oct 14 11:36:49 PM UTC 24
Finished Oct 14 11:36:53 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960856557 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3960856557
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.3186632533
Short name T338
Test name
Test status
Simulation time 338222857637 ps
CPU time 118.72 seconds
Started Oct 14 11:35:59 PM UTC 24
Finished Oct 14 11:37:59 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186632533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.3186632533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2534696640
Short name T756
Test name
Test status
Simulation time 163755324619 ps
CPU time 399.48 seconds
Started Oct 14 11:36:18 PM UTC 24
Finished Oct 14 11:43:02 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534696640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2534696640
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.2297872654
Short name T745
Test name
Test status
Simulation time 167569703848 ps
CPU time 276.82 seconds
Started Oct 14 11:35:25 PM UTC 24
Finished Oct 14 11:40:06 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297872654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2297872654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3825042276
Short name T777
Test name
Test status
Simulation time 329101942288 ps
CPU time 868.22 seconds
Started Oct 14 11:35:25 PM UTC 24
Finished Oct 14 11:50:03 PM UTC 24
Peak memory 212764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825042276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.3825042276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.158960851
Short name T746
Test name
Test status
Simulation time 327045457213 ps
CPU time 286.76 seconds
Started Oct 14 11:35:19 PM UTC 24
Finished Oct 14 11:40:09 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158960851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.158960851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.2203772544
Short name T747
Test name
Test status
Simulation time 492993832772 ps
CPU time 298.14 seconds
Started Oct 14 11:35:24 PM UTC 24
Finished Oct 14 11:40:26 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203772544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.2203772544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.1921681609
Short name T781
Test name
Test status
Simulation time 407310945970 ps
CPU time 949.32 seconds
Started Oct 14 11:35:28 PM UTC 24
Finished Oct 14 11:51:27 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921681609 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.1921681609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1663030813
Short name T761
Test name
Test status
Simulation time 610481935964 ps
CPU time 582.64 seconds
Started Oct 14 11:35:43 PM UTC 24
Finished Oct 14 11:45:32 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663030813 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.1663030813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.2303132723
Short name T767
Test name
Test status
Simulation time 137633575493 ps
CPU time 625.07 seconds
Started Oct 14 11:36:34 PM UTC 24
Finished Oct 14 11:47:06 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303132723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2303132723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.3585525001
Short name T718
Test name
Test status
Simulation time 43582385950 ps
CPU time 30.75 seconds
Started Oct 14 11:36:25 PM UTC 24
Finished Oct 14 11:36:57 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585525001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3585525001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.1293781880
Short name T713
Test name
Test status
Simulation time 3982636329 ps
CPU time 10.32 seconds
Started Oct 14 11:36:22 PM UTC 24
Finished Oct 14 11:36:33 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293781880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1293781880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.1009918060
Short name T707
Test name
Test status
Simulation time 5896509139 ps
CPU time 4.41 seconds
Started Oct 14 11:35:18 PM UTC 24
Finished Oct 14 11:35:24 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009918060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1009918060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.1375321230
Short name T759
Test name
Test status
Simulation time 164368573814 ps
CPU time 451.42 seconds
Started Oct 14 11:36:49 PM UTC 24
Finished Oct 14 11:44:26 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375321230 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.1375321230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1229980630
Short name T727
Test name
Test status
Simulation time 819184119536 ps
CPU time 80.92 seconds
Started Oct 14 11:36:48 PM UTC 24
Finished Oct 14 11:38:11 PM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1229980630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.adc_ctrl_stress_all_with_rand_reset.1229980630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.2204191951
Short name T729
Test name
Test status
Simulation time 292859896 ps
CPU time 1.81 seconds
Started Oct 14 11:38:12 PM UTC 24
Finished Oct 14 11:38:15 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204191951 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2204191951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1205414629
Short name T760
Test name
Test status
Simulation time 335330739349 ps
CPU time 477.09 seconds
Started Oct 14 11:37:28 PM UTC 24
Finished Oct 14 11:45:30 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205414629 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.1205414629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2335467903
Short name T774
Test name
Test status
Simulation time 527538994364 ps
CPU time 678.77 seconds
Started Oct 14 11:37:38 PM UTC 24
Finished Oct 14 11:49:04 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335467903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2335467903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.2369855756
Short name T750
Test name
Test status
Simulation time 326818763651 ps
CPU time 222.95 seconds
Started Oct 14 11:37:10 PM UTC 24
Finished Oct 14 11:40:56 PM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369855756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2369855756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4227475976
Short name T793
Test name
Test status
Simulation time 489936371483 ps
CPU time 1400.97 seconds
Started Oct 14 11:37:24 PM UTC 24
Finished Oct 15 12:01:00 AM UTC 24
Peak memory 212856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227475976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.4227475976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.2378458
Short name T360
Test name
Test status
Simulation time 492810163360 ps
CPU time 647.85 seconds
Started Oct 14 11:36:57 PM UTC 24
Finished Oct 14 11:47:52 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S
EQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2378458
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.4104921323
Short name T787
Test name
Test status
Simulation time 330960462947 ps
CPU time 918.6 seconds
Started Oct 14 11:37:04 PM UTC 24
Finished Oct 14 11:52:33 PM UTC 24
Peak memory 212708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104921323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.4104921323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.1422733545
Short name T753
Test name
Test status
Simulation time 354726455348 ps
CPU time 300.39 seconds
Started Oct 14 11:37:26 PM UTC 24
Finished Oct 14 11:42:30 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422733545 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.1422733545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2150405065
Short name T97
Test name
Test status
Simulation time 387613467641 ps
CPU time 280.53 seconds
Started Oct 14 11:37:27 PM UTC 24
Finished Oct 14 11:42:11 PM UTC 24
Peak memory 210044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150405065 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.2150405065
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.3974564364
Short name T369
Test name
Test status
Simulation time 93132956562 ps
CPU time 506.52 seconds
Started Oct 14 11:38:00 PM UTC 24
Finished Oct 14 11:46:33 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974564364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3974564364
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.3194593107
Short name T728
Test name
Test status
Simulation time 21282066544 ps
CPU time 23.38 seconds
Started Oct 14 11:37:47 PM UTC 24
Finished Oct 14 11:38:12 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194593107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3194593107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.3661034626
Short name T726
Test name
Test status
Simulation time 3095666082 ps
CPU time 6.68 seconds
Started Oct 14 11:37:39 PM UTC 24
Finished Oct 14 11:37:47 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661034626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3661034626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.2903682212
Short name T719
Test name
Test status
Simulation time 6068069809 ps
CPU time 7.89 seconds
Started Oct 14 11:36:54 PM UTC 24
Finished Oct 14 11:37:03 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903682212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2903682212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.3283669203
Short name T758
Test name
Test status
Simulation time 167619295722 ps
CPU time 360.56 seconds
Started Oct 14 11:38:12 PM UTC 24
Finished Oct 14 11:44:17 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283669203 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.3283669203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2089705708
Short name T218
Test name
Test status
Simulation time 2808310676 ps
CPU time 11.98 seconds
Started Oct 14 11:38:11 PM UTC 24
Finished Oct 14 11:38:24 PM UTC 24
Peak memory 220444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2089705708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.adc_ctrl_stress_all_with_rand_reset.2089705708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.2677856201
Short name T741
Test name
Test status
Simulation time 482633238 ps
CPU time 2.9 seconds
Started Oct 14 11:39:28 PM UTC 24
Finished Oct 14 11:39:32 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677856201 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2677856201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.3158863812
Short name T791
Test name
Test status
Simulation time 507299040198 ps
CPU time 953.89 seconds
Started Oct 14 11:39:03 PM UTC 24
Finished Oct 14 11:55:07 PM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158863812 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.3158863812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2085919335
Short name T788
Test name
Test status
Simulation time 347298400980 ps
CPU time 860.69 seconds
Started Oct 14 11:39:08 PM UTC 24
Finished Oct 14 11:53:38 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085919335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2085919335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.3399727225
Short name T350
Test name
Test status
Simulation time 326190125533 ps
CPU time 340.77 seconds
Started Oct 14 11:38:27 PM UTC 24
Finished Oct 14 11:44:12 PM UTC 24
Peak memory 210288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399727225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3399727225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2099041980
Short name T90
Test name
Test status
Simulation time 496421417523 ps
CPU time 146.94 seconds
Started Oct 14 11:38:42 PM UTC 24
Finished Oct 14 11:41:11 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099041980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.2099041980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.611240466
Short name T782
Test name
Test status
Simulation time 334638096384 ps
CPU time 787.3 seconds
Started Oct 14 11:38:17 PM UTC 24
Finished Oct 14 11:51:33 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611240466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.611240466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.1975487718
Short name T785
Test name
Test status
Simulation time 326396319536 ps
CPU time 806.95 seconds
Started Oct 14 11:38:26 PM UTC 24
Finished Oct 14 11:52:01 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975487718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.1975487718
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1198570067
Short name T794
Test name
Test status
Simulation time 601566804782 ps
CPU time 1813.21 seconds
Started Oct 14 11:38:50 PM UTC 24
Finished Oct 15 12:09:22 AM UTC 24
Peak memory 212656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198570067 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.1198570067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1634966725
Short name T786
Test name
Test status
Simulation time 607542138114 ps
CPU time 807.78 seconds
Started Oct 14 11:38:54 PM UTC 24
Finished Oct 14 11:52:30 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634966725 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.1634966725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.2467284940
Short name T780
Test name
Test status
Simulation time 134852205614 ps
CPU time 674.95 seconds
Started Oct 14 11:39:20 PM UTC 24
Finished Oct 14 11:50:43 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467284940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2467284940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.1506152772
Short name T748
Test name
Test status
Simulation time 31941837731 ps
CPU time 71.98 seconds
Started Oct 14 11:39:17 PM UTC 24
Finished Oct 14 11:40:31 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506152772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1506152772
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.1924085593
Short name T739
Test name
Test status
Simulation time 5122994926 ps
CPU time 10.96 seconds
Started Oct 14 11:39:14 PM UTC 24
Finished Oct 14 11:39:26 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924085593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1924085593
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.2013970846
Short name T732
Test name
Test status
Simulation time 5572824191 ps
CPU time 23.35 seconds
Started Oct 14 11:38:17 PM UTC 24
Finished Oct 14 11:38:41 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013970846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2013970846
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.656367748
Short name T789
Test name
Test status
Simulation time 341673060206 ps
CPU time 890.98 seconds
Started Oct 14 11:39:25 PM UTC 24
Finished Oct 14 11:54:25 PM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656367748 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.656367748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3199472518
Short name T327
Test name
Test status
Simulation time 12734954090 ps
CPU time 27.92 seconds
Started Oct 14 11:39:24 PM UTC 24
Finished Oct 14 11:39:54 PM UTC 24
Peak memory 220712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3199472518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.adc_ctrl_stress_all_with_rand_reset.3199472518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.3860347510
Short name T752
Test name
Test status
Simulation time 283956696 ps
CPU time 2.02 seconds
Started Oct 14 11:41:00 PM UTC 24
Finished Oct 14 11:41:03 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860347510 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3860347510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.456637008
Short name T354
Test name
Test status
Simulation time 536698984951 ps
CPU time 615.26 seconds
Started Oct 14 11:40:09 PM UTC 24
Finished Oct 14 11:50:31 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456637008 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.456637008
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.4154294503
Short name T773
Test name
Test status
Simulation time 350076706984 ps
CPU time 525.75 seconds
Started Oct 14 11:40:10 PM UTC 24
Finished Oct 14 11:49:02 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154294503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4154294503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.1377027704
Short name T91
Test name
Test status
Simulation time 326884604089 ps
CPU time 87.65 seconds
Started Oct 14 11:39:48 PM UTC 24
Finished Oct 14 11:41:17 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377027704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1377027704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2604946820
Short name T790
Test name
Test status
Simulation time 333537535012 ps
CPU time 884.3 seconds
Started Oct 14 11:39:54 PM UTC 24
Finished Oct 14 11:54:47 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604946820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2604946820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.2501265347
Short name T755
Test name
Test status
Simulation time 328756542814 ps
CPU time 199.58 seconds
Started Oct 14 11:39:33 PM UTC 24
Finished Oct 14 11:42:55 PM UTC 24
Peak memory 210396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501265347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2501265347
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.528809812
Short name T89
Test name
Test status
Simulation time 162626604612 ps
CPU time 85.34 seconds
Started Oct 14 11:39:44 PM UTC 24
Finished Oct 14 11:41:11 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528809812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.528809812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1304632062
Short name T764
Test name
Test status
Simulation time 588144625265 ps
CPU time 370.68 seconds
Started Oct 14 11:40:07 PM UTC 24
Finished Oct 14 11:46:22 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304632062 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.1304632062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.279772218
Short name T779
Test name
Test status
Simulation time 127205911264 ps
CPU time 578.83 seconds
Started Oct 14 11:40:49 PM UTC 24
Finished Oct 14 11:50:34 PM UTC 24
Peak memory 210684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279772218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.279772218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.1851533422
Short name T94
Test name
Test status
Simulation time 23973882820 ps
CPU time 61.22 seconds
Started Oct 14 11:40:32 PM UTC 24
Finished Oct 14 11:41:35 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851533422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1851533422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.3089493597
Short name T749
Test name
Test status
Simulation time 4380648416 ps
CPU time 19.17 seconds
Started Oct 14 11:40:27 PM UTC 24
Finished Oct 14 11:40:48 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089493597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3089493597
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.483428985
Short name T742
Test name
Test status
Simulation time 5983086292 ps
CPU time 13.88 seconds
Started Oct 14 11:39:28 PM UTC 24
Finished Oct 14 11:39:43 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483428985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.483428985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.3017378217
Short name T345
Test name
Test status
Simulation time 568829264785 ps
CPU time 708.54 seconds
Started Oct 14 11:40:57 PM UTC 24
Finished Oct 14 11:52:53 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017378217 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.3017378217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.175922468
Short name T87
Test name
Test status
Simulation time 5449004099 ps
CPU time 13.21 seconds
Started Oct 14 11:40:52 PM UTC 24
Finished Oct 14 11:41:06 PM UTC 24
Peak memory 220584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=175922468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
49.adc_ctrl_stress_all_with_rand_reset.175922468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.721388657
Short name T372
Test name
Test status
Simulation time 496802372 ps
CPU time 3.02 seconds
Started Oct 14 10:30:07 PM UTC 24
Finished Oct 14 10:30:11 PM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721388657 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.721388657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2577727342
Short name T252
Test name
Test status
Simulation time 388523982796 ps
CPU time 871.13 seconds
Started Oct 14 10:29:18 PM UTC 24
Finished Oct 14 10:43:58 PM UTC 24
Peak memory 213052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577727342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2577727342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.4093735422
Short name T155
Test name
Test status
Simulation time 332857586377 ps
CPU time 106.66 seconds
Started Oct 14 10:29:06 PM UTC 24
Finished Oct 14 10:30:55 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093735422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4093735422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1174721091
Short name T428
Test name
Test status
Simulation time 492049859975 ps
CPU time 1242.73 seconds
Started Oct 14 10:29:06 PM UTC 24
Finished Oct 14 10:50:01 PM UTC 24
Peak memory 212916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174721091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.1174721091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.22407959
Short name T183
Test name
Test status
Simulation time 164180887369 ps
CPU time 162.59 seconds
Started Oct 14 10:28:54 PM UTC 24
Finished Oct 14 10:31:39 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22407959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.22407959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.458272539
Short name T130
Test name
Test status
Simulation time 328623355988 ps
CPU time 200.44 seconds
Started Oct 14 10:29:04 PM UTC 24
Finished Oct 14 10:32:27 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458272539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.458272539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3088457299
Short name T384
Test name
Test status
Simulation time 203658319772 ps
CPU time 643 seconds
Started Oct 14 10:29:07 PM UTC 24
Finished Oct 14 10:39:57 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088457299 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.3088457299
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1412337342
Short name T223
Test name
Test status
Simulation time 128687622719 ps
CPU time 608.96 seconds
Started Oct 14 10:29:46 PM UTC 24
Finished Oct 14 10:40:01 PM UTC 24
Peak memory 210612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412337342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1412337342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2084868637
Short name T162
Test name
Test status
Simulation time 34559231725 ps
CPU time 85.48 seconds
Started Oct 14 10:29:44 PM UTC 24
Finished Oct 14 10:31:11 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084868637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2084868637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2588666069
Short name T212
Test name
Test status
Simulation time 4088459347 ps
CPU time 5.89 seconds
Started Oct 14 10:29:35 PM UTC 24
Finished Oct 14 10:29:42 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588666069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2588666069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.821359823
Short name T150
Test name
Test status
Simulation time 5794998090 ps
CPU time 23.66 seconds
Started Oct 14 10:28:53 PM UTC 24
Finished Oct 14 10:29:18 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821359823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.821359823
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.2128634578
Short name T166
Test name
Test status
Simulation time 390248520 ps
CPU time 2.52 seconds
Started Oct 14 10:31:26 PM UTC 24
Finished Oct 14 10:31:29 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128634578 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2128634578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3787633612
Short name T246
Test name
Test status
Simulation time 490502099121 ps
CPU time 1035.78 seconds
Started Oct 14 10:30:22 PM UTC 24
Finished Oct 14 10:47:48 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787633612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3787633612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.606833444
Short name T446
Test name
Test status
Simulation time 498656503942 ps
CPU time 1413.45 seconds
Started Oct 14 10:30:24 PM UTC 24
Finished Oct 14 10:54:10 PM UTC 24
Peak memory 213000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606833444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.606833444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.4121844081
Short name T132
Test name
Test status
Simulation time 165693472996 ps
CPU time 140.04 seconds
Started Oct 14 10:30:12 PM UTC 24
Finished Oct 14 10:32:35 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121844081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4121844081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1711320353
Short name T395
Test name
Test status
Simulation time 326280694213 ps
CPU time 729.9 seconds
Started Oct 14 10:30:15 PM UTC 24
Finished Oct 14 10:42:32 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711320353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.1711320353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2604714673
Short name T129
Test name
Test status
Simulation time 181999794258 ps
CPU time 111.77 seconds
Started Oct 14 10:30:29 PM UTC 24
Finished Oct 14 10:32:22 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604714673 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2604714673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.14769468
Short name T442
Test name
Test status
Simulation time 395143895381 ps
CPU time 1304.96 seconds
Started Oct 14 10:30:54 PM UTC 24
Finished Oct 14 10:52:52 PM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14769468 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.14769468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2503371311
Short name T205
Test name
Test status
Simulation time 138470839568 ps
CPU time 1010.9 seconds
Started Oct 14 10:31:22 PM UTC 24
Finished Oct 14 10:48:23 PM UTC 24
Peak memory 213068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503371311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2503371311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.1842829664
Short name T182
Test name
Test status
Simulation time 39591449828 ps
CPU time 24.95 seconds
Started Oct 14 10:31:11 PM UTC 24
Finished Oct 14 10:31:37 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842829664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1842829664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.614807479
Short name T163
Test name
Test status
Simulation time 2915346955 ps
CPU time 14.05 seconds
Started Oct 14 10:31:06 PM UTC 24
Finished Oct 14 10:31:21 PM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614807479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.614807479
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1397059512
Short name T373
Test name
Test status
Simulation time 5973376506 ps
CPU time 10.19 seconds
Started Oct 14 10:30:11 PM UTC 24
Finished Oct 14 10:30:23 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397059512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1397059512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3382517496
Short name T243
Test name
Test status
Simulation time 189765866543 ps
CPU time 143.76 seconds
Started Oct 14 10:31:25 PM UTC 24
Finished Oct 14 10:33:51 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382517496 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.3382517496
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.736440842
Short name T133
Test name
Test status
Simulation time 282532949 ps
CPU time 1.91 seconds
Started Oct 14 10:32:36 PM UTC 24
Finished Oct 14 10:32:39 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736440842 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.736440842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.2584369301
Short name T174
Test name
Test status
Simulation time 366379425954 ps
CPU time 980.95 seconds
Started Oct 14 10:31:56 PM UTC 24
Finished Oct 14 10:48:26 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584369301 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.2584369301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1016124544
Short name T118
Test name
Test status
Simulation time 173925043295 ps
CPU time 46.76 seconds
Started Oct 14 10:31:58 PM UTC 24
Finished Oct 14 10:32:47 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016124544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1016124544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.4263532241
Short name T244
Test name
Test status
Simulation time 173309370464 ps
CPU time 252.43 seconds
Started Oct 14 10:31:32 PM UTC 24
Finished Oct 14 10:35:47 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263532241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4263532241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2329388554
Short name T390
Test name
Test status
Simulation time 163361731390 ps
CPU time 591.6 seconds
Started Oct 14 10:31:38 PM UTC 24
Finished Oct 14 10:41:36 PM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329388554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.2329388554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.4147642682
Short name T144
Test name
Test status
Simulation time 319589047342 ps
CPU time 694.47 seconds
Started Oct 14 10:31:32 PM UTC 24
Finished Oct 14 10:43:13 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147642682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4147642682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.1939116475
Short name T195
Test name
Test status
Simulation time 495603516723 ps
CPU time 396.16 seconds
Started Oct 14 10:31:32 PM UTC 24
Finished Oct 14 10:38:13 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939116475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.1939116475
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.942857248
Short name T197
Test name
Test status
Simulation time 361016568703 ps
CPU time 422.31 seconds
Started Oct 14 10:31:40 PM UTC 24
Finished Oct 14 10:38:47 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942857248 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.942857248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3948051829
Short name T209
Test name
Test status
Simulation time 410288694289 ps
CPU time 1017.32 seconds
Started Oct 14 10:31:42 PM UTC 24
Finished Oct 14 10:48:49 PM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948051829 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.3948051829
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.1628197081
Short name T49
Test name
Test status
Simulation time 125166168574 ps
CPU time 496.32 seconds
Started Oct 14 10:32:28 PM UTC 24
Finished Oct 14 10:40:49 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628197081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1628197081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.546335785
Short name T135
Test name
Test status
Simulation time 31274938898 ps
CPU time 19.86 seconds
Started Oct 14 10:32:23 PM UTC 24
Finished Oct 14 10:32:45 PM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546335785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.546335785
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.1204840151
Short name T131
Test name
Test status
Simulation time 4791743319 ps
CPU time 7.43 seconds
Started Oct 14 10:32:19 PM UTC 24
Finished Oct 14 10:32:28 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204840151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1204840151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.91495168
Short name T184
Test name
Test status
Simulation time 6067503882 ps
CPU time 26.21 seconds
Started Oct 14 10:31:30 PM UTC 24
Finished Oct 14 10:31:57 PM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91495168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.91495168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1572255579
Short name T85
Test name
Test status
Simulation time 540471219 ps
CPU time 1.09 seconds
Started Oct 14 10:33:46 PM UTC 24
Finished Oct 14 10:33:48 PM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572255579 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1572255579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.2167409070
Short name T251
Test name
Test status
Simulation time 163735527892 ps
CPU time 250.41 seconds
Started Oct 14 10:33:11 PM UTC 24
Finished Oct 14 10:37:25 PM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167409070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2167409070
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3827430684
Short name T128
Test name
Test status
Simulation time 336121575391 ps
CPU time 880.31 seconds
Started Oct 14 10:32:47 PM UTC 24
Finished Oct 14 10:47:36 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827430684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3827430684
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1781579991
Short name T452
Test name
Test status
Simulation time 495959796169 ps
CPU time 1353.71 seconds
Started Oct 14 10:32:49 PM UTC 24
Finished Oct 14 10:55:36 PM UTC 24
Peak memory 212852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781579991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.1781579991
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1766745176
Short name T81
Test name
Test status
Simulation time 166236443659 ps
CPU time 30.71 seconds
Started Oct 14 10:32:42 PM UTC 24
Finished Oct 14 10:33:14 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766745176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1766745176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3097705091
Short name T445
Test name
Test status
Simulation time 492195946831 ps
CPU time 1267.03 seconds
Started Oct 14 10:32:45 PM UTC 24
Finished Oct 14 10:54:04 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097705091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.3097705091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3079368712
Short name T478
Test name
Test status
Simulation time 604267751760 ps
CPU time 1671.73 seconds
Started Oct 14 10:32:57 PM UTC 24
Finished Oct 14 11:01:05 PM UTC 24
Peak memory 212696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079368712 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.3079368712
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.532287174
Short name T200
Test name
Test status
Simulation time 88622757827 ps
CPU time 356.7 seconds
Started Oct 14 10:33:27 PM UTC 24
Finished Oct 14 10:39:27 PM UTC 24
Peak memory 210684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532287174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.532287174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3723854564
Short name T84
Test name
Test status
Simulation time 24165984446 ps
CPU time 14.91 seconds
Started Oct 14 10:33:25 PM UTC 24
Finished Oct 14 10:33:41 PM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723854564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3723854564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.2827210820
Short name T83
Test name
Test status
Simulation time 4698591761 ps
CPU time 10.36 seconds
Started Oct 14 10:33:15 PM UTC 24
Finished Oct 14 10:33:26 PM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827210820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2827210820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.4153960918
Short name T136
Test name
Test status
Simulation time 5577343849 ps
CPU time 13.48 seconds
Started Oct 14 10:32:40 PM UTC 24
Finished Oct 14 10:32:54 PM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153960918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4153960918
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3125018550
Short name T152
Test name
Test status
Simulation time 377043289796 ps
CPU time 274.16 seconds
Started Oct 14 10:33:42 PM UTC 24
Finished Oct 14 10:38:19 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125018550 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.3125018550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1912185402
Short name T28
Test name
Test status
Simulation time 1443228250 ps
CPU time 10.47 seconds
Started Oct 14 10:33:39 PM UTC 24
Finished Oct 14 10:33:51 PM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1912185402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.adc_ctrl_stress_all_with_rand_reset.1912185402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3384393702
Short name T377
Test name
Test status
Simulation time 443486660 ps
CPU time 1.1 seconds
Started Oct 14 10:36:15 PM UTC 24
Finished Oct 14 10:36:17 PM UTC 24
Peak memory 208940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384393702 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3384393702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3554843600
Short name T139
Test name
Test status
Simulation time 169771033850 ps
CPU time 147.1 seconds
Started Oct 14 10:33:51 PM UTC 24
Finished Oct 14 10:36:21 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554843600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3554843600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2310028769
Short name T422
Test name
Test status
Simulation time 332647081178 ps
CPU time 834.93 seconds
Started Oct 14 10:34:14 PM UTC 24
Finished Oct 14 10:48:18 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310028769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.2310028769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3883179314
Short name T256
Test name
Test status
Simulation time 167750584680 ps
CPU time 441.74 seconds
Started Oct 14 10:33:51 PM UTC 24
Finished Oct 14 10:41:18 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883179314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3883179314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1659258371
Short name T389
Test name
Test status
Simulation time 164788480127 ps
CPU time 444.97 seconds
Started Oct 14 10:33:51 PM UTC 24
Finished Oct 14 10:41:21 PM UTC 24
Peak memory 210044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659258371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.1659258371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2227063919
Short name T147
Test name
Test status
Simulation time 194677305455 ps
CPU time 748.67 seconds
Started Oct 14 10:34:23 PM UTC 24
Finished Oct 14 10:47:00 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227063919 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.2227063919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2939730207
Short name T410
Test name
Test status
Simulation time 411936358232 ps
CPU time 728.6 seconds
Started Oct 14 10:34:30 PM UTC 24
Finished Oct 14 10:46:46 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939730207 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.2939730207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1740234126
Short name T222
Test name
Test status
Simulation time 63624327663 ps
CPU time 370.81 seconds
Started Oct 14 10:35:53 PM UTC 24
Finished Oct 14 10:42:09 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740234126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1740234126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1084880930
Short name T378
Test name
Test status
Simulation time 25962475525 ps
CPU time 24.91 seconds
Started Oct 14 10:35:51 PM UTC 24
Finished Oct 14 10:36:17 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084880930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1084880930
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3341011676
Short name T376
Test name
Test status
Simulation time 5214061766 ps
CPU time 3.26 seconds
Started Oct 14 10:35:48 PM UTC 24
Finished Oct 14 10:35:53 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341011676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3341011676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2739773678
Short name T374
Test name
Test status
Simulation time 5837927298 ps
CPU time 23.65 seconds
Started Oct 14 10:33:49 PM UTC 24
Finished Oct 14 10:34:14 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739773678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2739773678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.561861462
Short name T29
Test name
Test status
Simulation time 7101006722 ps
CPU time 16.74 seconds
Started Oct 14 10:35:56 PM UTC 24
Finished Oct 14 10:36:14 PM UTC 24
Peak memory 220644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=561861462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.adc_ctrl_stress_all_with_rand_reset.561861462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest
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