| T613 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1936132847 |
|
|
Feb 08 11:00:25 AM UTC 25 |
Feb 08 11:15:38 AM UTC 25 |
333935264721 ps |
| T304 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3603065058 |
|
|
Feb 08 11:08:50 AM UTC 25 |
Feb 08 11:15:47 AM UTC 25 |
223261289078 ps |
| T614 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.4128910961 |
|
|
Feb 08 11:14:44 AM UTC 25 |
Feb 08 11:15:56 AM UTC 25 |
178573278376 ps |
| T615 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.2466828407 |
|
|
Feb 08 11:01:07 AM UTC 25 |
Feb 08 11:16:03 AM UTC 25 |
324612231154 ps |
| T313 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.3690637180 |
|
|
Feb 08 11:11:34 AM UTC 25 |
Feb 08 11:16:04 AM UTC 25 |
554474620710 ps |
| T616 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.1264571352 |
|
|
Feb 08 11:16:03 AM UTC 25 |
Feb 08 11:16:08 AM UTC 25 |
4317984187 ps |
| T301 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.915950540 |
|
|
Feb 08 11:13:52 AM UTC 25 |
Feb 08 11:16:11 AM UTC 25 |
197029392626 ps |
| T617 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.343236395 |
|
|
Feb 08 11:02:01 AM UTC 25 |
Feb 08 11:16:31 AM UTC 25 |
350671612423 ps |
| T179 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.4212649473 |
|
|
Feb 08 11:13:23 AM UTC 25 |
Feb 08 11:16:48 AM UTC 25 |
425042360950 ps |
| T618 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3595316027 |
|
|
Feb 08 11:14:27 AM UTC 25 |
Feb 08 11:16:52 AM UTC 25 |
162049868485 ps |
| T619 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.3648884604 |
|
|
Feb 08 11:16:49 AM UTC 25 |
Feb 08 11:16:53 AM UTC 25 |
345565434 ps |
| T620 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.134921537 |
|
|
Feb 08 11:15:10 AM UTC 25 |
Feb 08 11:16:55 AM UTC 25 |
33654776152 ps |
| T36 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.262936094 |
|
|
Feb 08 11:12:17 AM UTC 25 |
Feb 08 11:16:58 AM UTC 25 |
431096131415 ps |
| T621 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.2354924171 |
|
|
Feb 08 11:02:23 AM UTC 25 |
Feb 08 11:17:03 AM UTC 25 |
334716040426 ps |
| T622 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.2762530573 |
|
|
Feb 08 11:14:11 AM UTC 25 |
Feb 08 11:17:09 AM UTC 25 |
167081547437 ps |
| T623 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3875514545 |
|
|
Feb 08 11:14:37 AM UTC 25 |
Feb 08 11:17:10 AM UTC 25 |
211070241030 ps |
| T624 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2793182252 |
|
|
Feb 08 10:55:47 AM UTC 25 |
Feb 08 11:17:13 AM UTC 25 |
494710581398 ps |
| T625 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.70903345 |
|
|
Feb 08 11:07:13 AM UTC 25 |
Feb 08 11:17:19 AM UTC 25 |
79800077037 ps |
| T626 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.973804983 |
|
|
Feb 08 10:50:12 AM UTC 25 |
Feb 08 11:17:22 AM UTC 25 |
491752475105 ps |
| T627 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1606590861 |
|
|
Feb 08 11:16:53 AM UTC 25 |
Feb 08 11:17:24 AM UTC 25 |
5921290647 ps |
| T628 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.2353718693 |
|
|
Feb 08 11:17:23 AM UTC 25 |
Feb 08 11:17:37 AM UTC 25 |
4573189511 ps |
| T280 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.673710532 |
|
|
Feb 08 11:13:08 AM UTC 25 |
Feb 08 11:17:39 AM UTC 25 |
323706576308 ps |
| T629 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1010371803 |
|
|
Feb 08 11:11:32 AM UTC 25 |
Feb 08 11:17:40 AM UTC 25 |
584699323284 ps |
| T276 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3714727265 |
|
|
Feb 08 10:58:55 AM UTC 25 |
Feb 08 11:17:44 AM UTC 25 |
370408437403 ps |
| T630 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2829366911 |
|
|
Feb 08 11:09:58 AM UTC 25 |
Feb 08 11:17:47 AM UTC 25 |
610001097576 ps |
| T631 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.3477879663 |
|
|
Feb 08 11:17:45 AM UTC 25 |
Feb 08 11:17:47 AM UTC 25 |
559089504 ps |
| T632 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.1173008165 |
|
|
Feb 08 11:17:48 AM UTC 25 |
Feb 08 11:18:07 AM UTC 25 |
5787919912 ps |
| T349 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.987152022 |
|
|
Feb 08 11:11:04 AM UTC 25 |
Feb 08 11:18:08 AM UTC 25 |
326720451981 ps |
| T633 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.2328209352 |
|
|
Feb 08 11:15:56 AM UTC 25 |
Feb 08 11:18:08 AM UTC 25 |
162251865973 ps |
| T65 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.554048468 |
|
|
Feb 08 11:07:14 AM UTC 25 |
Feb 08 11:18:18 AM UTC 25 |
485558418477 ps |
| T634 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3038302334 |
|
|
Feb 08 11:08:04 AM UTC 25 |
Feb 08 11:18:26 AM UTC 25 |
398445470412 ps |
| T635 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.1973500978 |
|
|
Feb 08 11:16:05 AM UTC 25 |
Feb 08 11:18:38 AM UTC 25 |
38300275570 ps |
| T636 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1969722855 |
|
|
Feb 08 11:17:04 AM UTC 25 |
Feb 08 11:18:44 AM UTC 25 |
166712611188 ps |
| T637 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.3477715512 |
|
|
Feb 08 11:14:07 AM UTC 25 |
Feb 08 11:19:14 AM UTC 25 |
325857881334 ps |
| T638 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.4004156102 |
|
|
Feb 08 11:11:18 AM UTC 25 |
Feb 08 11:19:19 AM UTC 25 |
161658638713 ps |
| T37 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.901534746 |
|
|
Feb 08 11:13:51 AM UTC 25 |
Feb 08 11:19:24 AM UTC 25 |
93671073571 ps |
| T639 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.2199323639 |
|
|
Feb 08 11:10:43 AM UTC 25 |
Feb 08 11:19:25 AM UTC 25 |
166355339804 ps |
| T640 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.3078291768 |
|
|
Feb 08 11:17:24 AM UTC 25 |
Feb 08 11:19:26 AM UTC 25 |
27352913916 ps |
| T329 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.3633420832 |
|
|
Feb 08 11:13:38 AM UTC 25 |
Feb 08 11:19:28 AM UTC 25 |
345061481013 ps |
| T641 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.2351457078 |
|
|
Feb 08 11:19:29 AM UTC 25 |
Feb 08 11:19:33 AM UTC 25 |
350265404 ps |
| T642 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2947153614 |
|
|
Feb 08 11:19:15 AM UTC 25 |
Feb 08 11:19:37 AM UTC 25 |
4464744206 ps |
| T643 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.4059166818 |
|
|
Feb 08 11:19:34 AM UTC 25 |
Feb 08 11:19:50 AM UTC 25 |
6037103512 ps |
| T644 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3971447392 |
|
|
Feb 08 11:18:09 AM UTC 25 |
Feb 08 11:19:55 AM UTC 25 |
159039538202 ps |
| T272 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2867659249 |
|
|
Feb 08 11:07:52 AM UTC 25 |
Feb 08 11:19:56 AM UTC 25 |
537674719174 ps |
| T645 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.837696417 |
|
|
Feb 08 11:07:40 AM UTC 25 |
Feb 08 11:20:09 AM UTC 25 |
499032310920 ps |
| T308 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3952948230 |
|
|
Feb 08 11:17:19 AM UTC 25 |
Feb 08 11:20:20 AM UTC 25 |
163318810722 ps |
| T646 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.2759531356 |
|
|
Feb 08 11:12:58 AM UTC 25 |
Feb 08 11:20:46 AM UTC 25 |
329043185545 ps |
| T292 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.712164043 |
|
|
Feb 08 11:14:38 AM UTC 25 |
Feb 08 11:20:53 AM UTC 25 |
490775687536 ps |
| T647 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.2168210376 |
|
|
Feb 08 11:18:08 AM UTC 25 |
Feb 08 11:21:09 AM UTC 25 |
328212760753 ps |
| T648 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3673169336 |
|
|
Feb 08 11:19:19 AM UTC 25 |
Feb 08 11:21:14 AM UTC 25 |
26646985971 ps |
| T649 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.2715358454 |
|
|
Feb 08 11:21:09 AM UTC 25 |
Feb 08 11:21:26 AM UTC 25 |
3473994761 ps |
| T214 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.2552887304 |
|
|
Feb 08 11:08:50 AM UTC 25 |
Feb 08 11:21:28 AM UTC 25 |
117042374126 ps |
| T650 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2850691368 |
|
|
Feb 08 11:13:10 AM UTC 25 |
Feb 08 11:21:28 AM UTC 25 |
163353117321 ps |
| T334 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.2659015116 |
|
|
Feb 08 11:08:25 AM UTC 25 |
Feb 08 11:21:37 AM UTC 25 |
547659414092 ps |
| T651 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.614813049 |
|
|
Feb 08 11:21:38 AM UTC 25 |
Feb 08 11:21:42 AM UTC 25 |
367762683 ps |
| T652 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3814552049 |
|
|
Feb 08 11:13:46 AM UTC 25 |
Feb 08 11:21:42 AM UTC 25 |
76163813982 ps |
| T653 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.3112369331 |
|
|
Feb 08 11:21:14 AM UTC 25 |
Feb 08 11:21:45 AM UTC 25 |
26609202969 ps |
| T654 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.1451636562 |
|
|
Feb 08 11:03:49 AM UTC 25 |
Feb 08 11:22:02 AM UTC 25 |
325513629765 ps |
| T204 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.66694086 |
|
|
Feb 08 11:16:12 AM UTC 25 |
Feb 08 11:22:08 AM UTC 25 |
101470893921 ps |
| T180 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.2928893609 |
|
|
Feb 08 11:16:58 AM UTC 25 |
Feb 08 11:22:09 AM UTC 25 |
486363463593 ps |
| T655 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.1940196201 |
|
|
Feb 08 11:21:43 AM UTC 25 |
Feb 08 11:22:11 AM UTC 25 |
5546672466 ps |
| T316 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2011837052 |
|
|
Feb 08 11:15:48 AM UTC 25 |
Feb 08 11:22:12 AM UTC 25 |
162031894520 ps |
| T656 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.1729632451 |
|
|
Feb 08 10:55:50 AM UTC 25 |
Feb 08 11:22:29 AM UTC 25 |
490911207191 ps |
| T66 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.2839132142 |
|
|
Feb 08 11:12:30 AM UTC 25 |
Feb 08 11:22:29 AM UTC 25 |
528706239872 ps |
| T657 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.831249295 |
|
|
Feb 08 11:22:30 AM UTC 25 |
Feb 08 11:22:37 AM UTC 25 |
4305762305 ps |
| T284 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.904392256 |
|
|
Feb 08 11:17:40 AM UTC 25 |
Feb 08 11:22:49 AM UTC 25 |
150475412798 ps |
| T658 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3507146413 |
|
|
Feb 08 11:17:37 AM UTC 25 |
Feb 08 11:22:59 AM UTC 25 |
75380756615 ps |
| T345 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.2420232179 |
|
|
Feb 08 11:03:51 AM UTC 25 |
Feb 08 11:23:04 AM UTC 25 |
489828700685 ps |
| T261 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1762936993 |
|
|
Feb 08 11:19:26 AM UTC 25 |
Feb 08 11:23:06 AM UTC 25 |
104334822080 ps |
| T347 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2594992836 |
|
|
Feb 08 11:18:45 AM UTC 25 |
Feb 08 11:23:08 AM UTC 25 |
331936389308 ps |
| T659 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.1883366360 |
|
|
Feb 08 11:23:07 AM UTC 25 |
Feb 08 11:23:10 AM UTC 25 |
279449679 ps |
| T660 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1632975710 |
|
|
Feb 08 11:18:27 AM UTC 25 |
Feb 08 11:23:17 AM UTC 25 |
404248829469 ps |
| T661 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.737138879 |
|
|
Feb 08 11:23:09 AM UTC 25 |
Feb 08 11:23:18 AM UTC 25 |
5884618519 ps |
| T662 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1130789074 |
|
|
Feb 08 11:15:31 AM UTC 25 |
Feb 08 11:23:22 AM UTC 25 |
162224708556 ps |
| T663 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2400806677 |
|
|
Feb 08 11:19:51 AM UTC 25 |
Feb 08 11:23:27 AM UTC 25 |
328962424719 ps |
| T664 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.2742652576 |
|
|
Feb 08 11:22:38 AM UTC 25 |
Feb 08 11:23:28 AM UTC 25 |
43739926641 ps |
| T665 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.353365283 |
|
|
Feb 08 11:23:06 AM UTC 25 |
Feb 08 11:23:31 AM UTC 25 |
9609374474 ps |
| T666 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.644640879 |
|
|
Feb 08 11:10:40 AM UTC 25 |
Feb 08 11:23:32 AM UTC 25 |
112397541787 ps |
| T667 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.1845340298 |
|
|
Feb 08 11:18:19 AM UTC 25 |
Feb 08 11:23:37 AM UTC 25 |
169053140865 ps |
| T668 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1438500519 |
|
|
Feb 08 11:15:29 AM UTC 25 |
Feb 08 11:23:38 AM UTC 25 |
322256407529 ps |
| T669 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.1061721680 |
|
|
Feb 08 11:23:37 AM UTC 25 |
Feb 08 11:23:42 AM UTC 25 |
2975134521 ps |
| T361 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3803408614 |
|
|
Feb 08 11:16:09 AM UTC 25 |
Feb 08 11:23:54 AM UTC 25 |
104197674792 ps |
| T670 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.815266350 |
|
|
Feb 08 11:21:43 AM UTC 25 |
Feb 08 11:24:02 AM UTC 25 |
328838556716 ps |
| T266 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.1125157596 |
|
|
Feb 08 11:17:48 AM UTC 25 |
Feb 08 11:24:20 AM UTC 25 |
164087401069 ps |
| T671 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.865877909 |
|
|
Feb 08 11:24:21 AM UTC 25 |
Feb 08 11:24:24 AM UTC 25 |
437904747 ps |
| T232 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2326832673 |
|
|
Feb 08 11:16:54 AM UTC 25 |
Feb 08 11:24:33 AM UTC 25 |
160709674444 ps |
| T305 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3831093125 |
|
|
Feb 08 11:22:13 AM UTC 25 |
Feb 08 11:24:35 AM UTC 25 |
347230047001 ps |
| T672 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.3143119416 |
|
|
Feb 08 11:24:25 AM UTC 25 |
Feb 08 11:24:41 AM UTC 25 |
6004278601 ps |
| T673 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.4152997378 |
|
|
Feb 08 11:22:03 AM UTC 25 |
Feb 08 11:24:56 AM UTC 25 |
165407953398 ps |
| T674 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.647038753 |
|
|
Feb 08 11:15:31 AM UTC 25 |
Feb 08 11:25:03 AM UTC 25 |
167152330908 ps |
| T675 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.3045903334 |
|
|
Feb 08 11:23:19 AM UTC 25 |
Feb 08 11:25:07 AM UTC 25 |
322803818283 ps |
| T676 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.4249716552 |
|
|
Feb 08 10:57:13 AM UTC 25 |
Feb 08 11:25:11 AM UTC 25 |
486970191905 ps |
| T677 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.4148704838 |
|
|
Feb 08 11:21:46 AM UTC 25 |
Feb 08 11:25:21 AM UTC 25 |
322069525452 ps |
| T678 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.570745141 |
|
|
Feb 08 11:23:11 AM UTC 25 |
Feb 08 11:26:04 AM UTC 25 |
163139705182 ps |
| T679 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2502631005 |
|
|
Feb 08 11:16:56 AM UTC 25 |
Feb 08 11:26:06 AM UTC 25 |
166898393855 ps |
| T680 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3855897186 |
|
|
Feb 08 11:23:39 AM UTC 25 |
Feb 08 11:26:13 AM UTC 25 |
34134198835 ps |
| T681 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2809968821 |
|
|
Feb 08 11:20:20 AM UTC 25 |
Feb 08 11:26:15 AM UTC 25 |
200968284106 ps |
| T682 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.426227692 |
|
|
Feb 08 11:26:05 AM UTC 25 |
Feb 08 11:26:20 AM UTC 25 |
2931281862 ps |
| T683 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.1289886879 |
|
|
Feb 08 11:15:37 AM UTC 25 |
Feb 08 11:26:28 AM UTC 25 |
556753308021 ps |
| T684 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2903910185 |
|
|
Feb 08 11:26:30 AM UTC 25 |
Feb 08 11:26:33 AM UTC 25 |
467031989 ps |
| T685 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2524387547 |
|
|
Feb 08 11:26:07 AM UTC 25 |
Feb 08 11:26:38 AM UTC 25 |
24094563007 ps |
| T686 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4166821041 |
|
|
Feb 08 11:13:28 AM UTC 25 |
Feb 08 11:26:40 AM UTC 25 |
406175639468 ps |
| T282 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.605254082 |
|
|
Feb 08 11:06:50 AM UTC 25 |
Feb 08 11:26:51 AM UTC 25 |
373484025214 ps |
| T687 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3434050075 |
|
|
Feb 08 11:26:34 AM UTC 25 |
Feb 08 11:26:59 AM UTC 25 |
5604991181 ps |
| T336 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3314882274 |
|
|
Feb 08 11:13:32 AM UTC 25 |
Feb 08 11:27:03 AM UTC 25 |
327658458052 ps |
| T688 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.1330078815 |
|
|
Feb 08 11:12:14 AM UTC 25 |
Feb 08 11:27:10 AM UTC 25 |
107344792073 ps |
| T689 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.1648229765 |
|
|
Feb 08 11:23:18 AM UTC 25 |
Feb 08 11:27:31 AM UTC 25 |
315706680025 ps |
| T690 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3623976489 |
|
|
Feb 08 11:26:16 AM UTC 25 |
Feb 08 11:27:32 AM UTC 25 |
25563702487 ps |
| T350 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.3890421995 |
|
|
Feb 08 11:25:12 AM UTC 25 |
Feb 08 11:27:34 AM UTC 25 |
340652595123 ps |
| T332 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.138917955 |
|
|
Feb 08 11:23:33 AM UTC 25 |
Feb 08 11:27:38 AM UTC 25 |
371099538271 ps |
| T691 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.4085048911 |
|
|
Feb 08 11:17:10 AM UTC 25 |
Feb 08 11:27:42 AM UTC 25 |
546814254963 ps |
| T692 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1177570598 |
|
|
Feb 08 11:27:38 AM UTC 25 |
Feb 08 11:27:49 AM UTC 25 |
25244330862 ps |
| T693 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.462408820 |
|
|
Feb 08 11:27:35 AM UTC 25 |
Feb 08 11:27:52 AM UTC 25 |
5245193593 ps |
| T200 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1926895884 |
|
|
Feb 08 11:23:32 AM UTC 25 |
Feb 08 11:28:07 AM UTC 25 |
507884633248 ps |
| T694 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.97769981 |
|
|
Feb 08 11:28:07 AM UTC 25 |
Feb 08 11:28:10 AM UTC 25 |
475113837 ps |
| T695 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1970508858 |
|
|
Feb 08 11:15:38 AM UTC 25 |
Feb 08 11:28:20 AM UTC 25 |
588280636717 ps |
| T696 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.342645766 |
|
|
Feb 08 11:19:25 AM UTC 25 |
Feb 08 11:28:23 AM UTC 25 |
87972710759 ps |
| T697 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.1642282027 |
|
|
Feb 08 11:15:20 AM UTC 25 |
Feb 08 11:28:26 AM UTC 25 |
189856774761 ps |
| T698 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.2215485431 |
|
|
Feb 08 11:26:41 AM UTC 25 |
Feb 08 11:28:30 AM UTC 25 |
321099820790 ps |
| T699 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.2738378041 |
|
|
Feb 08 11:28:12 AM UTC 25 |
Feb 08 11:28:34 AM UTC 25 |
5960424542 ps |
| T700 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1043825437 |
|
|
Feb 08 11:23:54 AM UTC 25 |
Feb 08 11:28:40 AM UTC 25 |
99993359849 ps |
| T701 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4120336241 |
|
|
Feb 08 11:23:00 AM UTC 25 |
Feb 08 11:28:41 AM UTC 25 |
1190696419321 ps |
| T702 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1262867403 |
|
|
Feb 08 11:27:00 AM UTC 25 |
Feb 08 11:28:45 AM UTC 25 |
171136112608 ps |
| T277 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3145735031 |
|
|
Feb 08 11:23:28 AM UTC 25 |
Feb 08 11:28:52 AM UTC 25 |
357217193704 ps |
| T344 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1191698892 |
|
|
Feb 08 11:20:09 AM UTC 25 |
Feb 08 11:28:55 AM UTC 25 |
173511089964 ps |
| T338 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.4265908206 |
|
|
Feb 08 11:20:54 AM UTC 25 |
Feb 08 11:29:14 AM UTC 25 |
170197570719 ps |
| T703 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.942928432 |
|
|
Feb 08 10:58:50 AM UTC 25 |
Feb 08 11:29:15 AM UTC 25 |
600352131341 ps |
| T704 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.2231552632 |
|
|
Feb 08 11:28:53 AM UTC 25 |
Feb 08 11:29:20 AM UTC 25 |
5322091586 ps |
| T705 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2649517942 |
|
|
Feb 08 11:28:56 AM UTC 25 |
Feb 08 11:29:23 AM UTC 25 |
37084533467 ps |
| T315 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.1192100474 |
|
|
Feb 08 11:03:29 AM UTC 25 |
Feb 08 11:29:25 AM UTC 25 |
561661739085 ps |
| T325 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1424111199 |
|
|
Feb 08 11:25:22 AM UTC 25 |
Feb 08 11:29:25 AM UTC 25 |
349987007801 ps |
| T706 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.2799036048 |
|
|
Feb 08 11:29:23 AM UTC 25 |
Feb 08 11:29:26 AM UTC 25 |
544505092 ps |
| T339 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3394218250 |
|
|
Feb 08 11:27:04 AM UTC 25 |
Feb 08 11:29:27 AM UTC 25 |
215195594759 ps |
| T707 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.1448551423 |
|
|
Feb 08 11:15:05 AM UTC 25 |
Feb 08 11:29:31 AM UTC 25 |
123512417449 ps |
| T708 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3065966982 |
|
|
Feb 08 11:17:14 AM UTC 25 |
Feb 08 11:29:38 AM UTC 25 |
185075143005 ps |
| T709 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1881638470 |
|
|
Feb 08 11:15:28 AM UTC 25 |
Feb 08 11:29:39 AM UTC 25 |
503518903301 ps |
| T710 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.1342359454 |
|
|
Feb 08 11:29:25 AM UTC 25 |
Feb 08 11:29:43 AM UTC 25 |
6012237412 ps |
| T711 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2239944132 |
|
|
Feb 08 11:18:09 AM UTC 25 |
Feb 08 11:29:47 AM UTC 25 |
487197546075 ps |
| T712 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3149178142 |
|
|
Feb 08 11:21:29 AM UTC 25 |
Feb 08 11:29:48 AM UTC 25 |
109786490938 ps |
| T713 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1226872006 |
|
|
Feb 08 11:24:36 AM UTC 25 |
Feb 08 11:29:49 AM UTC 25 |
484398912105 ps |
| T343 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1299225688 |
|
|
Feb 08 11:20:46 AM UTC 25 |
Feb 08 11:29:50 AM UTC 25 |
378059823630 ps |
| T283 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2237475592 |
|
|
Feb 08 11:29:16 AM UTC 25 |
Feb 08 11:29:50 AM UTC 25 |
71168941238 ps |
| T714 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3064720484 |
|
|
Feb 08 11:11:28 AM UTC 25 |
Feb 08 11:29:56 AM UTC 25 |
374220814880 ps |
| T715 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.2778925487 |
|
|
Feb 08 11:24:34 AM UTC 25 |
Feb 08 11:29:59 AM UTC 25 |
332605582811 ps |
| T716 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.4036918565 |
|
|
Feb 08 11:29:49 AM UTC 25 |
Feb 08 11:30:00 AM UTC 25 |
4269947643 ps |
| T717 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1560606919 |
|
|
Feb 08 11:29:59 AM UTC 25 |
Feb 08 11:30:04 AM UTC 25 |
457764808 ps |
| T320 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.2784885436 |
|
|
Feb 08 11:24:42 AM UTC 25 |
Feb 08 11:30:16 AM UTC 25 |
336686228106 ps |
| T718 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.3736026374 |
|
|
Feb 08 11:30:00 AM UTC 25 |
Feb 08 11:30:17 AM UTC 25 |
5912529734 ps |
| T719 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.827785040 |
|
|
Feb 08 11:29:57 AM UTC 25 |
Feb 08 11:30:24 AM UTC 25 |
6117162341 ps |
| T181 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.4080774469 |
|
|
Feb 08 11:29:44 AM UTC 25 |
Feb 08 11:30:25 AM UTC 25 |
171730489360 ps |
| T720 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3730957409 |
|
|
Feb 08 11:21:28 AM UTC 25 |
Feb 08 11:30:29 AM UTC 25 |
78465134395 ps |
| T721 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.525898171 |
|
|
Feb 08 11:29:50 AM UTC 25 |
Feb 08 11:30:37 AM UTC 25 |
40125804095 ps |
| T722 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.3614886621 |
|
|
Feb 08 11:09:50 AM UTC 25 |
Feb 08 11:30:42 AM UTC 25 |
411337772895 ps |
| T723 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3838200491 |
|
|
Feb 08 11:29:51 AM UTC 25 |
Feb 08 11:30:49 AM UTC 25 |
51905438952 ps |
| T724 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3296827269 |
|
|
Feb 08 11:29:32 AM UTC 25 |
Feb 08 11:30:52 AM UTC 25 |
320663780700 ps |
| T725 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.3538677739 |
|
|
Feb 08 11:18:38 AM UTC 25 |
Feb 08 11:30:55 AM UTC 25 |
340313450733 ps |
| T726 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.2805406949 |
|
|
Feb 08 11:22:29 AM UTC 25 |
Feb 08 11:30:59 AM UTC 25 |
179533102099 ps |
| T727 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.465198595 |
|
|
Feb 08 11:30:50 AM UTC 25 |
Feb 08 11:31:06 AM UTC 25 |
4179428104 ps |
| T728 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.1455505763 |
|
|
Feb 08 11:30:53 AM UTC 25 |
Feb 08 11:31:15 AM UTC 25 |
25929542337 ps |
| T729 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.1499346858 |
|
|
Feb 08 11:31:16 AM UTC 25 |
Feb 08 11:31:20 AM UTC 25 |
355795567 ps |
| T730 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.3359299108 |
|
|
Feb 08 11:19:56 AM UTC 25 |
Feb 08 11:31:21 AM UTC 25 |
489982345875 ps |
| T731 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.3745090535 |
|
|
Feb 08 11:28:27 AM UTC 25 |
Feb 08 11:31:44 AM UTC 25 |
326036549256 ps |
| T732 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.885735811 |
|
|
Feb 08 11:28:31 AM UTC 25 |
Feb 08 11:31:46 AM UTC 25 |
160182022522 ps |
| T733 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.1668327008 |
|
|
Feb 08 11:31:21 AM UTC 25 |
Feb 08 11:31:50 AM UTC 25 |
5986594904 ps |
| T734 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3469184937 |
|
|
Feb 08 11:29:28 AM UTC 25 |
Feb 08 11:31:52 AM UTC 25 |
162956872283 ps |
| T735 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.2793862409 |
|
|
Feb 08 11:29:39 AM UTC 25 |
Feb 08 11:31:52 AM UTC 25 |
201507429577 ps |
| T736 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.2602603601 |
|
|
Feb 08 11:22:49 AM UTC 25 |
Feb 08 11:31:58 AM UTC 25 |
71829852790 ps |
| T195 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.449914319 |
|
|
Feb 08 11:26:39 AM UTC 25 |
Feb 08 11:32:01 AM UTC 25 |
483356377928 ps |
| T359 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.1096366075 |
|
|
Feb 08 11:23:42 AM UTC 25 |
Feb 08 11:32:05 AM UTC 25 |
88828128858 ps |
| T346 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2318938077 |
|
|
Feb 08 11:07:29 AM UTC 25 |
Feb 08 11:32:06 AM UTC 25 |
488352755788 ps |
| T737 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2778732158 |
|
|
Feb 08 11:28:41 AM UTC 25 |
Feb 08 11:32:16 AM UTC 25 |
611787216244 ps |
| T738 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.239896905 |
|
|
Feb 08 11:32:06 AM UTC 25 |
Feb 08 11:32:20 AM UTC 25 |
3068403411 ps |
| T739 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.782900230 |
|
|
Feb 08 11:27:52 AM UTC 25 |
Feb 08 11:32:42 AM UTC 25 |
331826236963 ps |
| T196 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.1587762738 |
|
|
Feb 08 11:28:35 AM UTC 25 |
Feb 08 11:32:55 AM UTC 25 |
380290239074 ps |
| T740 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.2989837290 |
|
|
Feb 08 11:32:56 AM UTC 25 |
Feb 08 11:33:00 AM UTC 25 |
400157031 ps |
| T741 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2680260767 |
|
|
Feb 08 11:17:10 AM UTC 25 |
Feb 08 11:33:07 AM UTC 25 |
393133545687 ps |
| T742 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3326289413 |
|
|
Feb 08 11:24:57 AM UTC 25 |
Feb 08 11:33:15 AM UTC 25 |
163292104778 ps |
| T743 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.3078830237 |
|
|
Feb 08 11:33:01 AM UTC 25 |
Feb 08 11:33:17 AM UTC 25 |
5952284431 ps |
| T744 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.4167774746 |
|
|
Feb 08 11:26:52 AM UTC 25 |
Feb 08 11:33:22 AM UTC 25 |
484667295865 ps |
| T363 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.686097326 |
|
|
Feb 08 11:21:29 AM UTC 25 |
Feb 08 11:33:37 AM UTC 25 |
587339391135 ps |
| T745 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.3573982034 |
|
|
Feb 08 11:09:05 AM UTC 25 |
Feb 08 11:33:38 AM UTC 25 |
497212829292 ps |
| T746 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.1883874583 |
|
|
Feb 08 11:27:33 AM UTC 25 |
Feb 08 11:33:44 AM UTC 25 |
168098018483 ps |
| T182 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.3188464765 |
|
|
Feb 08 11:27:31 AM UTC 25 |
Feb 08 11:33:59 AM UTC 25 |
491235515930 ps |
| T311 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1907649773 |
|
|
Feb 08 11:31:00 AM UTC 25 |
Feb 08 11:34:06 AM UTC 25 |
45430525658 ps |
| T747 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.1640316364 |
|
|
Feb 08 11:34:08 AM UTC 25 |
Feb 08 11:34:20 AM UTC 25 |
4904369057 ps |
| T319 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3941541152 |
|
|
Feb 08 11:32:21 AM UTC 25 |
Feb 08 11:34:23 AM UTC 25 |
62879273355 ps |
| T748 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.149371984 |
|
|
Feb 08 11:28:42 AM UTC 25 |
Feb 08 11:34:27 AM UTC 25 |
163597850486 ps |
| T183 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.196201461 |
|
|
Feb 08 11:30:04 AM UTC 25 |
Feb 08 11:34:27 AM UTC 25 |
482473101299 ps |
| T749 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1869716716 |
|
|
Feb 08 11:30:38 AM UTC 25 |
Feb 08 11:34:28 AM UTC 25 |
339655789878 ps |
| T750 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4046730407 |
|
|
Feb 08 11:30:26 AM UTC 25 |
Feb 08 11:34:29 AM UTC 25 |
159485647186 ps |
| T751 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.4278751795 |
|
|
Feb 08 11:34:29 AM UTC 25 |
Feb 08 11:34:32 AM UTC 25 |
333234189 ps |
| T752 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.4048972355 |
|
|
Feb 08 11:33:15 AM UTC 25 |
Feb 08 11:34:59 AM UTC 25 |
163492705467 ps |
| T240 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.4270252884 |
|
|
Feb 08 11:33:17 AM UTC 25 |
Feb 08 11:34:59 AM UTC 25 |
159985121674 ps |
| T211 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.420841345 |
|
|
Feb 08 11:17:41 AM UTC 25 |
Feb 08 11:35:04 AM UTC 25 |
498092778769 ps |
| T753 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1326165917 |
|
|
Feb 08 11:31:50 AM UTC 25 |
Feb 08 11:35:05 AM UTC 25 |
162242734790 ps |
| T754 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1024654314 |
|
|
Feb 08 11:25:08 AM UTC 25 |
Feb 08 11:35:29 AM UTC 25 |
191812528090 ps |
| T755 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3414715009 |
|
|
Feb 08 11:19:57 AM UTC 25 |
Feb 08 11:35:33 AM UTC 25 |
330163172052 ps |
| T756 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.1840098560 |
|
|
Feb 08 11:32:07 AM UTC 25 |
Feb 08 11:35:34 AM UTC 25 |
43959300093 ps |
| T757 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2463480843 |
|
|
Feb 08 11:12:41 AM UTC 25 |
Feb 08 11:35:36 AM UTC 25 |
494966844405 ps |
| T758 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.1318118784 |
|
|
Feb 08 11:31:46 AM UTC 25 |
Feb 08 11:35:38 AM UTC 25 |
317691258498 ps |
| T759 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.3531244842 |
|
|
Feb 08 11:28:25 AM UTC 25 |
Feb 08 11:35:39 AM UTC 25 |
329120597716 ps |
| T760 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.3090991200 |
|
|
Feb 08 11:28:46 AM UTC 25 |
Feb 08 11:35:43 AM UTC 25 |
169692741421 ps |
| T761 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4101928244 |
|
|
Feb 08 11:09:37 AM UTC 25 |
Feb 08 11:35:47 AM UTC 25 |
488786968112 ps |
| T184 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.437846273 |
|
|
Feb 08 11:33:38 AM UTC 25 |
Feb 08 11:35:50 AM UTC 25 |
569078404380 ps |
| T762 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2443445297 |
|
|
Feb 08 11:33:39 AM UTC 25 |
Feb 08 11:36:02 AM UTC 25 |
201541679291 ps |
| T763 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.1263981493 |
|
|
Feb 08 11:29:50 AM UTC 25 |
Feb 08 11:36:05 AM UTC 25 |
82777375627 ps |
| T764 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.2836540822 |
|
|
Feb 08 11:34:22 AM UTC 25 |
Feb 08 11:36:25 AM UTC 25 |
42660628595 ps |
| T765 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.283194738 |
|
|
Feb 08 11:30:17 AM UTC 25 |
Feb 08 11:36:37 AM UTC 25 |
164638731463 ps |
| T766 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.834872266 |
|
|
Feb 08 11:34:00 AM UTC 25 |
Feb 08 11:36:40 AM UTC 25 |
163543042950 ps |
| T767 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.3423017644 |
|
|
Feb 08 11:29:15 AM UTC 25 |
Feb 08 11:36:42 AM UTC 25 |
75325265207 ps |
| T221 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.263350239 |
|
|
Feb 08 11:27:49 AM UTC 25 |
Feb 08 11:36:46 AM UTC 25 |
374839875214 ps |
| T768 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3325155936 |
|
|
Feb 08 11:31:52 AM UTC 25 |
Feb 08 11:36:49 AM UTC 25 |
210395511432 ps |
| T312 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.393939107 |
|
|
Feb 08 11:29:21 AM UTC 25 |
Feb 08 11:36:55 AM UTC 25 |
235614421609 ps |
| T769 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2946726733 |
|
|
Feb 08 11:30:43 AM UTC 25 |
Feb 08 11:36:55 AM UTC 25 |
356926856808 ps |
| T298 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1462710714 |
|
|
Feb 08 11:31:59 AM UTC 25 |
Feb 08 11:36:59 AM UTC 25 |
324954063195 ps |
| T770 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2330829714 |
|
|
Feb 08 11:34:28 AM UTC 25 |
Feb 08 11:37:00 AM UTC 25 |
45517366103 ps |
| T771 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2139117799 |
|
|
Feb 08 11:23:23 AM UTC 25 |
Feb 08 11:37:14 AM UTC 25 |
328174915726 ps |
| T772 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2294671248 |
|
|
Feb 08 11:27:42 AM UTC 25 |
Feb 08 11:37:22 AM UTC 25 |
90683522943 ps |
| T773 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.981252984 |
|
|
Feb 08 11:26:21 AM UTC 25 |
Feb 08 11:37:25 AM UTC 25 |
188336626391 ps |
| T774 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.2207398931 |
|
|
Feb 08 11:26:13 AM UTC 25 |
Feb 08 11:37:53 AM UTC 25 |
114911293778 ps |
| T775 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3806280532 |
|
|
Feb 08 11:22:09 AM UTC 25 |
Feb 08 11:37:58 AM UTC 25 |
321582545086 ps |
| T776 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.2824607063 |
|
|
Feb 08 11:30:26 AM UTC 25 |
Feb 08 11:38:01 AM UTC 25 |
667281143577 ps |
| T777 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.157041549 |
|
|
Feb 08 11:30:16 AM UTC 25 |
Feb 08 11:38:04 AM UTC 25 |
161782923523 ps |
| T778 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.2153034620 |
|
|
Feb 08 11:34:24 AM UTC 25 |
Feb 08 11:38:42 AM UTC 25 |
78108320274 ps |
| T779 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.1777116114 |
|
|
Feb 08 11:19:38 AM UTC 25 |
Feb 08 11:39:30 AM UTC 25 |
490037432610 ps |
| T780 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3725211624 |
|
|
Feb 08 11:29:40 AM UTC 25 |
Feb 08 11:40:00 AM UTC 25 |
206772546043 ps |
| T781 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.2267784331 |
|
|
Feb 08 11:31:45 AM UTC 25 |
Feb 08 11:40:28 AM UTC 25 |
488527801997 ps |
| T782 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3002401074 |
|
|
Feb 08 11:32:17 AM UTC 25 |
Feb 08 11:41:35 AM UTC 25 |
90070865001 ps |
| T306 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.2525985681 |
|
|
Feb 08 11:16:32 AM UTC 25 |
Feb 08 11:42:08 AM UTC 25 |
4391138880234 ps |
| T351 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.3704540577 |
|
|
Feb 08 11:22:09 AM UTC 25 |
Feb 08 11:42:44 AM UTC 25 |
386834128134 ps |
| T783 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.2619810604 |
|
|
Feb 08 11:14:28 AM UTC 25 |
Feb 08 11:43:17 AM UTC 25 |
603570517149 ps |
| T323 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.3678262017 |
|
|
Feb 08 11:19:27 AM UTC 25 |
Feb 08 11:43:45 AM UTC 25 |
516251893533 ps |
| T784 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.4261224468 |
|
|
Feb 08 11:34:28 AM UTC 25 |
Feb 08 11:43:50 AM UTC 25 |
326388393088 ps |
| T324 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1344026535 |
|
|
Feb 08 11:25:04 AM UTC 25 |
Feb 08 11:44:11 AM UTC 25 |
577408147161 ps |
| T785 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1635289408 |
|
|
Feb 08 11:33:23 AM UTC 25 |
Feb 08 11:44:21 AM UTC 25 |
327629957087 ps |
| T786 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3764562789 |
|
|
Feb 08 11:22:12 AM UTC 25 |
Feb 08 11:45:20 AM UTC 25 |
603645436885 ps |
| T787 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1356545224 |
|
|
Feb 08 11:27:11 AM UTC 25 |
Feb 08 11:45:37 AM UTC 25 |
404521372808 ps |
| T788 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.4211305393 |
|
|
Feb 08 11:29:28 AM UTC 25 |
Feb 08 11:46:45 AM UTC 25 |
492252194044 ps |
| T789 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.296296641 |
|
|
Feb 08 11:31:07 AM UTC 25 |
Feb 08 11:47:05 AM UTC 25 |
335064002347 ps |
| T790 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.2348051960 |
|
|
Feb 08 11:07:16 AM UTC 25 |
Feb 08 11:47:17 AM UTC 25 |
672039411656 ps |
| T285 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.979289713 |
|
|
Feb 08 11:24:02 AM UTC 25 |
Feb 08 11:48:16 AM UTC 25 |
486544112076 ps |
| T302 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.935999169 |
|
|
Feb 08 11:33:44 AM UTC 25 |
Feb 08 11:48:26 AM UTC 25 |
533762336380 ps |
| T791 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.2985144993 |
|
|
Feb 08 11:31:52 AM UTC 25 |
Feb 08 11:48:55 AM UTC 25 |
405119220322 ps |
| T792 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.1343429479 |
|
|
Feb 08 11:28:21 AM UTC 25 |
Feb 08 11:49:13 AM UTC 25 |
484719444373 ps |
| T793 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.4055439703 |
|
|
Feb 08 11:30:56 AM UTC 25 |
Feb 08 11:49:40 AM UTC 25 |
142024855557 ps |
| T794 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.2589225153 |
|
|
Feb 08 11:33:08 AM UTC 25 |
Feb 08 11:50:13 AM UTC 25 |
333109386864 ps |
| T795 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.3750913697 |
|
|
Feb 08 11:32:43 AM UTC 25 |
Feb 08 11:50:15 AM UTC 25 |
339162038402 ps |
| T796 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.588561646 |
|
|
Feb 08 11:29:26 AM UTC 25 |
Feb 08 11:52:17 AM UTC 25 |
491126274877 ps |
| T797 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4251316945 |
|
|
Feb 08 11:23:29 AM UTC 25 |
Feb 08 11:53:24 AM UTC 25 |
597683382432 ps |
| T798 |
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.3533172615 |
|
|
Feb 08 11:29:48 AM UTC 25 |
Feb 08 11:53:58 AM UTC 25 |
539582747726 ps |