AES/MASKED Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.591us	1	1	100.00
V1	smoke	aes_smoke	11.000s	272.704us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	81.312us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	127.653us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	5.567ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	422.973us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	94.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	127.653us	20	20	100.00
		aes_csr_aliasing	5.000s	422.973us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	272.704us	50	50	100.00
		aes_config_error	29.000s	1.146ms	50	50	100.00
		aes_stress	3.100m	2.249ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	272.704us	50	50	100.00
		aes_config_error	29.000s	1.146ms	50	50	100.00
		aes_stress	3.100m	2.249ms	50	50	100.00
V2	back2back	aes_stress	3.100m	2.249ms	50	50	100.00
		aes_b2b	59.000s	788.538us	50	50	100.00
V2	backpressure	aes_stress	3.100m	2.249ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	272.704us	50	50	100.00
		aes_config_error	29.000s	1.146ms	50	50	100.00
		aes_stress	3.100m	2.249ms	50	50	100.00
		aes_alert_reset	21.000s	806.587us	50	50	100.00
V2	failure_test	aes_config_error	29.000s	1.146ms	50	50	100.00
		aes_alert_reset	21.000s	806.587us	50	50	100.00
		aes_man_cfg_err	5.000s	56.538us	50	50	100.00
V2	trigger_clear_test	aes_clear	34.000s	1.008ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	309.525us	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	806.587us	50	50	100.00
V2	stress	aes_stress	3.100m	2.249ms	50	50	100.00
V2	sideload	aes_stress	3.100m	2.249ms	50	50	100.00
		aes_sideload	36.000s	1.030ms	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	2.336ms	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	58.910us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	342.542us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	342.542us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	81.312us	5	5	100.00
		aes_csr_rw	4.000s	127.653us	20	20	100.00
		aes_csr_aliasing	5.000s	422.973us	5	5	100.00
		aes_same_csr_outstanding	5.000s	138.603us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	81.312us	5	5	100.00
		aes_csr_rw	4.000s	127.653us	20	20	100.00
		aes_csr_aliasing	5.000s	422.973us	5	5	100.00
		aes_same_csr_outstanding	5.000s	138.603us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.150m	1.421ms	49	50	98.00
V2S	fault_inject	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	143.013us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	25.000s	9.118ms	5	5	100.00
		aes_tl_intg_err	6.000s	163.574us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	163.574us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	806.587us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	272.704us	50	50	100.00
		aes_stress	3.100m	2.249ms	50	50	100.00
		aes_alert_reset	21.000s	806.587us	50	50	100.00
		aes_core_fi	27.000s	10.009ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	113.531us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.100m	2.249ms	50	50	100.00
		aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.100m	2.249ms	50	50	100.00
		aes_sideload	36.000s	1.030ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	110.956us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.100m	2.249ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.100m	2.249ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.917m	5.140ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.917m	5.140ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	10.030ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.917m	5.140ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	806.587us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_ctr_fi	6.000s	75.966us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.917m	5.140ms	50	50	100.00
		aes_control_fi	48.000s	10.016ms	286	300	95.33
		aes_cipher_fi	54.000s	10.030ms	333	350	95.14
V2S		TOTAL			952	985	96.65
V3		TOTAL			0	0	--
		TOTAL			1549	1582	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.47	99.02	97.55	99.41	95.83	95.66	97.78	98.67	92.70

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 13 failures.
  - 0.aes_control_fi.1461408133
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:cc178176-4230-4aa3-862a-a314d377fd92
```
  - 12.aes_control_fi.189332528
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:3eacfe31-b358-4a55-b903-7853569f3dcc
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 7 failures.
  - 33.aes_cipher_fi.4067934444
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  Job ID: smart:217bcef8-c636-45a6-ab21-0022cec5ea38
```
  - 68.aes_cipher_fi.244931264
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/68.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f5fb48b6-cd63-4a42-9e1d-72c19677b388
```
  - ... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_cipher_fi has 10 failures.

12.aes_cipher_fi.1899772001
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10030334258 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030334258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

89.aes_cipher_fi.3413209947
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10009256050 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009256050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 16.aes_core_fi.770168513
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008919423 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008919423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

34.aes_reseed.1458133244
Line 9357, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_reseed/latest/run.log

  UVM_FATAL @  35191180 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 96      3e      d2      0
                 1 00      d5      0c      0

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 276.aes_control_fi.4141184916
    Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/276.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015982498 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015982498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```