AES/MASKED Simulation Results

Sunday October 08 2023 19:02:39 UTC

GitHub Revision: `4e80560e2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3527490040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	82.967us	1	1	100.00
V1	smoke	aes_smoke	19.000s	1.107ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	65.537us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	58.081us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	764.214us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	87.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	216.420us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	58.081us	20	20	100.00
		aes_csr_aliasing	6.000s	87.001us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	19.000s	1.107ms	50	50	100.00
		aes_config_error	1.683m	3.622ms	50	50	100.00
		aes_stress	1.617m	2.812ms	50	50	100.00
V2	key_length	aes_smoke	19.000s	1.107ms	50	50	100.00
		aes_config_error	1.683m	3.622ms	50	50	100.00
		aes_stress	1.617m	2.812ms	50	50	100.00
V2	back2back	aes_stress	1.617m	2.812ms	50	50	100.00
		aes_b2b	53.000s	661.538us	50	50	100.00
V2	backpressure	aes_stress	1.617m	2.812ms	50	50	100.00
V2	multi_message	aes_smoke	19.000s	1.107ms	50	50	100.00
		aes_config_error	1.683m	3.622ms	50	50	100.00
		aes_stress	1.617m	2.812ms	50	50	100.00
		aes_alert_reset	27.000s	1.017ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	194.845us	50	50	100.00
		aes_config_error	1.683m	3.622ms	50	50	100.00
		aes_alert_reset	27.000s	1.017ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.167m	1.854ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	177.913us	1	1	100.00
V2	reset_recovery	aes_alert_reset	27.000s	1.017ms	50	50	100.00
V2	stress	aes_stress	1.617m	2.812ms	50	50	100.00
V2	sideload	aes_stress	1.617m	2.812ms	50	50	100.00
		aes_sideload	44.000s	1.478ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	403.513us	50	50	100.00
V2	stress_all	aes_stress_all	1.467m	11.051ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	54.630us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	670.540us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	670.540us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	65.537us	5	5	100.00
		aes_csr_rw	7.000s	58.081us	20	20	100.00
		aes_csr_aliasing	6.000s	87.001us	5	5	100.00
		aes_same_csr_outstanding	9.000s	285.955us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	65.537us	5	5	100.00
		aes_csr_rw	7.000s	58.081us	20	20	100.00
		aes_csr_aliasing	6.000s	87.001us	5	5	100.00
		aes_same_csr_outstanding	9.000s	285.955us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.817m	2.994ms	49	50	98.00
V2S	fault_inject	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	175.876us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.006ms	5	5	100.00
		aes_tl_intg_err	7.000s	131.487us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	131.487us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	27.000s	1.017ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	1.107ms	50	50	100.00
		aes_stress	1.617m	2.812ms	50	50	100.00
		aes_alert_reset	27.000s	1.017ms	50	50	100.00
		aes_core_fi	26.000s	10.040ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	74.824us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	110.807us	50	50	100.00
		aes_stress	1.617m	2.812ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.617m	2.812ms	50	50	100.00
		aes_sideload	44.000s	1.478ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	110.807us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	110.807us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	110.807us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	110.807us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	110.807us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.617m	2.812ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.617m	2.812ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	1.980ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	1.980ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	10.114ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	1.980ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	27.000s	1.017ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_ctr_fi	6.000s	196.170us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	1.980ms	50	50	100.00
		aes_control_fi	54.000s	10.043ms	277	300	92.33
		aes_cipher_fi	54.000s	10.114ms	336	350	96.00
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.033m	16.170ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	98.94	97.33	99.35	95.81	95.60	97.78	98.97	98.17

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_cipher_fi has 7 failures.
  - 6.aes_cipher_fi.2604128874
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:eaa0a9f2-1506-47e6-a657-0b68fbc2ff6b
```
  - 30.aes_cipher_fi.1733455608
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job ID: smart:43d9a5f2-0f8c-49ad-9bd1-ae3c653c90bb
```
  - ... and 5 more failures.
- Test aes_control_fi has 18 failures.
  - 14.aes_control_fi.2244210168
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job ID: smart:f6790581-f6c0-4683-8376-2f7044bc174a
```
  - 15.aes_control_fi.846086512
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:72754b6d-7bc6-4b51-b559-ca51e2382ef2
```
  - ... and 16 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.2456547200
Line 873, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2243498061 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2243498061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.2891137789
Line 1333, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2533822861 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2533822861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_cipher_fi has 7 failures.

49.aes_cipher_fi.904385780
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10029831848 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029831848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

54.aes_cipher_fi.3958637772
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10006916569 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006916569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

7.aes_control_fi.1752711049
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log

  UVM_FATAL @ 10042929045 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042929045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

89.aes_control_fi.2629086190
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_control_fi/latest/run.log

  UVM_FATAL @ 10043264163 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043264163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.220277253
Line 1181, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 717457337 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 717457337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.4061700647
Line 1701, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 820567875 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 820567875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:

Test aes_stress_all has 1 failures.

5.aes_stress_all.3180547911
Line 1318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log

  UVM_FATAL @ 199809432 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 199809432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_reseed has 1 failures.

44.aes_reseed.2356934816
Line 4577, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_reseed/latest/run.log

  UVM_FATAL @ 220606694 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 220606694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 33.aes_core_fi.3091081937
    Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022479832 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022479832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.1144086680
    Line 269, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039511608 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x734c5684) == 0x0
  UVM_INFO @ 10039511608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```