AES/MASKED Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	91.014us	1	1	100.00
V1	smoke	aes_smoke	12.000s	197.633us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	81.144us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	109.397us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	320.384us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	173.455us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	10.000s	80.440us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	109.397us	20	20	100.00
		aes_csr_aliasing	8.000s	173.455us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	197.633us	50	50	100.00
		aes_config_error	21.000s	1.853ms	50	50	100.00
		aes_stress	27.000s	8.696ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	197.633us	50	50	100.00
		aes_config_error	21.000s	1.853ms	50	50	100.00
		aes_stress	27.000s	8.696ms	50	50	100.00
V2	back2back	aes_stress	27.000s	8.696ms	50	50	100.00
		aes_b2b	33.000s	380.048us	50	50	100.00
V2	backpressure	aes_stress	27.000s	8.696ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	197.633us	50	50	100.00
		aes_config_error	21.000s	1.853ms	50	50	100.00
		aes_stress	27.000s	8.696ms	50	50	100.00
		aes_alert_reset	31.000s	1.155ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	60.338us	50	50	100.00
		aes_config_error	21.000s	1.853ms	50	50	100.00
		aes_alert_reset	31.000s	1.155ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.633m	5.251ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	21.000s	545.120us	1	1	100.00
V2	reset_recovery	aes_alert_reset	31.000s	1.155ms	50	50	100.00
V2	stress	aes_stress	27.000s	8.696ms	50	50	100.00
V2	sideload	aes_stress	27.000s	8.696ms	50	50	100.00
		aes_sideload	44.000s	1.629ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	151.717us	50	50	100.00
V2	stress_all	aes_stress_all	1.233m	3.302ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	55.622us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	106.171us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	106.171us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	81.144us	5	5	100.00
		aes_csr_rw	5.000s	109.397us	20	20	100.00
		aes_csr_aliasing	8.000s	173.455us	5	5	100.00
		aes_same_csr_outstanding	6.000s	330.430us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	81.144us	5	5	100.00
		aes_csr_rw	5.000s	109.397us	20	20	100.00
		aes_csr_aliasing	8.000s	173.455us	5	5	100.00
		aes_same_csr_outstanding	6.000s	330.430us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	16.000s	518.862us	49	50	98.00
V2S	fault_inject	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	125.270us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	1.268ms	5	5	100.00
		aes_tl_intg_err	9.000s	315.569us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	315.569us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	31.000s	1.155ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	197.633us	50	50	100.00
		aes_stress	27.000s	8.696ms	50	50	100.00
		aes_alert_reset	31.000s	1.155ms	50	50	100.00
		aes_core_fi	1.717m	10.124ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	152.069us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	110.696us	50	50	100.00
		aes_stress	27.000s	8.696ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	27.000s	8.696ms	50	50	100.00
		aes_sideload	44.000s	1.629ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	110.696us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	110.696us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	110.696us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	110.696us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	110.696us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	27.000s	8.696ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	27.000s	8.696ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	1.782ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	1.782ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	34.000s	10.011ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	1.782ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	31.000s	1.155ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_ctr_fi	9.000s	61.014us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	1.782ms	49	50	98.00
		aes_control_fi	31.000s	10.065ms	286	300	95.33
		aes_cipher_fi	34.000s	10.011ms	338	350	96.57
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.883m	3.671ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.50	98.96	97.42	99.37	95.85	95.60	97.78	98.97	98.99

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 10 failures.
  - 10.aes_control_fi.38413815660276055431591058945782247161323218993963674509587264176253014474650
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:2b80dcb0-6838-4bdb-9097-196d36cafa51
```
  - 82.aes_control_fi.67308674144312118038047859680386829403245339891442317353056055688230906413894
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_control_fi/latest/run.log
```
  Job ID: smart:2e5c2d7e-42f2-4dbc-b86e-7fe63eb70fea
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 5 failures.
  - 47.aes_cipher_fi.9398132286837525413051532777896459886218248975460658977345614054283252890751
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7ac27488-90f7-4e8d-b048-fe5eed1821de
```
  - 88.aes_cipher_fi.15500040518927414487040736350969021516735090192271931257324092678012815862531
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_cipher_fi/latest/run.log
```
  Job ID: smart:00963d92-2453-45a9-9c62-c2cf334f9591
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.51316763929981424564196011356761325312542073895738492733844391641435401299699
Line 469, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3671375361 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3671375361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.75076900183123918035987695491604952023669544815065276645052772026570617540927
Line 752, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 975012288 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 975012288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 27.aes_cipher_fi.19890967730563236410905773258878089509017827708489811601229470792551735432770
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011222712 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011222712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_cipher_fi.28982835206065091454991835726134612268964048399008493962398216093271987634811
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015320847 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015320847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 2.aes_core_fi.5504274764693167555184857792735095291362542593432437582114144644309611862541
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011265913 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011265913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_core_fi.47418942054234476269023671859438323564126291615543632177290095296810507590538
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005717335 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005717335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 61.aes_control_fi.18844024214223821844898097917229205375104404046241219154395839302712222238731
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013837269 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013837269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 142.aes_control_fi.79422732254906032487398659790494069842451053960301039637193951914159735106765
    Line 334, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/142.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10031211658 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031211658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.56606456555220459659606723369864213749127885828351846069445492582638221183699
Line 1346, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 625463375 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 625463375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.15553477171689873163621845475035850739669062181027864432095882213424634871092
Line 1246, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10599116725 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10599116725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 3.aes_fi.105316894158397951608643753980951351449248185679652326263819834490089254300377
    Line 4064, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 52863246 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 52807690 PS)
  UVM_ERROR @  52863246 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  52863246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 8.aes_reseed.1853057558620399492515945546159239670270652923625946441548905311285814342431
    Line 1374, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_reseed/latest/run.log
```
  UVM_FATAL @ 348197980 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 348197980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```