AES/MASKED Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	65.931us	1	1	100.00
V1	smoke	aes_smoke	8.000s	532.971us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	63.112us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	113.203us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.199ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	72.833us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	62.892us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	113.203us	20	20	100.00
		aes_csr_aliasing	6.000s	72.833us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	532.971us	50	50	100.00
		aes_config_error	14.000s	473.184us	50	50	100.00
		aes_stress	18.000s	524.868us	50	50	100.00
V2	key_length	aes_smoke	8.000s	532.971us	50	50	100.00
		aes_config_error	14.000s	473.184us	50	50	100.00
		aes_stress	18.000s	524.868us	50	50	100.00
V2	back2back	aes_stress	18.000s	524.868us	50	50	100.00
		aes_b2b	46.000s	778.000us	50	50	100.00
V2	backpressure	aes_stress	18.000s	524.868us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	532.971us	50	50	100.00
		aes_config_error	14.000s	473.184us	50	50	100.00
		aes_stress	18.000s	524.868us	50	50	100.00
		aes_alert_reset	45.000s	3.298ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	240.959us	50	50	100.00
		aes_config_error	14.000s	473.184us	50	50	100.00
		aes_alert_reset	45.000s	3.298ms	50	50	100.00
V2	trigger_clear_test	aes_clear	33.000s	1.991ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	354.851us	1	1	100.00
V2	reset_recovery	aes_alert_reset	45.000s	3.298ms	50	50	100.00
V2	stress	aes_stress	18.000s	524.868us	50	50	100.00
V2	sideload	aes_stress	18.000s	524.868us	50	50	100.00
		aes_sideload	12.000s	835.705us	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	469.533us	50	50	100.00
V2	stress_all	aes_stress_all	8.983m	17.295ms	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	94.589us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	203.894us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	203.894us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	63.112us	5	5	100.00
		aes_csr_rw	9.000s	113.203us	20	20	100.00
		aes_csr_aliasing	6.000s	72.833us	5	5	100.00
		aes_same_csr_outstanding	6.700m	10.016ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	63.112us	5	5	100.00
		aes_csr_rw	9.000s	113.203us	20	20	100.00
		aes_csr_aliasing	6.000s	72.833us	5	5	100.00
		aes_same_csr_outstanding	6.700m	10.016ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	18.000s	490.217us	49	50	98.00
V2S	fault_inject	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	1.106ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.048ms	5	5	100.00
		aes_tl_intg_err	10.000s	479.480us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	479.480us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	45.000s	3.298ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	532.971us	50	50	100.00
		aes_stress	18.000s	524.868us	50	50	100.00
		aes_alert_reset	45.000s	3.298ms	50	50	100.00
		aes_core_fi	1.433m	10.011ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	393.145us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	65.156us	50	50	100.00
		aes_stress	18.000s	524.868us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	524.868us	50	50	100.00
		aes_sideload	12.000s	835.705us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	65.156us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	65.156us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	65.156us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	65.156us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	65.156us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	524.868us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	524.868us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	388.037us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	388.037us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.014ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	388.037us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	45.000s	3.298ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_ctr_fi	11.000s	457.567us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	388.037us	49	50	98.00
		aes_control_fi	48.000s	10.019ms	286	300	95.33
		aes_cipher_fi	49.000s	10.014ms	341	350	97.43
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.350m	54.793ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	99.02	97.53	99.41	95.97	95.66	100.00	98.97	98.17

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test aes_cipher_fi has 3 failures.
  - 22.aes_cipher_fi.47864342749812341920979879504859700592543597704400639379089198931317196403100
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9cf10813-043f-4635-87d2-a593a6ce5891
```
  - 167.aes_cipher_fi.65966789194130901786857123261365099065108550818671202707816125449213135484417
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/167.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b29e589c-c27c-4afd-b866-e68e6fae7593
```
  - ... and 1 more failures.
- Test aes_control_fi has 8 failures.
  - 28.aes_control_fi.13949856292087494697630386080589155824672411461599436597546764189518691108077
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job ID: smart:38fca330-fed1-4486-92e4-68a63616ad00
```
  - 72.aes_control_fi.106401476182123347395610664082360422478099369887104734738678892056021349916395
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  Job ID: smart:0e722864-d647-4559-87de-4e29898631f7
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.67698889432023552977420395151604602971153151943773754846348825578160092858823
Line 1338, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 629092014 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 629092014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.18320543249797257994366051420019560785485288719999311527112425370560740593748
Line 1011, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 425993667 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 425993667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 36.aes_control_fi.56434691327304321566067992518709328053023713496763212377437748202679356390175
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014275962 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014275962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.aes_control_fi.112590778983191592926573995959478533645792329180128530477520373430874803139155
    Line 333, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012053703 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012053703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 62.aes_cipher_fi.43664565012856659122714578247220082607561803251843699994083064675431942647404
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010411558 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010411558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 66.aes_cipher_fi.65237978299191721017250051568025325950882784016979316795823591737443568111238
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030744164 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030744164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.47402086457034088711143301213976811913201918070357088026985092069802703692937
Line 1412, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10367632468 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10367632468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.77856495502001468195823439816829209153271669801433911881608739419518484838469
Line 1213, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1299325350 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1299325350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all has 1 failures.
  - 0.aes_stress_all.34613849571302735511734987623669936112222426864933005156170892764592290067926
    Line 16080, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 848557585 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 848557585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_reseed has 1 failures.
  - 26.aes_reseed.45364655351494028440183585880781954240843439494272465356690364477043285685025
    Line 1924, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_reseed/latest/run.log
```
  UVM_FATAL @ 361537498 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 361537498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 27.aes_core_fi.72714082650034140065997523691698851460883047438395527533635027627331881222637
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011109221 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011109221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_core_fi.7342404668266621263886416509229673876378242625162452147958011129023603540413
    Line 333, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015229415 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015229415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 12.aes_same_csr_outstanding.53135579472271216325114008201242197991080693633350507151072961608618424800988
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10015993970 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xa6d76f84) == 0x0
  UVM_INFO @ 10015993970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 49.aes_fi.111688388975360395975418444169925308109561840787410171253944630796467029401548
    Line 4113, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 21415613 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21395613 PS)
  UVM_ERROR @  21415613 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  21415613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```