AES/MASKED Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	287.080us	1	1	100.00
V1	smoke	aes_smoke	19.000s	521.757us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	61.431us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	504.135us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	510.830us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	3.451ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	84.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	504.135us	20	20	100.00
		aes_csr_aliasing	7.000s	3.451ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	19.000s	521.757us	50	50	100.00
		aes_config_error	15.000s	558.149us	50	50	100.00
		aes_stress	29.000s	1.477ms	50	50	100.00
V2	key_length	aes_smoke	19.000s	521.757us	50	50	100.00
		aes_config_error	15.000s	558.149us	50	50	100.00
		aes_stress	29.000s	1.477ms	50	50	100.00
V2	back2back	aes_stress	29.000s	1.477ms	50	50	100.00
		aes_b2b	27.000s	302.853us	50	50	100.00
V2	backpressure	aes_stress	29.000s	1.477ms	50	50	100.00
V2	multi_message	aes_smoke	19.000s	521.757us	50	50	100.00
		aes_config_error	15.000s	558.149us	50	50	100.00
		aes_stress	29.000s	1.477ms	50	50	100.00
		aes_alert_reset	45.000s	8.102ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	226.785us	50	50	100.00
		aes_config_error	15.000s	558.149us	50	50	100.00
		aes_alert_reset	45.000s	8.102ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.633m	22.830ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	267.454us	1	1	100.00
V2	reset_recovery	aes_alert_reset	45.000s	8.102ms	50	50	100.00
V2	stress	aes_stress	29.000s	1.477ms	50	50	100.00
V2	sideload	aes_stress	29.000s	1.477ms	50	50	100.00
		aes_sideload	16.000s	1.141ms	50	50	100.00
V2	deinitialization	aes_deinit	20.000s	652.741us	50	50	100.00
V2	stress_all	aes_stress_all	27.883m	93.774ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	172.082us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	349.250us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	349.250us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	61.431us	5	5	100.00
		aes_csr_rw	7.000s	504.135us	20	20	100.00
		aes_csr_aliasing	7.000s	3.451ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	105.660us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	61.431us	5	5	100.00
		aes_csr_rw	7.000s	504.135us	20	20	100.00
		aes_csr_aliasing	7.000s	3.451ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	105.660us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	47.000s	1.625ms	50	50	100.00
V2S	fault_inject	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	128.540us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	629.139us	5	5	100.00
		aes_tl_intg_err	6.000s	775.753us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	775.753us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	45.000s	8.102ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	521.757us	50	50	100.00
		aes_stress	29.000s	1.477ms	50	50	100.00
		aes_alert_reset	45.000s	8.102ms	50	50	100.00
		aes_core_fi	57.000s	10.017ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	87.435us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	86.699us	50	50	100.00
		aes_stress	29.000s	1.477ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	29.000s	1.477ms	50	50	100.00
		aes_sideload	16.000s	1.141ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	86.699us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	86.699us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	86.699us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	86.699us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	86.699us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	29.000s	1.477ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	29.000s	1.477ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	12.000s	237.719us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	12.000s	237.719us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	29.000s	10.014ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	12.000s	237.719us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	45.000s	8.102ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_ctr_fi	8.000s	73.734us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	12.000s	237.719us	50	50	100.00
		aes_control_fi	50.000s	10.007ms	279	300	93.00
		aes_cipher_fi	29.000s	10.014ms	344	350	98.29
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.650m	11.619ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.60	99.01	97.51	99.42	95.88	97.72	97.78	99.11	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 13 failures.
  - 6.aes_control_fi.53120785819188308829886802865958563249635304391846702794324722276079007234151
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:d77f69bc-c568-4ad9-ba55-6f4aeebfd182
```
  - 26.aes_control_fi.6235141267232030177737459905522903874204972300011674823341711137287454789603
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:1471c135-d5e4-4608-8f7e-5be359a08b35
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 4 failures.
  - 96.aes_cipher_fi.26955542691561513871430654485247311887803273072702536005495275072706264052523
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f122c7f1-b875-4c4c-8c1e-5b249c0439f5
```
  - 214.aes_cipher_fi.62271427517925115886892953876173014547073485687556071985323641077668961965456
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/214.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9be501ce-f192-4977-b447-c56b27302886
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 0.aes_control_fi.19487512649308449498110305017945164044117342301532001600570122794664888014935
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011942781 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011942781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.aes_control_fi.56487933794531858867763817797949606730974294191698025058810699125735798412330
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009517995 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009517995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.47833510964229447759529456165847428616016644632938537596159084207164660922554
Line 707, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2808326524 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2808326524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.107466890736237060469372710201359591330330380576348747600756761712266668295374
Line 596, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20400297392 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 20400297392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.39261554765241197374126328806736396638646216541265071281801453860172453641842
Line 1588, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6277851320 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6277851320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.30734274959116497251077359237629956175352070183256082477889122276156532193249
Line 1872, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1151254577 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1151254577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 9.aes_core_fi.39930940704975999673451901805460842640861697352799206544963653933088778206724
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018516602 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018516602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_core_fi.46371714605058120164641484263769680610229862753651147673184307668734734371585
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015092569 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015092569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_cipher_fi has 2 failures.
  - 163.aes_cipher_fi.101908005255231753255925507236206847654771894698921504072108489076072061906593
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/163.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013964297 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013964297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 327.aes_cipher_fi.100598421888776369955490653528380689134328781993282265722977692161582565350256
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/327.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021169887 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021169887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```