AES/MASKED Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.133us	1	1	100.00
V1	smoke	aes_smoke	10.000s	191.987us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	292.511us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	71.895us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	856.335us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	289.493us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	69.436us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	71.895us	20	20	100.00
		aes_csr_aliasing	5.000s	289.493us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	191.987us	50	50	100.00
		aes_config_error	3.150m	4.886ms	50	50	100.00
		aes_stress	1.983m	4.120ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	191.987us	50	50	100.00
		aes_config_error	3.150m	4.886ms	50	50	100.00
		aes_stress	1.983m	4.120ms	50	50	100.00
V2	back2back	aes_stress	1.983m	4.120ms	50	50	100.00
		aes_b2b	33.000s	1.136ms	50	50	100.00
V2	backpressure	aes_stress	1.983m	4.120ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	191.987us	50	50	100.00
		aes_config_error	3.150m	4.886ms	50	50	100.00
		aes_stress	1.983m	4.120ms	50	50	100.00
		aes_alert_reset	28.000s	963.098us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	118.582us	50	50	100.00
		aes_config_error	3.150m	4.886ms	50	50	100.00
		aes_alert_reset	28.000s	963.098us	50	50	100.00
V2	trigger_clear_test	aes_clear	57.000s	1.686ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.900m	35.454ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	963.098us	50	50	100.00
V2	stress	aes_stress	1.983m	4.120ms	50	50	100.00
V2	sideload	aes_stress	1.983m	4.120ms	50	50	100.00
		aes_sideload	50.000s	6.620ms	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	79.569us	50	50	100.00
V2	stress_all	aes_stress_all	2.650m	4.912ms	10	10	100.00
V2	alert_test	aes_alert_test	10.000s	140.755us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	466.293us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	466.293us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	292.511us	5	5	100.00
		aes_csr_rw	4.000s	71.895us	20	20	100.00
		aes_csr_aliasing	5.000s	289.493us	5	5	100.00
		aes_same_csr_outstanding	36.000s	10.208ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	292.511us	5	5	100.00
		aes_csr_rw	4.000s	71.895us	20	20	100.00
		aes_csr_aliasing	5.000s	289.493us	5	5	100.00
		aes_same_csr_outstanding	36.000s	10.208ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	44.000s	3.586ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	294.305us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.251ms	5	5	100.00
		aes_tl_intg_err	5.000s	165.201us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	165.201us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	963.098us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	191.987us	50	50	100.00
		aes_stress	1.983m	4.120ms	50	50	100.00
		aes_alert_reset	28.000s	963.098us	50	50	100.00
		aes_core_fi	1.450m	10.009ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	95.776us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	207.120us	50	50	100.00
		aes_stress	1.983m	4.120ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.983m	4.120ms	50	50	100.00
		aes_sideload	50.000s	6.620ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	207.120us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	207.120us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	207.120us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	207.120us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	207.120us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.983m	4.120ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.983m	4.120ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	204.909us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	204.909us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.037ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	204.909us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	963.098us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_ctr_fi	10.000s	73.708us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	204.909us	50	50	100.00
		aes_control_fi	50.000s	10.006ms	280	300	93.33
		aes_cipher_fi	46.000s	10.037ms	337	350	96.29
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	11.200m	23.817ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	99.04	97.60	99.44	95.85	95.60	97.78	99.12	97.57

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 17 failures.
  - 15.aes_control_fi.52905751566214923874165519115326802166137462677459109362528188089244077078198
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:711b160d-1ea2-478e-a3c1-cb5627ca15f6
```
  - 45.aes_control_fi.113053602026750162345278402936908950799203981739127477308908626692692082093279
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:c59a8191-aeb2-4c28-a8cc-3af56a472449
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 4 failures.
  - 127.aes_cipher_fi.90861966746084468939950056293619535468059781532660877467659318438770005797970
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/127.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1a39c5d7-794f-43c9-91c3-7f81c6fdbc6b
```
  - 138.aes_cipher_fi.1262439391512393458158377894052588589483794005906149393059461314212477482849
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/138.aes_cipher_fi/latest/run.log
```
  Job ID: smart:420b9775-872e-4949-ad5f-2b3e13ffc72a
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 1.aes_cipher_fi.28716910543204999002839441600740110207197744727713924891838132986861840458118
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012310237 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012310237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_cipher_fi.78707536696830156829793996689800085926960920553418233064348454814232703066
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033780778 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033780778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.104731628971922152954714864574867253187560215079517922986609138827539095607493
Line 773, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 276520050 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 276520050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.110649392726283578346921897259416015670605865471573749501087935869027301309828
Line 442, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16336352850 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 16336352850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.101169426673299885954463525225060181864774707809028821063609206504473934187630
Line 865, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2013471840 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2013471840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.83553296527926896019125551772138473848571008153614329353425090055777804509272
Line 1821, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3639551407 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3639551407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 88.aes_control_fi.94819433223667451746500731978579758862398043496815074450567149971105075215867
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10035156613 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035156613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 135.aes_control_fi.35430753698564637834720406179668168388459002755245802121971846343499556713252
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/135.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006387230 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006387230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:91) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.71847626103122728489771340329489053234558420287119833185860289798224407793678
    Line 293, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  41996555 ps: (aes_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  41996555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 11.aes_same_csr_outstanding.6669529440639550457901654891912020885244641375179790362986525990820729440907
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10208300278 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x5e323b84) == 0x0
  UVM_INFO @ 10208300278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 51.aes_core_fi.81765198307689429753537977507073478658551645260334218440062627428903939019588
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008826543 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008826543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```