AES/MASKED Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	102.021us	1	1	100.00
V1	smoke	aes_smoke	12.000s	616.664us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	100.059us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.965ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	909.144us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	61.538us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	100.059us	20	20	100.00
		aes_csr_aliasing	5.000s	909.144us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	616.664us	50	50	100.00
		aes_config_error	40.000s	3.057ms	50	50	100.00
		aes_stress	53.000s	2.917ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	616.664us	50	50	100.00
		aes_config_error	40.000s	3.057ms	50	50	100.00
		aes_stress	53.000s	2.917ms	50	50	100.00
V2	back2back	aes_stress	53.000s	2.917ms	50	50	100.00
		aes_b2b	33.000s	711.421us	50	50	100.00
V2	backpressure	aes_stress	53.000s	2.917ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	616.664us	50	50	100.00
		aes_config_error	40.000s	3.057ms	50	50	100.00
		aes_stress	53.000s	2.917ms	50	50	100.00
		aes_alert_reset	30.000s	4.137ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	350.364us	50	50	100.00
		aes_config_error	40.000s	3.057ms	50	50	100.00
		aes_alert_reset	30.000s	4.137ms	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	635.726us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	274.985us	1	1	100.00
V2	reset_recovery	aes_alert_reset	30.000s	4.137ms	50	50	100.00
V2	stress	aes_stress	53.000s	2.917ms	50	50	100.00
V2	sideload	aes_stress	53.000s	2.917ms	50	50	100.00
		aes_sideload	36.000s	934.652us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	570.798us	50	50	100.00
V2	stress_all	aes_stress_all	2.333m	5.962ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	86.361us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	500.126us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	500.126us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
		aes_csr_rw	3.000s	100.059us	20	20	100.00
		aes_csr_aliasing	5.000s	909.144us	5	5	100.00
		aes_same_csr_outstanding	4.000s	231.139us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
		aes_csr_rw	3.000s	100.059us	20	20	100.00
		aes_csr_aliasing	5.000s	909.144us	5	5	100.00
		aes_same_csr_outstanding	4.000s	231.139us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.533m	2.646ms	48	50	96.00
V2S	fault_inject	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	158.339us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.232ms	5	5	100.00
		aes_tl_intg_err	5.000s	181.311us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	181.311us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	30.000s	4.137ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	616.664us	50	50	100.00
		aes_stress	53.000s	2.917ms	50	50	100.00
		aes_alert_reset	30.000s	4.137ms	50	50	100.00
		aes_core_fi	14.000s	242.010us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	127.092us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	84.599us	50	50	100.00
		aes_stress	53.000s	2.917ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	53.000s	2.917ms	50	50	100.00
		aes_sideload	36.000s	934.652us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	84.599us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	84.599us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	84.599us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	84.599us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	84.599us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	53.000s	2.917ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	53.000s	2.917ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.900m	4.117ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.900m	4.117ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.008ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.900m	4.117ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	30.000s	4.137ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_ctr_fi	7.000s	67.079us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.900m	4.117ms	50	50	100.00
		aes_control_fi	31.000s	10.009ms	284	300	94.67
		aes_cipher_fi	47.000s	10.008ms	342	350	97.71
V2S		TOTAL			959	985	97.36
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.300m	16.150ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1566	1602	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.57	99.03	97.56	99.45	95.86	95.66	100.00	99.12	98.38

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 13 failures.
  - 2.aes_control_fi.99694538843309083669433140878712469681894858705587835050055347049536627343751
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job ID: smart:63ae833f-0e4e-4235-bb9a-ec654334c309
```
  - 17.aes_control_fi.59734550804806478088568697870233536426794556963164002527475040073380933297955
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:6c8f550f-c0e3-49f9-bf99-f55d54e65040
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 2 failures.
  - 104.aes_cipher_fi.63822186550760717243727579718004705165955214983599089836965731893287958457099
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  Job ID: smart:70633dc0-921b-41dc-bce6-52a816a8de6a
```
  - 316.aes_cipher_fi.73494654132312010519967829421989024134320447993413576931767467043608637041070
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/316.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e155647b-92cb-4f38-abb6-333058c34915
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.31138512596460127664147756490979436049560448500730793895279085295800028197114
Line 1397, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2750285647 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2750285647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.25169334941842039132099749726948880235975424704060193622183784055129525497352
Line 1801, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11776888033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 11776888033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 10.aes_cipher_fi.18877682520642873187785363082796604177364064738762502726404580230242637149164
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019150800 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019150800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_cipher_fi.13799611428271016692563824270682544412155506558764063786835515573539897407711
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010817397 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010817397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 47.aes_control_fi.26799658637178454596073257755627439160759501361228614726474715710022575325929
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009230416 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009230416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 130.aes_control_fi.91130966789894534725557076022620710822790094145040119397653982972447118491129
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/130.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017062494 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017062494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_reseed has 2 failures.
  - 7.aes_reseed.31284866825705831960551844799931812476565559805671123000478533846060706066696
    Line 2084, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_reseed/latest/run.log
```
  UVM_FATAL @ 121433880 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 121433880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_reseed.85398897536272807930974144305190846410543803948340705175395377572201521186489
    Line 899, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_reseed/latest/run.log
```
  UVM_FATAL @  66006678 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66006678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:91) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.11033958848905199735693485578945392359925150938700929773824394620979346080384
    Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   8874954 ps: (aes_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.aes_stress_all_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @   8874954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.86966014969674127253798837030786764383574391748343218991199793164834687994290
    Line 1387, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1548381053 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1548381053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:84) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.27320503527309446417254612274481257958861223957275085238558642596283650069264
    Line 293, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  10553852 ps: (aes_base_vseq.sv:84) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  10553852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 315.aes_cipher_fi.16399389764261447011875190600240763421803225472726111757987539370318050566837
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/315.aes_cipher_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 7925761 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 7915557 PS)
  UVM_ERROR @   7925761 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   7925761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```