AES/UNMASKED Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	53.368us	1	1	100.00
V1	smoke	aes_smoke	6.000s	100.864us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	80.229us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	60.719us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	697.537us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	712.454us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	60.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	60.719us	20	20	100.00
		aes_csr_aliasing	5.000s	712.454us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	100.864us	50	50	100.00
		aes_config_error	7.000s	421.625us	50	50	100.00
		aes_stress	37.000s	477.380us	50	50	100.00
V2	key_length	aes_smoke	6.000s	100.864us	50	50	100.00
		aes_config_error	7.000s	421.625us	50	50	100.00
		aes_stress	37.000s	477.380us	50	50	100.00
V2	back2back	aes_stress	37.000s	477.380us	50	50	100.00
		aes_b2b	10.000s	127.617us	50	50	100.00
V2	backpressure	aes_stress	37.000s	477.380us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	100.864us	50	50	100.00
		aes_config_error	7.000s	421.625us	50	50	100.00
		aes_stress	37.000s	477.380us	50	50	100.00
		aes_alert_reset	13.000s	565.628us	50	50	100.00
V2	failure_test	aes_config_error	7.000s	421.625us	50	50	100.00
		aes_alert_reset	13.000s	565.628us	50	50	100.00
		aes_man_cfg_err	6.000s	74.298us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	401.561us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	956.968us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	565.628us	50	50	100.00
V2	stress	aes_stress	37.000s	477.380us	50	50	100.00
V2	sideload	aes_stress	37.000s	477.380us	50	50	100.00
		aes_sideload	6.000s	85.324us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	124.896us	50	50	100.00
V2	alert_test	aes_alert_test	6.000s	53.331us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	195.889us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	195.889us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	80.229us	5	5	100.00
		aes_csr_rw	4.000s	60.719us	20	20	100.00
		aes_csr_aliasing	5.000s	712.454us	5	5	100.00
		aes_same_csr_outstanding	5.000s	103.242us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	80.229us	5	5	100.00
		aes_csr_rw	4.000s	60.719us	20	20	100.00
		aes_csr_aliasing	5.000s	712.454us	5	5	100.00
		aes_same_csr_outstanding	5.000s	103.242us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	45.000s	578.781us	48	50	96.00
V2S	fault_inject	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	434.545us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	680.753us	5	5	100.00
		aes_tl_intg_err	6.000s	485.232us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	485.232us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	565.628us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	100.864us	50	50	100.00
		aes_stress	37.000s	477.380us	50	50	100.00
		aes_alert_reset	13.000s	565.628us	50	50	100.00
		aes_core_fi	6.133m	10.007ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	120.566us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	37.000s	477.380us	50	50	100.00
		aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	37.000s	477.380us	50	50	100.00
		aes_sideload	6.000s	85.324us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	63.864us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	37.000s	477.380us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	37.000s	477.380us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	158.886us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	158.886us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	55.000s	63.018ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	158.886us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	565.628us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_ctr_fi	4.000s	76.800us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	158.886us	50	50	100.00
		aes_control_fi	46.000s	24.260ms	274	300	91.33
		aes_cipher_fi	55.000s	63.018ms	320	350	91.43
V2S		TOTAL			924	985	93.81
V3		TOTAL			0	0	--
		TOTAL			1521	1582	96.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.58	94.52	98.75	93.77	97.64	91.85	98.26	91.28

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 40 failures:
- Test aes_cipher_fi has 24 failures.
  - 6.aes_cipher_fi.4098313932
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:17138af7-05d0-4df9-bc10-e6938d91304f
```
  - 19.aes_cipher_fi.4018506248
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:84e67fc5-778b-4fbb-b5f6-64e5a58204c1
```
  - ... and 22 more failures.
- Test aes_control_fi has 16 failures.
  - 34.aes_control_fi.3473439989
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:a985566f-09d5-44e9-a8f4-14222849d2eb
```
  - 50.aes_control_fi.2197409602
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  Job ID: smart:1f4dc39b-0c11-4d13-8f5d-d5651b7e61e0
```
  - ... and 14 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_control_fi has 10 failures.

25.aes_control_fi.499313852
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log

  UVM_FATAL @ 10031692237 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031692237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.aes_control_fi.685894396
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006734183 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006734183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_cipher_fi has 6 failures.

53.aes_cipher_fi.1492965596
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10018163332 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018163332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

148.aes_cipher_fi.812395777
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/148.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10024473059 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024473059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:

Test aes_core_fi has 2 failures.

5.aes_core_fi.2140967430
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log

  UVM_FATAL @ 10040283061 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x683b5784) == 0x0
  UVM_INFO @ 10040283061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aes_core_fi.297861253
Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007424095 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd621f684) == 0x0
  UVM_INFO @ 10007424095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 2 failures:

Test aes_reseed has 2 failures.

7.aes_reseed.1706463826
Line 1499, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_reseed/latest/run.log

  UVM_FATAL @   8151445 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 8d      f1      e6      0
                 1 00      f9      2a      0

32.aes_reseed.458957825
Line 10957, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_reseed/latest/run.log

  UVM_FATAL @  46078550 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 1
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 8d      2e      38      0
                 1 00      33      86      0

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 55.aes_core_fi.2472066105
    Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017548864 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017548864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```