AES/UNMASKED Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	65.327us	1	1	100.00
V1	smoke	aes_smoke	7.000s	159.339us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	74.790us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	120.859us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	181.740us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	587.465us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	130.120us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	120.859us	20	20	100.00
		aes_csr_aliasing	4.000s	587.465us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	159.339us	50	50	100.00
		aes_config_error	9.000s	198.855us	50	50	100.00
		aes_stress	9.000s	75.694us	50	50	100.00
V2	key_length	aes_smoke	7.000s	159.339us	50	50	100.00
		aes_config_error	9.000s	198.855us	50	50	100.00
		aes_stress	9.000s	75.694us	50	50	100.00
V2	back2back	aes_stress	9.000s	75.694us	50	50	100.00
		aes_b2b	13.000s	171.186us	50	50	100.00
V2	backpressure	aes_stress	9.000s	75.694us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	159.339us	50	50	100.00
		aes_config_error	9.000s	198.855us	50	50	100.00
		aes_stress	9.000s	75.694us	50	50	100.00
		aes_alert_reset	9.000s	122.461us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	84.213us	50	50	100.00
		aes_config_error	9.000s	198.855us	50	50	100.00
		aes_alert_reset	9.000s	122.461us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	260.702us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	208.336us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	122.461us	50	50	100.00
V2	stress	aes_stress	9.000s	75.694us	50	50	100.00
V2	sideload	aes_stress	9.000s	75.694us	50	50	100.00
		aes_sideload	9.000s	78.474us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	141.826us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	3.309ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	88.640us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	129.381us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	129.381us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	74.790us	5	5	100.00
		aes_csr_rw	8.000s	120.859us	20	20	100.00
		aes_csr_aliasing	4.000s	587.465us	5	5	100.00
		aes_same_csr_outstanding	13.000s	260.577us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	74.790us	5	5	100.00
		aes_csr_rw	8.000s	120.859us	20	20	100.00
		aes_csr_aliasing	4.000s	587.465us	5	5	100.00
		aes_same_csr_outstanding	13.000s	260.577us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	9.000s	66.810us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	94.141us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.179ms	5	5	100.00
		aes_tl_intg_err	10.000s	259.203us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	259.203us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	122.461us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	159.339us	50	50	100.00
		aes_stress	9.000s	75.694us	50	50	100.00
		aes_alert_reset	9.000s	122.461us	50	50	100.00
		aes_core_fi	6.900m	10.010ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	69.441us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	202.848us	50	50	100.00
		aes_stress	9.000s	75.694us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	75.694us	50	50	100.00
		aes_sideload	9.000s	78.474us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	202.848us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	202.848us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	202.848us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	202.848us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	202.848us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	75.694us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	75.694us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	247.445us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	247.445us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	53.000s	47.763ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	247.445us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	122.461us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_ctr_fi	8.000s	129.051us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	247.445us	50	50	100.00
		aes_control_fi	50.000s	31.529ms	275	300	91.67
		aes_cipher_fi	53.000s	47.763ms	322	350	92.00
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.600m	40.983ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.28	97.56	94.48	98.87	93.67	97.64	92.59	98.66	98.17

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test aes_control_fi has 17 failures.
  - 13.aes_control_fi.92487361161344223965518402755536142837566432661046890725827017964535191380150
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:6d42dcdd-fc3c-42c1-b22e-d95ecb069895
```
  - 56.aes_control_fi.64608750963998454766658675823787551603810439679417136440484829603029137458595
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job ID: smart:0bf5f13c-5ccd-40ca-9abe-fc376f470b62
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 18 failures.
  - 22.aes_cipher_fi.70382300862308603539305996073648265735171032971011875436216571477067720112279
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6c578d87-5436-4fa9-ba15-5155d9748aeb
```
  - 38.aes_cipher_fi.87662564487687101268098778202673054640227519746960565361207412795703583342513
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  Job ID: smart:54cd9eba-5b11-40b0-bf3b-e1a399ae9a92
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 13.aes_cipher_fi.68808921233126052852384301630007819793555981817896200401330814388109249221159
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004823683 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004823683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_cipher_fi.17007900578002630163034549219790627577548066194922813580578833814431124139914
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002401649 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002401649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 85.aes_control_fi.73175492394626150402348769405523276272495313729268216620209631515475391948655
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003914946 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003914946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 128.aes_control_fi.103275395749338985105451917674069080719980957265205821257777465690678392053723
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/128.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006442193 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006442193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.55914508897777749474697831863137929191116864337497496608458948680914902706026
Line 679, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40983259289 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 40983259289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.17293839590228539483179635917503527102962461501611026809463457491349347828429
Line 838, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1624460653 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1624460653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.85096104536371588263014011265771883486264982163662234902344260481283133431484
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004413825 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004413825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_core_fi.45145709397561714519316827328164956319639893813579506991419107866222505136743
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012301639 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012301639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 17.aes_core_fi.28263872899107337453929081764892785986062267445420927163503850560438359997754
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010360106 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xae78d84) == 0x0
  UVM_INFO @ 10010360106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_core_fi.4636108954699944324990178406650397047963455232099171941514690250377925959341
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10077694648 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xcb6bea84) == 0x0
  UVM_INFO @ 10077694648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:724) virtual_sequencer [aes_alert_reset_vseq] has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.112959900848377768004342670327036356111103826468988516937053923909857863489937
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  22143456 ps: (aes_base_vseq.sv:724) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq]
       Was able to clear FATAL ALERT without reset
  
       ---| Idle:          0
       ---| Stall:         0
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

8.aes_stress_all_with_rand_reset.17223312013835243241542485667994495740498716237951850141008505185663806885447
Line 1835, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 972449810 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 972429402 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 972449810 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 972429402 PS)
  UVM_ERROR @ 972449810 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 9.aes_stress_all.114840339351330936346499020286898438312924057761734324852278331289967027366169
    Line 9502, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 486398241 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 486398241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.62970390793965703297393926461374599756024724410974811992597804699074475073419
    Line 1388, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1908498658 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1908498658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```