AES/UNMASKED Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.892us	1	1	100.00
V1	smoke	aes_smoke	8.000s	94.510us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.771us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	77.006us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	2.332ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	205.002us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	179.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	77.006us	20	20	100.00
		aes_csr_aliasing	5.000s	205.002us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	94.510us	50	50	100.00
		aes_config_error	6.000s	261.217us	50	50	100.00
		aes_stress	6.000s	84.773us	50	50	100.00
V2	key_length	aes_smoke	8.000s	94.510us	50	50	100.00
		aes_config_error	6.000s	261.217us	50	50	100.00
		aes_stress	6.000s	84.773us	50	50	100.00
V2	back2back	aes_stress	6.000s	84.773us	50	50	100.00
		aes_b2b	10.000s	203.904us	50	50	100.00
V2	backpressure	aes_stress	6.000s	84.773us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	94.510us	50	50	100.00
		aes_config_error	6.000s	261.217us	50	50	100.00
		aes_stress	6.000s	84.773us	50	50	100.00
		aes_alert_reset	8.000s	244.836us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	86.755us	50	50	100.00
		aes_config_error	6.000s	261.217us	50	50	100.00
		aes_alert_reset	8.000s	244.836us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	108.627us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	170.058us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	244.836us	50	50	100.00
V2	stress	aes_stress	6.000s	84.773us	50	50	100.00
V2	sideload	aes_stress	6.000s	84.773us	50	50	100.00
		aes_sideload	14.000s	785.163us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	472.865us	50	50	100.00
V2	stress_all	aes_stress_all	22.000s	1.296ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	51.564us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	279.533us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	279.533us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.771us	5	5	100.00
		aes_csr_rw	3.000s	77.006us	20	20	100.00
		aes_csr_aliasing	5.000s	205.002us	5	5	100.00
		aes_same_csr_outstanding	4.000s	118.096us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.771us	5	5	100.00
		aes_csr_rw	3.000s	77.006us	20	20	100.00
		aes_csr_aliasing	5.000s	205.002us	5	5	100.00
		aes_same_csr_outstanding	4.000s	118.096us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	76.194us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	218.279us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	951.146us	5	5	100.00
		aes_tl_intg_err	6.000s	122.117us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	122.117us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	244.836us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	94.510us	50	50	100.00
		aes_stress	6.000s	84.773us	50	50	100.00
		aes_alert_reset	8.000s	244.836us	50	50	100.00
		aes_core_fi	6.800m	10.010ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	235.270us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	51.968us	50	50	100.00
		aes_stress	6.000s	84.773us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	84.773us	50	50	100.00
		aes_sideload	14.000s	785.163us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	51.968us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	51.968us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	51.968us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	51.968us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	51.968us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	84.773us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	84.773us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	156.513us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	156.513us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	50.829ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	156.513us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	244.836us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_ctr_fi	13.000s	99.852us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	156.513us	49	50	98.00
		aes_control_fi	52.000s	60.602ms	275	300	91.67
		aes_cipher_fi	44.000s	50.829ms	327	350	93.43
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	13.317m	52.168ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.50	94.35	98.81	93.62	97.72	91.11	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 16 failures.
  - 0.aes_control_fi.67717001074406659570848903471851598289144741628771403606194923229012537647816
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:c6a56243-6804-4d85-b026-66fcf25e5658
```
  - 18.aes_control_fi.82972137909942267494750765739972614923604443423114163117474020392774109189396
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:819dec16-934f-44bb-ae80-603d9a206a13
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 14 failures.
  - 1.aes_cipher_fi.93845635889714754026596218840342436302165859306786341827756673942066843808058
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c809a978-4b2e-4f1d-a2f2-1143d8cb65d7
```
  - 3.aes_cipher_fi.34818953998698821455035075404297880304556155476428856068153766885401578538582
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:793c1be7-83b7-4670-895a-ff848e89833b
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 6.aes_control_fi.91190607321438103006932511913320008745138721990966952007298375955775536765892
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004776458 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004776458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_control_fi.31545500598256706780687873485089863077492942819354886096533313699579953171882
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10001831582 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001831582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 16.aes_cipher_fi.67215825334064961414566920357120660011200983675000932167918184221445383678594
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008966107 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008966107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 99.aes_cipher_fi.57355676370899141546581508040445575678661343211604374937304191507530571674012
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/99.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012990747 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012990747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.40265728329768564039909101482376382165033641705607807745589439077322425168606
Line 821, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 156559198785 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 156559198785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.88896719590931506963454157624593822906767936977535038905754203647815643009502
Line 1239, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 328888335 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 328888335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 5 failures:
- Test aes_core_fi has 5 failures.
  - 2.aes_core_fi.82552420032547098515955242011801868123732530357872359455289521408403052699149
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009994639 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x63167084) == 0x0
  UVM_INFO @ 10009994639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_core_fi.110591011569449199863412950744176810254607467123369096177913275682036034827789
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024146755 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xc11df84) == 0x0
  UVM_INFO @ 10024146755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.10203176314554241097312365752902766739408017083106653803700516717687069826096
Line 1609, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 909729842 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 909729842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.109486374866058426053654237625351975189945808127988274006447951213284720443407
Line 736, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 209273168 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 209273168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:520) [aes_fi_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_fi has 1 failures.
  - 1.aes_fi.43099838696092413761337325127301906876290347670115511207304137088102739229044
    Line 3901, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_fi/latest/run.log
```
  UVM_ERROR @  57949710 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  57949710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.101811951001382327939581800999699564645108355574926939796135291823364505520121
    Line 615, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 230519678 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 230519678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 52.aes_core_fi.55073963054760119074641847987909220506603182027466878116030228347494844204877
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10079710280 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10079710280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 55.aes_core_fi.44868354831769750032470419765021916700883365529812654110513974885174793770037
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006353396 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006353396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```