AES/UNMASKED Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 3.000s 63.608us 1 1 100.00
V1 smoke aes_smoke 9.000s 56.082us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 4.000s 68.550us 5 5 100.00
V1 csr_rw aes_csr_rw 9.000s 283.740us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 9.000s 329.995us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 9.000s 243.195us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 6.000s 63.301us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 9.000s 283.740us 20 20 100.00
aes_csr_aliasing 9.000s 243.195us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 9.000s 56.082us 50 50 100.00
aes_config_error 9.000s 117.986us 50 50 100.00
aes_stress 8.000s 66.438us 47 50 94.00
V2 key_length aes_smoke 9.000s 56.082us 50 50 100.00
aes_config_error 9.000s 117.986us 50 50 100.00
aes_stress 8.000s 66.438us 47 50 94.00
V2 back2back aes_stress 8.000s 66.438us 47 50 94.00
aes_b2b 11.000s 176.038us 50 50 100.00
V2 backpressure aes_stress 8.000s 66.438us 47 50 94.00
V2 multi_message aes_smoke 9.000s 56.082us 50 50 100.00
aes_config_error 9.000s 117.986us 50 50 100.00
aes_stress 8.000s 66.438us 47 50 94.00
aes_alert_reset 10.000s 77.382us 49 50 98.00
V2 failure_test aes_man_cfg_err 8.000s 91.043us 50 50 100.00
aes_config_error 9.000s 117.986us 50 50 100.00
aes_alert_reset 10.000s 77.382us 49 50 98.00
V2 trigger_clear_test aes_clear 12.000s 243.514us 48 50 96.00
V2 nist_test_vectors aes_nist_vectors 6.000s 200.667us 1 1 100.00
V2 reset_recovery aes_alert_reset 10.000s 77.382us 49 50 98.00
V2 stress aes_stress 8.000s 66.438us 47 50 94.00
V2 sideload aes_stress 8.000s 66.438us 47 50 94.00
aes_sideload 10.000s 62.300us 50 50 100.00
V2 deinitialization aes_deinit 10.000s 374.637us 49 50 98.00
V2 stress_all aes_stress_all 34.000s 2.154ms 10 10 100.00
V2 alert_test aes_alert_test 8.000s 96.881us 49 50 98.00
V2 tl_d_oob_addr_access aes_tl_errors 11.000s 435.631us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 11.000s 435.631us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 4.000s 68.550us 5 5 100.00
aes_csr_rw 9.000s 283.740us 20 20 100.00
aes_csr_aliasing 9.000s 243.195us 5 5 100.00
aes_same_csr_outstanding 9.000s 150.956us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 4.000s 68.550us 5 5 100.00
aes_csr_rw 9.000s 283.740us 20 20 100.00
aes_csr_aliasing 9.000s 243.195us 5 5 100.00
aes_same_csr_outstanding 9.000s 150.956us 20 20 100.00
V2 TOTAL 493 501 98.40
V2S reseeding aes_reseed 10.000s 122.096us 49 50 98.00
V2S fault_inject aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
V2S shadow_reg_update_error aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 8.000s 79.655us 20 20 100.00
V2S tl_intg_err aes_sec_cm 7.000s 848.864us 5 5 100.00
aes_tl_intg_err 11.000s 603.335us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 11.000s 603.335us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 10.000s 77.382us 49 50 98.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 9.000s 56.082us 50 50 100.00
aes_stress 8.000s 66.438us 47 50 94.00
aes_alert_reset 10.000s 77.382us 49 50 98.00
aes_core_fi 40.000s 10.009ms 65 70 92.86
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 10.000s 57.050us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 10.000s 62.075us 48 50 96.00
aes_stress 8.000s 66.438us 47 50 94.00
V2S sec_cm_key_sideload aes_stress 8.000s 66.438us 47 50 94.00
aes_sideload 10.000s 62.300us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 10.000s 62.075us 48 50 96.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 10.000s 62.075us 48 50 96.00
V2S sec_cm_key_sec_wipe aes_readability 10.000s 62.075us 48 50 96.00
V2S sec_cm_iv_config_sec_wipe aes_readability 10.000s 62.075us 48 50 96.00
V2S sec_cm_data_reg_sec_wipe aes_readability 10.000s 62.075us 48 50 96.00
V2S sec_cm_data_reg_key_sca aes_stress 8.000s 66.438us 47 50 94.00
V2S sec_cm_key_masking aes_stress 8.000s 66.438us 47 50 94.00
V2S sec_cm_main_fsm_sparse aes_fi 10.000s 101.479us 48 50 96.00
V2S sec_cm_main_fsm_redun aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_cipher_fsm_sparse aes_fi 10.000s 101.479us 48 50 96.00
V2S sec_cm_cipher_fsm_redun aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 51.000s 26.729ms 319 350 91.14
V2S sec_cm_ctr_fsm_sparse aes_fi 10.000s 101.479us 48 50 96.00
V2S sec_cm_ctr_fsm_redun aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_ctrl_sparse aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 10.000s 77.382us 49 50 98.00
V2S sec_cm_main_fsm_local_esc aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_ctr_fi 15.000s 10.009ms 49 50 98.00
V2S sec_cm_data_reg_local_esc aes_fi 10.000s 101.479us 48 50 96.00
aes_control_fi 47.000s 10.002ms 273 300 91.00
aes_cipher_fi 51.000s 26.729ms 319 350 91.14
V2S TOTAL 916 985 92.99
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 17.617m 197.248ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1515 1602 94.57

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 8 61.54
V2S 11 11 4 36.36
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.21 97.49 94.31 98.83 93.59 97.72 91.11 98.85 97.36

Failure Buckets

Past Results