AES/UNMASKED Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	51.099us	1	1	100.00
V1	smoke	aes_smoke	5.000s	394.243us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	98.133us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	193.222us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	2.495ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	179.050us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	87.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	193.222us	20	20	100.00
		aes_csr_aliasing	5.000s	179.050us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	394.243us	50	50	100.00
		aes_config_error	6.000s	138.522us	50	50	100.00
		aes_stress	9.000s	103.538us	50	50	100.00
V2	key_length	aes_smoke	5.000s	394.243us	50	50	100.00
		aes_config_error	6.000s	138.522us	50	50	100.00
		aes_stress	9.000s	103.538us	50	50	100.00
V2	back2back	aes_stress	9.000s	103.538us	50	50	100.00
		aes_b2b	12.000s	262.305us	50	50	100.00
V2	backpressure	aes_stress	9.000s	103.538us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	394.243us	50	50	100.00
		aes_config_error	6.000s	138.522us	50	50	100.00
		aes_stress	9.000s	103.538us	50	50	100.00
		aes_alert_reset	9.000s	255.048us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	91.189us	50	50	100.00
		aes_config_error	6.000s	138.522us	50	50	100.00
		aes_alert_reset	9.000s	255.048us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	320.255us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	224.332us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	255.048us	50	50	100.00
V2	stress	aes_stress	9.000s	103.538us	50	50	100.00
V2	sideload	aes_stress	9.000s	103.538us	50	50	100.00
		aes_sideload	5.000s	62.299us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	96.678us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	1.983ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	67.389us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	168.303us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	168.303us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	98.133us	5	5	100.00
		aes_csr_rw	4.000s	193.222us	20	20	100.00
		aes_csr_aliasing	5.000s	179.050us	5	5	100.00
		aes_same_csr_outstanding	8.000s	102.432us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	98.133us	5	5	100.00
		aes_csr_rw	4.000s	193.222us	20	20	100.00
		aes_csr_aliasing	5.000s	179.050us	5	5	100.00
		aes_same_csr_outstanding	8.000s	102.432us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	240.339us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	95.237us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.645ms	5	5	100.00
		aes_tl_intg_err	5.000s	229.327us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	229.327us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	255.048us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	394.243us	50	50	100.00
		aes_stress	9.000s	103.538us	50	50	100.00
		aes_alert_reset	9.000s	255.048us	50	50	100.00
		aes_core_fi	40.000s	10.008ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	65.041us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	57.041us	50	50	100.00
		aes_stress	9.000s	103.538us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	103.538us	50	50	100.00
		aes_sideload	5.000s	62.299us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	57.041us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	57.041us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	57.041us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	57.041us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	57.041us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	103.538us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	103.538us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	234.445us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	234.445us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	65.651ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	234.445us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	255.048us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_ctr_fi	4.000s	126.638us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	234.445us	49	50	98.00
		aes_control_fi	48.000s	63.002ms	275	300	91.67
		aes_cipher_fi	49.000s	65.651ms	327	350	93.43
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.700m	37.069ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	97.58	94.52	98.83	93.85	97.72	91.11	98.85	98.58

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_control_fi has 16 failures.
  - 15.aes_control_fi.45125655809326694472787785106221488809061396558743271235305149856325525596348
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:4035eaa0-ae92-464c-8c7d-b09d8744f84c
```
  - 22.aes_control_fi.66886313309137346995459515036542938553991158584788973664070426415017523203827
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:69b3774c-3036-4e44-ab96-79b71eeddd7a
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 11 failures.
  - 21.aes_cipher_fi.54544459557046804107392010014452718884585968399023436400675387769610374471053
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a5ded835-1ffc-459a-8888-7fc36aadef63
```
  - 34.aes_cipher_fi.47103014753106491370471059840669254615839425939988643271435162877370215646020
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c537ebcd-5776-41de-847f-cf78d2c8e255
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 12.aes_cipher_fi.10873228022216034061600133784861663998766541418526915761111184966189423406728
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012385259 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012385259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_cipher_fi.53056787437098635263366347399205188926212532179023317594670376258560873984214
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036935242 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036935242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 3.aes_control_fi.11697736779373751099481153563175582943271767038446647747126352754329892372425
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019538127 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019538127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_control_fi.54377127931303000295238805578379614976804829426196532414168304126652828819527
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004499582 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004499582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.52400479225885289215956217255977295211040856207555012574068278506452492236837
Line 381, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 446960876 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 446960876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.77651677534876445867195189739248403932848868554855483648555677782206160899488
Line 386, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4278452383 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4278452383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 0.aes_core_fi.61203126797332614427141278014258129671971129510173163905816595890685436904123
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012366522 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012366522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_core_fi.16897016048915566260447468596260561854800221515536633305509140529593943900341
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007737854 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007737854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.46165895489371920258803090658885914121436100049776184312732792133608165864273
Line 1486, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 940810569 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 940810569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.76941211745043971529360221864814096468670009359439438963857932510679922493330
Line 783, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3279697138 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3279697138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:724) virtual_sequencer [aes_reseed_vseq] has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.13943460869978898854683501630082690131569535113040409593332982946196962095399
    Line 347, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  22159417 ps: (aes_base_vseq.sv:724) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq]
       Was able to clear FATAL ALERT without reset
  
       ---| Idle:          0
       ---| Stall:         0
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 12.aes_fi.5330541051113474574819072028651561654107213112834701857833842289846111361402
    Line 3186, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 18998405 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 18978405 PS)
  UVM_ERROR @  18998405 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  18998405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 36.aes_core_fi.49929433160516377581423693036524610741893133729654078065042168179640910902632
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011098017 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011098017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```