AES/UNMASKED Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	72.786us	1	1	100.00
V1	smoke	aes_smoke	4.000s	143.888us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	74.740us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	140.941us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	860.471us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	1.402ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	109.863us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	140.941us	20	20	100.00
		aes_csr_aliasing	6.000s	1.402ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	143.888us	50	50	100.00
		aes_config_error	6.000s	131.166us	50	50	100.00
		aes_stress	6.000s	603.980us	50	50	100.00
V2	key_length	aes_smoke	4.000s	143.888us	50	50	100.00
		aes_config_error	6.000s	131.166us	50	50	100.00
		aes_stress	6.000s	603.980us	50	50	100.00
V2	back2back	aes_stress	6.000s	603.980us	50	50	100.00
		aes_b2b	10.000s	116.039us	50	50	100.00
V2	backpressure	aes_stress	6.000s	603.980us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	143.888us	50	50	100.00
		aes_config_error	6.000s	131.166us	50	50	100.00
		aes_stress	6.000s	603.980us	50	50	100.00
		aes_alert_reset	6.000s	796.490us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	56.197us	50	50	100.00
		aes_config_error	6.000s	131.166us	50	50	100.00
		aes_alert_reset	6.000s	796.490us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	264.363us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	472.328us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	796.490us	50	50	100.00
V2	stress	aes_stress	6.000s	603.980us	50	50	100.00
V2	sideload	aes_stress	6.000s	603.980us	50	50	100.00
		aes_sideload	5.000s	74.232us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	260.690us	50	50	100.00
V2	stress_all	aes_stress_all	44.000s	11.099ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	229.194us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	355.212us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	355.212us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	74.740us	5	5	100.00
		aes_csr_rw	3.000s	140.941us	20	20	100.00
		aes_csr_aliasing	6.000s	1.402ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	96.251us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	74.740us	5	5	100.00
		aes_csr_rw	3.000s	140.941us	20	20	100.00
		aes_csr_aliasing	6.000s	1.402ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	96.251us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	77.768us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	155.584us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	2.039ms	5	5	100.00
		aes_tl_intg_err	6.000s	681.997us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	681.997us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	796.490us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	143.888us	50	50	100.00
		aes_stress	6.000s	603.980us	50	50	100.00
		aes_alert_reset	6.000s	796.490us	50	50	100.00
		aes_core_fi	6.567m	10.018ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	56.802us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	127.520us	50	50	100.00
		aes_stress	6.000s	603.980us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	603.980us	50	50	100.00
		aes_sideload	5.000s	74.232us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	127.520us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	127.520us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	127.520us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	127.520us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	127.520us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	603.980us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	603.980us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	211.698us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	211.698us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.002ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	211.698us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	796.490us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_ctr_fi	4.000s	87.707us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	211.698us	48	50	96.00
		aes_control_fi	49.000s	31.529ms	276	300	92.00
		aes_cipher_fi	50.000s	10.002ms	322	350	92.00
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.250m	10.887ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1535	1602	95.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.26	97.58	94.52	98.81	93.76	97.72	91.11	98.66	97.57

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_control_fi has 19 failures.
  - 8.aes_control_fi.96576722209212353547019571965777558824803648010903066741065957524544152540643
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:9dcf3453-98d3-415e-9aec-c5274fa64a49
```
  - 30.aes_control_fi.62919784308293794134514908860745119458429939527506045222552518780826314484525
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:5d170969-5eea-4256-ac50-2527c689053f
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 15 failures.
  - 53.aes_cipher_fi.64824722805936669165774927457729874912516345683906385490992124495409943987303
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c4a0407a-d8e4-4042-b878-28b47bcd122b
```
  - 68.aes_cipher_fi.16155898160254108850128743863592817926081302436840333918464909890094513882467
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d73f5cf3-50f1-4962-aafe-233e976afedf
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 16.aes_cipher_fi.3090264397003466333018107729180745625647880348597208594855194654048061079294
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004142628 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004142628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_cipher_fi.29927202906669449620828507683787201741729734730348976503029495969248911374785
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002086903 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002086903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.24071141286613995357515191118540852548825023536794976474630589818815646378577
Line 1060, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1421659366 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1421659366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.112235370002063197943869657099306353318767171349859020656336172356357134791060
Line 753, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 144326345 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 144326345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 28.aes_control_fi.96182233228665597795565425162847089020351539001520278597150924550266729800376
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005711416 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005711416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_control_fi.78905502542325766096994797030769969003704415392463476760562257702966618976278
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015343288 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015343288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.57212471103877410173528695992206211059482065056083059319852853927821719662345
Line 1354, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2386234784 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2386234784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.91972417202351816555980994323667389455813208735378542462714536522727602804303
Line 894, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10886856908 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10886856908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

17.aes_fi.108950854080295119241675909956546605439873526632619359268003058398012253491657
Line 3197, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 33170306 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 33130306 PS)
  UVM_ERROR @  33170306 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  33170306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.aes_fi.72019968050121482278409992106154522116039193457618161092553548515091148759073
Line 1793, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 55399525 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 55288414 PS)
  UVM_ERROR @  55399525 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  55399525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 31.aes_core_fi.107305333640475104322451916936245024956398865128970508410889913719078848380077
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003647165 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003647165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_core_fi.98682175141996922910569498878106645890924158154422158746717724298391335757033
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014602473 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014602473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.27409823703102404116939096982653941037618415196848642944904299563853928948712
    Line 474, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2461324458 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2461324458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 23.aes_core_fi.45186931024504262813865524230968406049880783973389177979642225503684437958400
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017959594 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x50dbbd84) == 0x0
  UVM_INFO @ 10017959594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```