30db5a999| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.500s | 526.407us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.380s | 1.076ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.390s | 505.733us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 22.940s | 10.856ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.650s | 601.609us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.510s | 593.008us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.390s | 505.733us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.650s | 601.609us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.000s | 309.099us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.250s | 516.719us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 51.820s | 37.673ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.610s | 575.818us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 10.943m | 404.593ms | 49 | 50 | 98.00 |
| V2 | intr_test | aon_timer_intr_test | 1.330s | 478.858us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.320s | 594.446us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.320s | 594.446us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.380s | 1.076ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.390s | 505.733us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.650s | 601.609us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.580s | 2.566ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.380s | 1.076ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.390s | 505.733us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.650s | 601.609us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.580s | 2.566ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 4.250s | 7.963ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 12.940s | 7.881ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 12.940s | 7.881ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 25.363m | 151.062ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 428 | 430 | 99.53 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.46 | 99.82 | 94.68 | 100.00 | -- | 99.35 | 100.00 | 96.90 |
UVM_ERROR (aon_timer_scoreboard.sv:355) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
22.aon_timer_stress_all.2754155749
Line 228, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all/latest/run.log
UVM_ERROR @ 2152460088 ps: (aon_timer_scoreboard.sv:355) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2152460088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
26.aon_timer_stress_all_with_rand_reset.729428224
Line 287, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2133888439 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2133888439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---