AON_TIMER Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.510s	592.983us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.420s	1.102ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.460s	479.205us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	29.840s	11.482ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.730s	521.889us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	567.758us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.460s	479.205us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	521.889us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.820s	455.893us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.080s	384.065us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.539m	54.383ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	536.265us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.050m	441.314ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	501.910us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.670s	962.311us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.670s	962.311us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.420s	1.102ms	5	5	100.00
		aon_timer_csr_rw	1.460s	479.205us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	521.889us	5	5	100.00
		aon_timer_same_csr_outstanding	3.990s	2.204ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.420s	1.102ms	5	5	100.00
		aon_timer_csr_rw	1.460s	479.205us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	521.889us	5	5	100.00
		aon_timer_same_csr_outstanding	3.990s	2.204ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	10.820s	7.503ms	5	5	100.00
		aon_timer_tl_intg_err	15.130s	8.403ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.130s	8.403ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.815m	2.330s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			429	430	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.61	99.82	95.32	100.00	--	99.35	100.00	97.16

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:360) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
  • Test aon_timer_stress_all has 1 failures.

    • 9.aon_timer_stress_all.47180203270811109334539526648279177873673889345909638881942183830246541164055
      Line 267, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all/latest/run.log

        UVM_ERROR @ 775602838 ps: (aon_timer_scoreboard.sv:360) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 775602838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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