V1 |
smoke |
clkmgr_smoke |
1.450s |
275.562us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
clkmgr_csr_hw_reset |
0.870s |
68.314us |
5 |
5 |
100.00 |
V1 |
csr_rw |
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
clkmgr_csr_bit_bash |
11.700s |
1.937ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
clkmgr_csr_aliasing |
2.020s |
217.226us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
clkmgr_csr_mem_rw_with_rand_reset |
1.980s |
105.209us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.020s |
217.226us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
peri_enables |
clkmgr_peri |
1.100s |
171.357us |
50 |
50 |
100.00 |
V2 |
trans_enables |
clkmgr_trans |
1.900s |
400.791us |
50 |
50 |
100.00 |
V2 |
extclk |
clkmgr_extclk |
1.540s |
283.633us |
50 |
50 |
100.00 |
V2 |
clk_status |
clkmgr_clk_status |
0.930s |
79.077us |
50 |
50 |
100.00 |
V2 |
jitter |
clkmgr_smoke |
1.450s |
275.562us |
50 |
50 |
100.00 |
V2 |
frequency |
clkmgr_frequency |
18.140s |
2.477ms |
50 |
50 |
100.00 |
V2 |
frequency_timeout |
clkmgr_frequency_timeout |
16.430s |
2.302ms |
50 |
50 |
100.00 |
V2 |
frequency_overflow |
clkmgr_frequency |
18.140s |
2.477ms |
50 |
50 |
100.00 |
V2 |
stress_all |
clkmgr_stress_all |
1.903m |
16.321ms |
50 |
50 |
100.00 |
V2 |
intr_test |
clkmgr_intr_test |
0.840s |
113.672us |
50 |
50 |
100.00 |
V2 |
alert_test |
clkmgr_alert_test |
1.310s |
211.005us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
clkmgr_tl_errors |
4.650s |
619.409us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
clkmgr_tl_errors |
4.650s |
619.409us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
clkmgr_csr_hw_reset |
0.870s |
68.314us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.020s |
217.226us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.810s |
208.107us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
clkmgr_csr_hw_reset |
0.870s |
68.314us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.020s |
217.226us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.810s |
208.107us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
490 |
490 |
100.00 |
V2S |
tl_intg_err |
clkmgr_sec_cm |
3.600s |
688.376us |
5 |
5 |
100.00 |
|
|
clkmgr_tl_intg_err |
5.980s |
1.416ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error |
clkmgr_shadow_reg_errors |
6.630s |
1.952ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_read_clear_staged_value |
clkmgr_shadow_reg_errors |
6.630s |
1.952ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_storage_error |
clkmgr_shadow_reg_errors |
6.630s |
1.952ms |
20 |
20 |
100.00 |
V2S |
shadowed_reset_glitch |
clkmgr_shadow_reg_errors |
6.630s |
1.952ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error_with_csr_rw |
clkmgr_shadow_reg_errors_with_csr_rw |
5.170s |
1.004ms |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
clkmgr_tl_intg_err |
5.980s |
1.416ms |
20 |
20 |
100.00 |
V2S |
sec_cm_meas_clk_bkgn_chk |
clkmgr_frequency |
18.140s |
2.477ms |
50 |
50 |
100.00 |
V2S |
sec_cm_timeout_clk_bkgn_chk |
clkmgr_frequency_timeout |
16.430s |
2.302ms |
50 |
50 |
100.00 |
V2S |
sec_cm_meas_config_shadow |
clkmgr_shadow_reg_errors |
6.630s |
1.952ms |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_intersig_mubi |
clkmgr_idle_intersig_mubi |
1.890s |
387.554us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
clkmgr_lc_ctrl_intersig_mubi |
1.390s |
251.239us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_clk_handshake_intersig_mubi |
clkmgr_lc_clk_byp_req_intersig_mubi |
1.640s |
332.913us |
50 |
50 |
100.00 |
V2S |
sec_cm_clk_handshake_intersig_mubi |
clkmgr_clk_handshake_intersig_mubi |
1.740s |
363.244us |
50 |
50 |
100.00 |
V2S |
sec_cm_div_intersig_mubi |
clkmgr_div_intersig_mubi |
1.600s |
307.736us |
50 |
50 |
100.00 |
V2S |
sec_cm_jitter_config_mubi |
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_ctr_redun |
clkmgr_sec_cm |
3.600s |
688.376us |
5 |
5 |
100.00 |
V2S |
sec_cm_meas_config_regwen |
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
V2S |
sec_cm_clk_ctrl_config_regwen |
clkmgr_csr_rw |
0.950s |
58.028us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
clkmgr_sec_cm |
3.600s |
688.376us |
5 |
5 |
100.00 |
V2S |
|
TOTAL |
|
|
315 |
315 |
100.00 |
V3 |
stress_all_with_rand_reset |
clkmgr_stress_all_with_rand_reset |
21.138m |
196.036ms |
49 |
50 |
98.00 |
V3 |
|
TOTAL |
|
|
49 |
50 |
98.00 |
|
|
TOTAL |
|
|
959 |
960 |
99.90 |