748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 1.690s | 346.662us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 1.120s | 170.543us | 4 | 5 | 80.00 |
| V1 | csr_rw | clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 22.110s | 6.795ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | clkmgr_csr_aliasing | 2.260s | 294.736us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 1.680s | 73.439us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 |
| clkmgr_csr_aliasing | 2.260s | 294.736us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 101 | 105 | 96.19 | |||
| V2 | peri_enables | clkmgr_peri | 0.900s | 79.634us | 48 | 50 | 96.00 |
| V2 | trans_enables | clkmgr_trans | 1.490s | 214.587us | 50 | 50 | 100.00 |
| V2 | extclk | clkmgr_extclk | 1.400s | 219.597us | 50 | 50 | 100.00 |
| V2 | clk_status | clkmgr_clk_status | 1.050s | 151.312us | 50 | 50 | 100.00 |
| V2 | jitter | clkmgr_smoke | 1.690s | 346.662us | 50 | 50 | 100.00 |
| V2 | frequency | clkmgr_frequency | 17.200s | 2.242ms | 50 | 50 | 100.00 |
| V2 | frequency_timeout | clkmgr_frequency_timeout | 15.920s | 2.296ms | 50 | 50 | 100.00 |
| V2 | frequency_overflow | clkmgr_frequency | 17.200s | 2.242ms | 50 | 50 | 100.00 |
| V2 | stress_all | clkmgr_stress_all | 1.653m | 13.155ms | 49 | 50 | 98.00 |
| V2 | intr_test | clkmgr_intr_test | 0.770s | 78.134us | 49 | 50 | 98.00 |
| V2 | alert_test | clkmgr_alert_test | 1.090s | 112.414us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 4.510s | 1.092ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 4.510s | 1.092ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 1.120s | 170.543us | 4 | 5 | 80.00 |
| clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 | ||
| clkmgr_csr_aliasing | 2.260s | 294.736us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 1.840s | 307.802us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 1.120s | 170.543us | 4 | 5 | 80.00 |
| clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 | ||
| clkmgr_csr_aliasing | 2.260s | 294.736us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 1.840s | 307.802us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 484 | 490 | 98.78 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 3.760s | 629.990us | 5 | 5 | 100.00 |
| clkmgr_tl_intg_err | 6.450s | 1.787ms | 20 | 20 | 100.00 | ||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 2.450s | 367.315us | 19 | 20 | 95.00 |
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 2.450s | 367.315us | 19 | 20 | 95.00 |
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 2.450s | 367.315us | 19 | 20 | 95.00 |
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 2.450s | 367.315us | 19 | 20 | 95.00 |
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 3.620s | 538.503us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 6.450s | 1.787ms | 20 | 20 | 100.00 |
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 17.200s | 2.242ms | 50 | 50 | 100.00 |
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 15.920s | 2.296ms | 50 | 50 | 100.00 |
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 2.450s | 367.315us | 19 | 20 | 95.00 |
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 1.690s | 285.851us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 1.530s | 257.592us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 1.450s | 244.599us | 49 | 50 | 98.00 |
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 1.360s | 175.185us | 50 | 50 | 100.00 |
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 1.230s | 154.665us | 50 | 50 | 100.00 |
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 |
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 3.760s | 629.990us | 5 | 5 | 100.00 |
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 |
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 1.050s | 132.150us | 19 | 20 | 95.00 |
| V2S | prim_count_check | clkmgr_sec_cm | 3.760s | 629.990us | 5 | 5 | 100.00 |
| V2S | TOTAL | 313 | 315 | 99.37 | |||
| V3 | regwen | clkmgr_regwen | 7.020s | 1.344ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 31.098m | 409.685ms | 48 | 50 | 96.00 |
| V3 | TOTAL | 98 | 100 | 98.00 | |||
| TOTAL | 996 | 1010 | 98.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 3 | 50.00 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 9 | 9 | 7 | 77.78 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.52 | 99.15 | 95.84 | 100.00 | 100.00 | 98.81 | 97.01 | 98.80 |
Exit reason: Error: User command failed Job returned non-zero exit code has 9 failures:
Test clkmgr_same_csr_outstanding has 2 failures.
2.clkmgr_same_csr_outstanding.90808653757384432918830260685083016021853176461178973574363361539210876507835
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/2.clkmgr_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792155835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.792155835
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.clkmgr_same_csr_outstanding.95136107911913565856581987156882696656452774208321207532828192997588471387447
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/4.clkmgr_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796374839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.3796374839
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_csr_mem_rw_with_rand_reset has 2 failures.
2.clkmgr_csr_mem_rw_with_rand_reset.96139671871673673750072351949557282736613871494955230678874997906816363139039
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292294623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.292294623
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
16.clkmgr_csr_mem_rw_with_rand_reset.54587283363854884025600762450829265133258005749871438496112920032392092443191
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823152183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.2823152183
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_csr_hw_reset has 1 failures.
3.clkmgr_csr_hw_reset.75374394418776630026585946986410471108284064941211185105918648422437495769698
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/3.clkmgr_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700165218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.3700165218
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_shadow_reg_errors has 1 failures.
16.clkmgr_shadow_reg_errors.105628628951199689645348988671774151651069693898055599908832787407589685072430
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest/run.log
[make]: simulate
cd /workspace/16.clkmgr_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686456366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.2686456366
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_csr_rw has 1 failures.
18.clkmgr_csr_rw.94906910534421825270192596228810105339541819917453056742449623892641990665226
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest/run.log
[make]: simulate
cd /workspace/18.clkmgr_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106863114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.1106863114
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more tests.
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 3 failures:
Test clkmgr_peri has 2 failures.
31.clkmgr_peri.51870029886159189764672707327495551939823802506804998754114723687085608877262
Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_peri/latest/run.log
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
UVM_ERROR @ 1581148 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
UVM_INFO @ 1581148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.clkmgr_peri.11920975670571169967735151170002783516004886650256588525909267183959030017936
Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_peri/latest/run.log
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
UVM_ERROR @ 1563000 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
UVM_INFO @ 1563000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test clkmgr_stress_all_with_rand_reset has 1 failures.
40.clkmgr_stress_all_with_rand_reset.32226828973657923924105162575649136630134596182779560633349252678552462004579
Line 469, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
UVM_ERROR @ 5081296266 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
UVM_INFO @ 5081296266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 2 failures:
Test clkmgr_stress_all_with_rand_reset has 1 failures.
33.clkmgr_stress_all_with_rand_reset.60499203339643481956953223932050157523095785344656122856283613679682181481170
Line 644, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 11688503226 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 11688503226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test clkmgr_stress_all has 1 failures.
36.clkmgr_stress_all.7602594532027376596446158475306855305472732873691883639557792383906574980312
Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 17097210 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 17097210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---