CSRNG Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	224.730us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	15.091us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	14.629us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	450.185us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	75.969us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	291.015us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	14.629us	20	20	100.00
		csrng_csr_aliasing	5.000s	75.969us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	310.690us	200	200	100.00
V2	alerts	csrng_alert	8.000s	395.974us	500	500	100.00
V2	err	csrng_err	6.000s	27.758us	490	500	98.00
V2	cmds	csrng_cmds	1.217m	6.876ms	50	50	100.00
V2	life cycle	csrng_cmds	1.217m	6.876ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.383m	2.443ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	42.969us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	36.890us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.755ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.755ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	15.091us	5	5	100.00
		csrng_csr_rw	4.000s	14.629us	20	20	100.00
		csrng_csr_aliasing	5.000s	75.969us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	163.746us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	15.091us	5	5	100.00
		csrng_csr_rw	4.000s	14.629us	20	20	100.00
		csrng_csr_aliasing	5.000s	75.969us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	163.746us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	7.000s	37.222us	5	5	100.00
		csrng_tl_intg_err	10.000s	435.312us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	40.351us	50	50	100.00
		csrng_csr_rw	4.000s	14.629us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	395.974us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.383m	2.443ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	395.974us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.383m	2.443ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	395.974us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	435.312us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
		csrng_sec_cm	7.000s	37.222us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	310.690us	200	200	100.00
		csrng_err	6.000s	27.758us	490	500	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.097h	48.712ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			1614	1670	96.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.80	93.32	84.23	95.38	86.43	92.29	98.18	97.50	95.40

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 28 failures:
- Test csrng_stress_all_with_rand_reset has 28 failures.
  - 0.csrng_stress_all_with_rand_reset.3965216491
    Line 253, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003090610 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x3687bc14) == 0x6
  UVM_INFO @ 10003090610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.311673687
    Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10002069663 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xaccdd714) == 0x6
  UVM_INFO @ 10002069663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 11 failures:
- Test csrng_stress_all_with_rand_reset has 11 failures.
  - 2.csrng_stress_all_with_rand_reset.2576272188
    Line 259, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003968872 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xb070fd14) == 0x6
  UVM_INFO @ 10003968872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.1129033684
    Line 229, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012189003 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xa3279a94) == 0x6
  UVM_INFO @ 10012189003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

14.csrng_err.858527310
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1762028 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1762028 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1762028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.csrng_err.3332354095
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3220951 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3220951 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3220951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 4 failures:

Test csrng_stress_all_with_rand_reset has 4 failures.

4.csrng_stress_all_with_rand_reset.3588422808
Line 231, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 3069816 PS + 12
  Verilog Stack Trace:

16.csrng_stress_all_with_rand_reset.3940640575
Line 248, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 3479715823 PS + 14
  Verilog Stack Trace:

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

25.csrng_stress_all.2143506344
Line 272, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log

  UVM_ERROR @ 806146699 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 806146699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.csrng_stress_all.4017528694
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all/latest/run.log

  UVM_ERROR @ 2223376466 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2223376466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

58.csrng_err.2585017670
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/58.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8986352 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8986352 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8986352 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8986352 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8986352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

225.csrng_err.1190523233
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/225.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 10026995 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 10026995 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 10026995 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  10026995 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  10026995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 45.csrng_stress_all_with_rand_reset.4260060924
    Line 229, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   5241733 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @   5241733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```