1522c8119| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 9.000s | 108.897us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 102.219us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 6.000s | 57.140us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 20.000s | 1.452ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 7.000s | 99.169us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 8.000s | 40.407us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 6.000s | 57.140us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 7.000s | 99.169us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 12.000s | 648.568us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 |
| V2 | cmds | csrng_cmds | 13.883m | 90.195ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 13.883m | 90.195ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 23.417m | 137.233ms | 47 | 50 | 94.00 |
| V2 | intr_test | csrng_intr_test | 7.000s | 37.205us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 8.000s | 33.806us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 13.000s | 348.643us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 13.000s | 348.643us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 102.219us | 5 | 5 | 100.00 |
| csrng_csr_rw | 6.000s | 57.140us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 99.169us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 7.000s | 118.306us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 102.219us | 5 | 5 | 100.00 |
| csrng_csr_rw | 6.000s | 57.140us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 99.169us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 7.000s | 118.306us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1420 | 1440 | 98.61 | |||
| V2S | tl_intg_err | csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 16.000s | 314.010us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 7.000s | 38.300us | 50 | 50 | 100.00 |
| csrng_csr_rw | 6.000s | 57.140us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 12.000s | 648.568us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 23.417m | 137.233ms | 47 | 50 | 94.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 12.000s | 648.568us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 23.417m | 137.233ms | 47 | 50 | 94.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 12.000s | 648.568us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 16.000s | 314.010us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 9.000s | 135.842us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 9.000s | 159.069us | 200 | 200 | 100.00 |
| csrng_err | 13.000s | 31.157us | 483 | 500 | 96.60 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 2.371h | 244.850ms | 37 | 50 | 74.00 |
| V3 | TOTAL | 37 | 50 | 74.00 | |||
| TOTAL | 1637 | 1670 | 98.02 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 7 | 77.78 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.74 | 93.22 | 84.27 | 95.33 | 86.43 | 92.29 | 100.00 | 97.50 | 95.28 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:
22.csrng_err.2379492107
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6307147 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6307147 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6307147 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 6307147 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 6307147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
161.csrng_err.3764119123
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/161.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3636743 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3636743 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3636743 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 3636743 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 3636743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 6 more failures.
UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:
6.csrng_stress_all_with_rand_reset.3900527902
Line 807, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 131026626218 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 131026626218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.csrng_stress_all_with_rand_reset.2106605142
Line 446, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 26637146275 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
UVM_INFO @ 26637146275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:
138.csrng_err.3846725082
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/138.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 27404960 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 27404960 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 27404960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
149.csrng_err.835130727
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/149.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 8938410 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 8938410 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 8938410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 4 failures:
10.csrng_stress_all_with_rand_reset.703988029
Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3962366323 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 3962366323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.csrng_stress_all_with_rand_reset.1687553073
Line 782, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 149839148293 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 149839148293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
13.csrng_err.2866335398
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 13.csrng_err.2866335398
coverage files:
model(design data) : /workspace/coverage/default/13.csrng_err.2866335398/icc_238a3628_24e48c5b.ucm
data : /workspace/coverage/default/13.csrng_err.2866335398/icc_238a3628_24e48c5b.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Oct 04, 2023 at 13:27:40 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:172: simulate] Error 1
248.csrng_err.2203231673
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/248.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 248.csrng_err.2203231673
coverage files:
model(design data) : /workspace/coverage/default/248.csrng_err.2203231673/icc_238a3628_24e48c5b.ucm
data : /workspace/coverage/default/248.csrng_err.2203231673/icc_238a3628_24e48c5b.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Oct 04, 2023 at 13:22:13 PDT (total: 00:00:07)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:172: simulate] Error 1
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:
1.csrng_stress_all_with_rand_reset.2117786575
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
Time: 23182252 PS + 12
Verilog Stack Trace:
28.csrng_stress_all_with_rand_reset.2167311699
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
Time: 16381429 PS + 11
Verilog Stack Trace:
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
13.csrng_stress_all_with_rand_reset.271483018
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e835ff87-b091-4d85-bc7a-349846507b2f
30.csrng_stress_all_with_rand_reset.2828937181
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9e04e460-d0b5-47aa-83d8-a8bffafdb279
UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
15.csrng_stress_all.2815771074
Line 279, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
UVM_ERROR @ 8073172200 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 8073172200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.csrng_stress_all.443306608
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log
UVM_ERROR @ 5591704659 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 5591704659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
12.csrng_stress_all.3372398192
Line 265, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
UVM_ERROR @ 62421530 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 62421530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---