CSRNG Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	24.580us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	8.000s	21.947us	5	5	100.00
V1	csr_rw	csrng_csr_rw	13.000s	23.861us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	1.167ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	106.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	21.504us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	13.000s	23.861us	20	20	100.00
		csrng_csr_aliasing	9.000s	106.020us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	37.853us	200	200	100.00
V2	alerts	csrng_alert	19.000s	51.907us	500	500	100.00
V2	err	csrng_err	13.000s	27.418us	488	500	97.60
V2	cmds	csrng_cmds	17.350m	108.393ms	50	50	100.00
V2	life cycle	csrng_cmds	17.350m	108.393ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.717m	114.137ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	41.050us	50	50	100.00
V2	alert_test	csrng_alert_test	11.000s	44.122us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	366.932us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	366.932us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	8.000s	21.947us	5	5	100.00
		csrng_csr_rw	13.000s	23.861us	20	20	100.00
		csrng_csr_aliasing	9.000s	106.020us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	41.036us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	8.000s	21.947us	5	5	100.00
		csrng_csr_rw	13.000s	23.861us	20	20	100.00
		csrng_csr_aliasing	9.000s	106.020us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	41.036us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	6.000s	85.380us	5	5	100.00
		csrng_tl_intg_err	44.000s	1.204ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	13.036us	50	50	100.00
		csrng_csr_rw	13.000s	23.861us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	19.000s	51.907us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.717m	114.137ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	19.000s	51.907us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.717m	114.137ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	19.000s	51.907us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	44.000s	1.204ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
		csrng_sec_cm	6.000s	85.380us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	37.853us	200	200	100.00
		csrng_err	13.000s	27.418us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.013h	94.349ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1645	1670	98.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.71	93.20	84.23	95.31	86.43	92.23	98.18	97.33	95.05

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 4.csrng_stress_all_with_rand_reset.32360837045396343132816405316473477143941124495628453384259073863096028444125
    Line 467, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 383450926946 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 383450926946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.csrng_stress_all_with_rand_reset.107870977190739536731922434063750587554892954796297971875852825905883094797991
    Line 435, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 34575582947 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 34575582947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

137.csrng_err.49420828890615834718295963561279828413500015317143852296483826759661086918492
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/137.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1811802 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1811802 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1811802 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1811802 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1811802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

166.csrng_err.103736427094927349237942397623347873066830425408141436079083813786664935785103
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/166.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4833640 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4833640 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4833640 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4833640 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4833640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

109.csrng_err.57270515177715970240784200517483836606680869446126936160187028508561384885093
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/109.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4087855 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4087855 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4087855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

282.csrng_err.33309362261209803239918797774949322106231354872497724698148767085993193267730
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/282.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7824596 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7824596 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7824596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.84143480693548749815252345492834254821877033383375566049567635114138408368424
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1042e4c3-53cf-44cc-aa12-cd171fe15785
```
  - 30.csrng_stress_all_with_rand_reset.67068282466083833113186667651463959173312679910100462662365651279832309321818
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b9887983-07a9-4419-8050-e0e705262a42
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 22.csrng_stress_all_with_rand_reset.85118412666343605829131146519568963082979971840733588614805502602724409888675
    Line 602, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 41936415963 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 41936415963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all_with_rand_reset.38194268977911081695321121305625171328294333231945541118726053215302348911309
    Line 550, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 75567822223 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 75567822223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:158) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 38.csrng_stress_all.10093499095233994316745821853593230456705841527862873478162257032533812179604
    Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  40537672 ps: (csrng_scoreboard.sv:158) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  40537672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 471.csrng_err.58318520823682238944792119731222542137489990690068596396389409906669500913518
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/471.csrng_err/latest/run.log
```
  UVM_ERROR @   2782151 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2782151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```