CSRNG Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	20.665us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	13.000s	24.114us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	110.234us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	1.201ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	80.958us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	11.000s	257.572us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	110.234us	20	20	100.00
		csrng_csr_aliasing	10.000s	80.958us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	28.628us	198	200	99.00
V2	alerts	csrng_alert	8.000s	448.305us	500	500	100.00
V2	err	csrng_err	6.000s	31.378us	490	500	98.00
V2	cmds	csrng_cmds	8.383m	49.101ms	50	50	100.00
V2	life cycle	csrng_cmds	8.383m	49.101ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.300m	30.047ms	50	50	100.00
V2	intr_test	csrng_intr_test	8.000s	14.907us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	91.438us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.119ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.119ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	13.000s	24.114us	5	5	100.00
		csrng_csr_rw	8.000s	110.234us	20	20	100.00
		csrng_csr_aliasing	10.000s	80.958us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	52.764us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	13.000s	24.114us	5	5	100.00
		csrng_csr_rw	8.000s	110.234us	20	20	100.00
		csrng_csr_aliasing	10.000s	80.958us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	52.764us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	25.000s	1.007ms	5	5	100.00
		csrng_tl_intg_err	17.000s	715.917us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	188.576us	50	50	100.00
		csrng_csr_rw	8.000s	110.234us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	448.305us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.300m	30.047ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	448.305us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.300m	30.047ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	448.305us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	715.917us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
		csrng_sec_cm	25.000s	1.007ms	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	28.628us	198	200	99.00
		csrng_err	6.000s	31.378us	490	500	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.363h	236.339ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1608	1670	96.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.59	93.22	84.39	95.44	85.68	91.85	100.00	97.36	92.98

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test csrng_stress_all_with_rand_reset has 36 failures.
  - 3.csrng_stress_all_with_rand_reset.77984797231561413363814493691196262782317503307680974440589328809586661294295
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16317496842 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16317496842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.46585776996360868852672417274764235436997163521715234343192273354039511966464
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2441148383 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2441148383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test csrng_stress_all_with_rand_reset has 14 failures.
  - 0.csrng_stress_all_with_rand_reset.93133372385662978964032742547230080361646091853744768706180970467028533609571
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2172668012 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2172668012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.32204139966799959494805798999021413425971060421387978353577623999964875353124
    Line 286, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2658060995 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2658060995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

60.csrng_err.73157935821130480807782676008377161947590533922319324621629292301372417767215
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/60.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 9676177 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   9676177 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   9676177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

66.csrng_err.34095597454671282311941783318303178566179060627373328418399521042512675225907
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/66.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6056124 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6056124 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6056124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

263.csrng_err.14709383369491525500176461119518309823216310167338990430540477887231459594456
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/263.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 9665401 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 9665401 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 9665401 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   9665401 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   9665401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

403.csrng_err.60132852736857155978122479828323946157591552079339029730910706798398222789940
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/403.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1509805 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1509805 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1509805 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1509805 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1509805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1717): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

7.csrng_intr.98851636451023234125540595746134965360778672410419101776014558688405188386511
Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1717): (time 66575162 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 66575162 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 66575162 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1720): (time 66575162 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1721): (time 66575162 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1718): Assertion CsrngUniZeroizeKey_A has failed has 1 failures:

Test csrng_intr has 1 failures.

100.csrng_intr.92630594883702084287853077601290238488631252805932532997530379849188970737784
Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/100.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 15284052 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 15284052 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15284052 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15284052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---