CSRNG Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	20.378us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	58.967us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	29.193us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	50.000s	4.097ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	142.904us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	342.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	29.193us	20	20	100.00
		csrng_csr_aliasing	5.000s	142.904us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	28.325us	197	200	98.50
V2	alerts	csrng_alert	15.000s	119.546us	500	500	100.00
V2	err	csrng_err	9.000s	34.348us	485	500	97.00
V2	cmds	csrng_cmds	7.883m	48.019ms	50	50	100.00
V2	life cycle	csrng_cmds	7.883m	48.019ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.267m	159.821ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	101.374us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	109.610us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	743.493us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	743.493us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	58.967us	5	5	100.00
		csrng_csr_rw	4.000s	29.193us	20	20	100.00
		csrng_csr_aliasing	5.000s	142.904us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	377.725us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	58.967us	5	5	100.00
		csrng_csr_rw	4.000s	29.193us	20	20	100.00
		csrng_csr_aliasing	5.000s	142.904us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	377.725us	20	20	100.00
V2		TOTAL			1419	1440	98.54
V2S	tl_intg_err	csrng_sec_cm	7.000s	142.757us	5	5	100.00
		csrng_tl_intg_err	23.000s	439.598us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	33.486us	50	50	100.00
		csrng_csr_rw	4.000s	29.193us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	119.546us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.267m	159.821ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	119.546us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.267m	159.821ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	119.546us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	439.598us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
		csrng_sec_cm	7.000s	142.757us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	28.325us	197	200	98.50
		csrng_err	9.000s	34.348us	485	500	97.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.179h	662.144ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1599	1670	95.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.59	93.22	84.39	95.44	85.64	91.92	98.18	97.52	93.20

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test csrng_stress_all_with_rand_reset has 31 failures.
  - 0.csrng_stress_all_with_rand_reset.63655828542675019825492712863444779840917739773368832483188596639176737182306
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1785155925 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1785155925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.110371566470135397295052769854338875280481427477962625789463448365285595480521
    Line 389, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40137706890 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40137706890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test csrng_stress_all_with_rand_reset has 19 failures.
  - 1.csrng_stress_all_with_rand_reset.21164539276927051797994188815792909436113897869589661437835958264991338054455
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 162674724 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 162674724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.42724093667888992422742452515903432800534283452947748137584192573703257326437
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36177578368 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36177578368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

89.csrng_err.81904839816192243026672367007662893509216140233201524595680681750633953822499
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8228166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8228166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8228166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8228166 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8228166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

100.csrng_err.58026846391117013950267949712916773600146609785514723725372385864178310959534
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/100.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2359021 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2359021 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2359021 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2359021 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2359021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

26.csrng_err.87064054265574789907874711038024733702298990671773420435649697614030242647460
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3402447 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3402447 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3402447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

106.csrng_err.41298242604068833520779779950515766878239757710933304285863061698221278930657
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/106.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1901343 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1901343 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1901343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1718): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

23.csrng_intr.57810471448602157269464297920077246639741133383578167765142335939425724413314
Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 21086231 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 21086231 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21086231 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21086231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

111.csrng_intr.12088443284592032516714082913343937405509561714422370296272436899192612169089
Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/111.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 44837107 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 44837107 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  44837107 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  44837107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 20.csrng_stress_all.18052454698023342225420741224710093088593348274528630028222927349284157779098
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 14695579501 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 14695579501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.csrng_stress_all.22118621829184070222768390860113956403092164306808805695471539721072115256410
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1573299263 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1573299263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 17.csrng_stress_all.71294783274520276135916343401684504787961097857095443579561151294362926592051
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  32414024 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  32414024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```