CSRNG Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	15.452us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	55.512us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	55.363us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	687.030us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	164.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	29.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	55.363us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.250us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	40.284us	200	200	100.00
V2	alerts	csrng_alert	15.000s	125.910us	500	500	100.00
V2	err	csrng_err	14.000s	20.982us	484	500	96.80
V2	cmds	csrng_cmds	6.400m	28.448ms	37	50	74.00
V2	life cycle	csrng_cmds	6.400m	28.448ms	37	50	74.00
V2	stress_all	csrng_stress_all	25.867m	97.743ms	47	50	94.00
V2	intr_test	csrng_intr_test	8.000s	120.532us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	40.087us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	446.224us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	446.224us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	55.512us	5	5	100.00
		csrng_csr_rw	8.000s	55.363us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.250us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	275.547us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	55.512us	5	5	100.00
		csrng_csr_rw	8.000s	55.363us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.250us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	275.547us	20	20	100.00
V2		TOTAL			1408	1440	97.78
V2S	tl_intg_err	csrng_sec_cm	9.000s	135.569us	5	5	100.00
		csrng_tl_intg_err	15.000s	647.290us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	40.299us	50	50	100.00
		csrng_csr_rw	8.000s	55.363us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	125.910us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.867m	97.743ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	125.910us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.867m	97.743ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	125.910us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	647.290us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
		csrng_sec_cm	9.000s	135.569us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	40.284us	200	200	100.00
		csrng_err	14.000s	20.982us	484	500	96.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.565h	198.575ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1588	1670	95.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.62	93.14	84.13	95.36	85.99	91.67	100.00	97.50	94.85

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test csrng_stress_all_with_rand_reset has 34 failures.
  - 0.csrng_stress_all_with_rand_reset.11787364945518705644596225610529757527215247022899047838608620492008496995209
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6080479155 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6080479155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.9784644605317917119082665400873653478982998293630013421708187700869866281497
    Line 349, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102856367438 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102856367438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 20 failures:

Test csrng_cmds has 13 failures.

6.csrng_cmds.63863334839363372843571586391758646337334315267395483439278851881793947262084
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  6.csrng_cmds.1825660036
  
  coverage files:
    model(design data) :  /workspace/coverage/default/6.csrng_cmds.1825660036/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/6.csrng_cmds.1825660036/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 16, 2024 at 12:42:54 PDT  (total: 00:01:50)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

10.csrng_cmds.64672847764814526970824657769869101288076286410780872255000912379532080650569
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  10.csrng_cmds.1063328073
  
  coverage files:
    model(design data) :  /workspace/coverage/default/10.csrng_cmds.1063328073/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/10.csrng_cmds.1063328073/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 16, 2024 at 12:42:00 PDT  (total: 00:00:40)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 11 more failures.

Test csrng_err has 7 failures.

77.csrng_err.57700128206092841894922724616527744285130788109345630491065407008978082182415
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/77.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  77.csrng_err.4064261391
  
  coverage files:
    model(design data) :  /workspace/coverage/default/77.csrng_err.4064261391/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/77.csrng_err.4064261391/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 16, 2024 at 12:41:57 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

96.csrng_err.66443214072198628835343097132921229407144054830040408174839002971245448528859
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/96.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  96.csrng_err.1056703451
  
  coverage files:
    model(design data) :  /workspace/coverage/default/96.csrng_err.1056703451/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/96.csrng_err.1056703451/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 16, 2024 at 12:42:19 PDT  (total: 00:00:08)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test csrng_stress_all_with_rand_reset has 16 failures.
  - 1.csrng_stress_all_with_rand_reset.47033225069235230345229852496935356955563069494957369758510860366358715667908
    Line 412, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14707466755 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14707466755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.55188874359542129762072637950979716427043652652582813563782912377661742046868
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 662894051 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 662894051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

197.csrng_err.34397498309751165641470937544873323618962657335507487900941403038055767582726
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/197.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4514696 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4514696 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4514696 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4514696 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4514696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

215.csrng_err.46260035077113916862143287643393413061750333523119939092184809611333018694882
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/215.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7851017 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7851017 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7851017 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   7851017 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   7851017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 16.csrng_stress_all.72324329201398163458631941430487880499376079889846811004269527957019901037641
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1906633468 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1906633468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.csrng_stress_all.48572429599954311338103443374882815294405560869011529494326785349374248998302
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8263047618 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8263047618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

160.csrng_err.1888264348049087130768218854620014953143497774748335419564666864712709724561
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/160.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 4574779 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4574779 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4574779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

474.csrng_err.28950204606757980635595336578103709082787264157306106324622410390324108292815
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/474.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3983131 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3983131 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3983131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 24.csrng_stress_all.22162774865513913171340184526224191351760781694861726473886546550990746134861
    Line 330, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 306986166 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 306986166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): (time * NS) Assertion ValidKnown_A has failed has 1 failures:

Test csrng_err has 1 failures.

273.csrng_err.78206600730812198441393771336095357271710233177646773993317424124972007460908
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/273.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2672 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2672 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2672 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2672000 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2672000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]