CSRNG Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 13.000s 15.452us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 6.000s 55.512us 5 5 100.00
V1 csr_rw csrng_csr_rw 8.000s 55.363us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 24.000s 687.030us 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 6.000s 164.250us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 10.000s 29.957us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 8.000s 55.363us 20 20 100.00
csrng_csr_aliasing 6.000s 164.250us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 14.000s 40.284us 200 200 100.00
V2 alerts csrng_alert 15.000s 125.910us 500 500 100.00
V2 err csrng_err 14.000s 20.982us 484 500 96.80
V2 cmds csrng_cmds 6.400m 28.448ms 37 50 74.00
V2 life cycle csrng_cmds 6.400m 28.448ms 37 50 74.00
V2 stress_all csrng_stress_all 25.867m 97.743ms 47 50 94.00
V2 intr_test csrng_intr_test 8.000s 120.532us 50 50 100.00
V2 alert_test csrng_alert_test 9.000s 40.087us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 16.000s 446.224us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 16.000s 446.224us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 6.000s 55.512us 5 5 100.00
csrng_csr_rw 8.000s 55.363us 20 20 100.00
csrng_csr_aliasing 6.000s 164.250us 5 5 100.00
csrng_same_csr_outstanding 10.000s 275.547us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 6.000s 55.512us 5 5 100.00
csrng_csr_rw 8.000s 55.363us 20 20 100.00
csrng_csr_aliasing 6.000s 164.250us 5 5 100.00
csrng_same_csr_outstanding 10.000s 275.547us 20 20 100.00
V2 TOTAL 1408 1440 97.78
V2S tl_intg_err csrng_sec_cm 9.000s 135.569us 5 5 100.00
csrng_tl_intg_err 15.000s 647.290us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 9.000s 40.299us 50 50 100.00
csrng_csr_rw 8.000s 55.363us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 15.000s 125.910us 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 25.867m 97.743ms 47 50 94.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 15.000s 125.910us 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
V2S sec_cm_constants_lc_gated csrng_stress_all 25.867m 97.743ms 47 50 94.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 15.000s 125.910us 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 15.000s 647.290us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
csrng_sec_cm 9.000s 135.569us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 14.000s 40.284us 200 200 100.00
csrng_err 14.000s 20.982us 484 500 96.80
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 1.565h 198.575ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 1588 1670 95.09

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 6 66.67
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.62 93.14 84.13 95.36 85.99 91.67 100.00 97.50 94.85

Failure Buckets

Past Results