CSRNG Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	25.375us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.169us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	23.434us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	1.309ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	291.885us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	200.299us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	23.434us	20	20	100.00
		csrng_csr_aliasing	6.000s	291.885us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	11.000s	27.220us	200	200	100.00
V2	alerts	csrng_alert	14.000s	191.529us	500	500	100.00
V2	err	csrng_err	19.000s	20.516us	479	500	95.80
V2	cmds	csrng_cmds	12.617m	58.392ms	40	50	80.00
V2	life cycle	csrng_cmds	12.617m	58.392ms	40	50	80.00
V2	stress_all	csrng_stress_all	25.550m	98.891ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	218.115us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	21.199us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	497.807us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	497.807us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.169us	5	5	100.00
		csrng_csr_rw	4.000s	23.434us	20	20	100.00
		csrng_csr_aliasing	6.000s	291.885us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	164.747us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.169us	5	5	100.00
		csrng_csr_rw	4.000s	23.434us	20	20	100.00
		csrng_csr_aliasing	6.000s	291.885us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	164.747us	20	20	100.00
V2		TOTAL			1407	1440	97.71
V2S	tl_intg_err	csrng_sec_cm	9.000s	37.730us	5	5	100.00
		csrng_tl_intg_err	13.000s	1.223ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	14.218us	50	50	100.00
		csrng_csr_rw	4.000s	23.434us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	14.000s	191.529us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.550m	98.891ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	14.000s	191.529us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.550m	98.891ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	14.000s	191.529us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	1.223ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
		csrng_sec_cm	9.000s	37.730us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	11.000s	27.220us	200	200	100.00
		csrng_err	19.000s	20.516us	479	500	95.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	55.783m	36.434ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1587	1670	95.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.62	93.14	84.13	95.38	86.03	91.54	100.00	97.17	94.96

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
- Test csrng_stress_all_with_rand_reset has 38 failures.
  - 0.csrng_stress_all_with_rand_reset.97262815588964562847723363850234931894212757262252188006885666577645333100206
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29356411305 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29356411305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.7832646798673211434081194463960603130105109419715019212816885707321690442551
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33756430637 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33756430637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 15 failures:

Test csrng_cmds has 10 failures.

0.csrng_cmds.39264625138936168828679859425082941067575678028906007857778557821424608549923
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  0.csrng_cmds.3362593827
  
  coverage files:
    model(design data) :  /workspace/coverage/default/0.csrng_cmds.3362593827/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/0.csrng_cmds.3362593827/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 18, 2024 at 13:22:28 PDT  (total: 00:03:38)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

6.csrng_cmds.64228457772468795540407545634999853934264315190430581860011285951492554724323
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  6.csrng_cmds.3095630819
  
  coverage files:
    model(design data) :  /workspace/coverage/default/6.csrng_cmds.3095630819/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/6.csrng_cmds.3095630819/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 18, 2024 at 13:19:19 PDT  (total: 00:00:29)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 8 more failures.

Test csrng_err has 5 failures.

65.csrng_err.87912007862878475241827174393839236061221810889135628966097615205635120358164
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/65.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  65.csrng_err.164553492
  
  coverage files:
    model(design data) :  /workspace/coverage/default/65.csrng_err.164553492/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/65.csrng_err.164553492/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 18, 2024 at 13:20:19 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

83.csrng_err.100422153095289113896818041134338176651494899806883020479582346901364654196750
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/83.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  83.csrng_err.1795672078
  
  coverage files:
    model(design data) :  /workspace/coverage/default/83.csrng_err.1795672078/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/83.csrng_err.1795672078/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 18, 2024 at 13:20:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
- Test csrng_stress_all_with_rand_reset has 12 failures.
  - 1.csrng_stress_all_with_rand_reset.81301709042456961238021662231590806696196238574884057459275176140596293782408
    Line 593, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36433551143 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36433551143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.11854846318883205119954793340577626584494753995192101422389983791576291927585
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35047436963 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35047436963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

71.csrng_err.106061601034527509848124561893258450955506857021233313341830304648981968842495
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/71.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 12855718 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 12855718 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 12855718 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  12855718 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  12855718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

93.csrng_err.78229942193620305637000252855550291650959929650673557237525844879041273576679
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/93.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 28836595 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 28836595 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 28836595 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  28836595 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  28836595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

66.csrng_err.17143993747779678817269182857736276267269830639908603156259245895231521783900
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/66.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 10306553 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  10306553 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10306553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

183.csrng_err.68910527109437849565160562195995546671359244883651072624251890338564031181409
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/183.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6627209 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6627209 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6627209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 32.csrng_stress_all.73936837870121249678982310599593025899314922578823370083098984420647901133103
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 17952981050 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 17952981050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 34.csrng_stress_all.91603645951348195391715074781742606786262996267210608756152611615664215314130
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8109369025 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8109369025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 317.csrng_err.91644118926862024891375674132128986088459239487494992930895915444260092873834
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/317.csrng_err/latest/run.log
```
  UVM_ERROR @   2874432 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2874432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```