EDN Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	13.088us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	20.542us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	16.184us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.150s	535.004us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.190s	33.705us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.780s	27.092us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	16.184us	20	20	100.00
		edn_csr_aliasing	1.190s	33.705us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.650s	77.703us	50	50	100.00
V2	csrng_commands	edn_genbits	1.650s	77.703us	50	50	100.00
V2	genbits	edn_genbits	1.650s	77.703us	50	50	100.00
V2	interrupts	edn_intr	1.180s	28.647us	50	50	100.00
V2	alerts	edn_alert	1.060s	36.986us	50	50	100.00
V2	errs	edn_err	1.160s	20.906us	50	50	100.00
V2	disable	edn_disable	0.910s	13.783us	43	50	86.00
		edn_disable_auto_req_mode	1.080s	24.054us	50	50	100.00
V2	stress_all	edn_stress_all	4.370s	1.283ms	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	198.533us	50	50	100.00
V2	alert_test	edn_alert_test	1.150s	34.368us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.400s	467.205us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.400s	467.205us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	20.542us	5	5	100.00
		edn_csr_rw	0.940s	16.184us	20	20	100.00
		edn_csr_aliasing	1.190s	33.705us	5	5	100.00
		edn_same_csr_outstanding	1.530s	77.939us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	20.542us	5	5	100.00
		edn_csr_rw	0.940s	16.184us	20	20	100.00
		edn_csr_aliasing	1.190s	33.705us	5	5	100.00
		edn_same_csr_outstanding	1.530s	77.939us	20	20	100.00
V2		TOTAL			483	490	98.57
V2S	tl_intg_err	edn_sec_cm	5.770s	1.498ms	5	5	100.00
		edn_tl_intg_err	2.500s	98.295us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.920s	15.363us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	36.986us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.770s	1.498ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.770s	1.498ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.770s	1.498ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	36.986us	50	50	100.00
		edn_sec_cm	5.770s	1.498ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	36.986us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.500s	98.295us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	55.697m	525.491ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			673	680	98.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.29	99.03	94.16	96.79	73.03	98.62	99.77	98.61

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:

Test edn_disable has 7 failures.

7.edn_disable.3478936556
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.edn_disable.862142366
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.