EDN Simulation Results

Sunday October 08 2023 19:02:39 UTC

GitHub Revision: 4e80560e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3527490040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.010s	16.679us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.900s	13.942us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.950s	16.836us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.700s	200.272us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.430s	126.428us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	113.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.950s	16.836us	20	20	100.00
		edn_csr_aliasing	1.430s	126.428us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.490s	75.370us	50	50	100.00
V2	csrng_commands	edn_genbits	1.490s	75.370us	50	50	100.00
V2	genbits	edn_genbits	1.490s	75.370us	50	50	100.00
V2	interrupts	edn_intr	1.140s	20.779us	50	50	100.00
V2	alerts	edn_alert	1.080s	19.640us	50	50	100.00
V2	errs	edn_err	1.550s	56.625us	100	100	100.00
V2	disable	edn_disable	0.940s	13.920us	50	50	100.00
		edn_disable_auto_req_mode	1.160s	26.631us	50	50	100.00
V2	stress_all	edn_stress_all	4.310s	593.461us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	17.557us	50	50	100.00
V2	alert_test	edn_alert_test	1.000s	19.404us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.420s	1.307ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.420s	1.307ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.900s	13.942us	5	5	100.00
		edn_csr_rw	0.950s	16.836us	20	20	100.00
		edn_csr_aliasing	1.430s	126.428us	5	5	100.00
		edn_same_csr_outstanding	1.620s	425.717us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.900s	13.942us	5	5	100.00
		edn_csr_rw	0.950s	16.836us	20	20	100.00
		edn_csr_aliasing	1.430s	126.428us	5	5	100.00
		edn_same_csr_outstanding	1.620s	425.717us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	edn_sec_cm	6.440s	1.428ms	5	5	100.00
		edn_tl_intg_err	2.710s	127.984us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.890s	23.502us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.080s	19.640us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.440s	1.428ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.440s	1.428ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.440s	1.428ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.080s	19.640us	50	50	100.00
		edn_sec_cm	6.440s	1.428ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.080s	19.640us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.710s	127.984us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	34.923m	167.284ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			729	730	99.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.06	99.02	92.39	96.79	95.39	98.62	99.77	97.45

Failure Buckets

• Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 13.edn_stress_all_with_rand_reset.2171733843
      Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a142bd05-cab8-43de-8907-7b6a33bb1076
      

Past Results

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• 2023.09.25_01.51.45
• 2023.09.18_00.01.24
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