EDN Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	15.149us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.920s	55.046us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	18.282us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.120s	506.980us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	254.119us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.340s	128.744us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	18.282us	20	20	100.00
		edn_csr_aliasing	1.420s	254.119us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	10.130s	1.215ms	300	300	100.00
V2	csrng_commands	edn_genbits	10.130s	1.215ms	300	300	100.00
V2	genbits	edn_genbits	10.130s	1.215ms	300	300	100.00
V2	interrupts	edn_intr	1.160s	19.312us	50	50	100.00
V2	alerts	edn_alert	1.070s	22.784us	50	50	100.00
V2	errs	edn_err	1.620s	54.509us	100	100	100.00
V2	disable	edn_disable	0.960s	13.935us	48	50	96.00
		edn_disable_auto_req_mode	1.170s	285.774us	50	50	100.00
V2	stress_all	edn_stress_all	4.500s	206.994us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	13.984us	50	50	100.00
V2	alert_test	edn_alert_test	1.490s	59.214us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.790s	2.012ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.790s	2.012ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.920s	55.046us	5	5	100.00
		edn_csr_rw	0.960s	18.282us	20	20	100.00
		edn_csr_aliasing	1.420s	254.119us	5	5	100.00
		edn_same_csr_outstanding	1.320s	68.738us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.920s	55.046us	5	5	100.00
		edn_csr_rw	0.960s	18.282us	20	20	100.00
		edn_csr_aliasing	1.420s	254.119us	5	5	100.00
		edn_same_csr_outstanding	1.320s	68.738us	20	20	100.00
V2		TOTAL			788	790	99.75
V2S	tl_intg_err	edn_sec_cm	6.870s	436.421us	5	5	100.00
		edn_tl_intg_err	2.530s	414.971us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.920s	16.895us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.070s	22.784us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.870s	436.421us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.870s	436.421us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.870s	436.421us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.070s	22.784us	50	50	100.00
		edn_sec_cm	6.870s	436.421us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.070s	22.784us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.530s	414.971us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	57.149m	566.759ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			977	980	99.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.13	99.02	92.26	96.79	94.08	98.62	99.77	99.40

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_disable has 2 failures.

    • 17.edn_disable.94991731869484293626803837122640264639829400857447553734783488820159038605937
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/17.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.edn_disable.85722481345854511867837973007401546355897970976410005433576109528191681321950
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/23.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 6.edn_stress_all_with_rand_reset.113021238507793728239558788398372606173451727661773563765610679191700086865889
      Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8df565a8-31c0-454c-9f79-a36b5a61d0a2
      

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