EDN Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.130s	17.669us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	21.021us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.970s	16.640us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.940s	996.729us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.500s	33.944us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.800s	27.092us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.970s	16.640us	20	20	100.00
		edn_csr_aliasing	1.500s	33.944us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	8.430s	1.149ms	300	300	100.00
V2	csrng_commands	edn_genbits	8.430s	1.149ms	300	300	100.00
V2	genbits	edn_genbits	8.430s	1.149ms	300	300	100.00
V2	interrupts	edn_intr	1.270s	23.108us	50	50	100.00
V2	alerts	edn_alert	1.470s	28.475us	200	200	100.00
V2	errs	edn_err	1.370s	39.456us	100	100	100.00
V2	disable	edn_disable	0.990s	15.882us	50	50	100.00
		edn_disable_auto_req_mode	1.570s	50.195us	50	50	100.00
V2	stress_all	edn_stress_all	8.010s	415.508us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	15.910us	50	50	100.00
V2	alert_test	edn_alert_test	1.070s	18.500us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.660s	346.993us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.660s	346.993us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	21.021us	5	5	100.00
		edn_csr_rw	0.970s	16.640us	20	20	100.00
		edn_csr_aliasing	1.500s	33.944us	5	5	100.00
		edn_same_csr_outstanding	1.410s	42.849us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	21.021us	5	5	100.00
		edn_csr_rw	0.970s	16.640us	20	20	100.00
		edn_csr_aliasing	1.500s	33.944us	5	5	100.00
		edn_same_csr_outstanding	1.410s	42.849us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	3.300s	358.454us	0	5	0.00
		edn_tl_intg_err	4.800s	258.660us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.140s	27.908us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.470s	28.475us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.300s	358.454us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.300s	358.454us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.300s	358.454us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.300s	358.454us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.470s	28.475us	200	200	100.00
		edn_sec_cm	3.300s	358.454us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.470s	28.475us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.800s	258.660us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.876m	592.026ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.32	98.25	93.31	90.85	86.63	95.50	96.83	91.89

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.77378456308156246759750795759283893613706618603722864095001539610178320841121
Line 446, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @ 358454485 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @ 358454485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.32700653114806162541519708618093888330184527531177545363577848270975381266446
Line 398, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @  78877676 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  78877676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.