ENTROPY_SRC Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 100.495us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 40.872us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 23.250us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 18.000s 289.095us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 13.000s 2.691ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 13.000s 31.352us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 23.250us 20 20 100.00
entropy_src_csr_aliasing 13.000s 2.691ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 100.495us 50 50 100.00
entropy_src_rng 4.767m 10.057ms 298 300 99.33
entropy_src_fw_ov 2.517m 5.041ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 2.517m 5.041ms 299 300 99.67
V2 rng_mode entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 4.683m 10.063ms 398 400 99.50
V2 health_checks entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2 conditioning entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2 interrupts entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2 alerts entropy_src_rng 4.767m 10.057ms 298 300 99.33
entropy_src_functional_alerts 9.000s 114.501us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.000s 583.498us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 14.000s 52.410us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 13.000s 36.344us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 17.800us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 13.000s 36.639us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 13.000s 36.639us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 40.872us 5 5 100.00
entropy_src_csr_rw 8.000s 23.250us 20 20 100.00
entropy_src_csr_aliasing 13.000s 2.691ms 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 124.537us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 40.872us 5 5 100.00
entropy_src_csr_rw 8.000s 23.250us 20 20 100.00
entropy_src_csr_aliasing 13.000s 2.691ms 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 124.537us 20 20 100.00
V2 TOTAL 2235 2240 99.78
V2S tl_intg_err entropy_src_sec_cm 8.000s 93.561us 5 5 100.00
entropy_src_tl_intg_err 16.000s 515.489us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.767m 10.057ms 298 300 99.33
entropy_src_cfg_regwen 13.000s 117.472us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.767m 10.057ms 298 300 99.33
entropy_src_fw_ov 2.517m 5.041ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 14.000s 52.410us 1000 1000 100.00
entropy_src_sec_cm 8.000s 93.561us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 14.000s 52.410us 1000 1000 100.00
entropy_src_sec_cm 8.000s 93.561us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.767m 10.057ms 298 300 99.33
V2S sec_cm_ctr_redun entropy_src_functional_errors 14.000s 52.410us 1000 1000 100.00
entropy_src_sec_cm 8.000s 93.561us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 14.000s 52.410us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 114.501us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 16.000s 515.489us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.567m 10.040ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 5.974ms 47 50 94.00
TOTAL 2512 2520 99.68

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 7 70.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
85.82 98.61 96.55 98.64 95.88 89.23 97.00 91.70 53.78

Failure Buckets

Past Results