ENTROPY_SRC Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 7.000s 44.360us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 33.445us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 17.443us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 264.798us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 74.933us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 38.420us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 17.443us 20 20 100.00
entropy_src_csr_aliasing 7.000s 74.933us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 7.000s 44.360us 50 50 100.00
entropy_src_rng 5.150m 10.016ms 298 300 99.33
entropy_src_fw_ov 2.500m 5.026ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.500m 5.026ms 289 300 96.33
V2 rng_mode entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 9.300m 10.024ms 378 400 94.50
V2 health_checks entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2 conditioning entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2 interrupts entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2 alerts entropy_src_rng 5.150m 10.016ms 298 300 99.33
entropy_src_functional_alerts 7.000s 341.594us 50 50 100.00
V2 stress_all entropy_src_stress_all 14.000s 411.020us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 26.000s 339.167us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 27.995us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 67.205us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 445.494us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 445.494us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 33.445us 5 5 100.00
entropy_src_csr_rw 4.000s 17.443us 20 20 100.00
entropy_src_csr_aliasing 7.000s 74.933us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 98.284us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 33.445us 5 5 100.00
entropy_src_csr_rw 4.000s 17.443us 20 20 100.00
entropy_src_csr_aliasing 7.000s 74.933us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 98.284us 20 20 100.00
V2 TOTAL 2226 2290 97.21
V2S tl_intg_err entropy_src_sec_cm 5.000s 250.202us 5 5 100.00
entropy_src_tl_intg_err 7.000s 749.965us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.150m 10.016ms 298 300 99.33
entropy_src_cfg_regwen 6.000s 17.261us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.150m 10.016ms 298 300 99.33
entropy_src_fw_ov 2.500m 5.026ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
entropy_src_sec_cm 5.000s 250.202us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
entropy_src_sec_cm 5.000s 250.202us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.150m 10.016ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
entropy_src_sec_cm 5.000s 250.202us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
entropy_src_sec_cm 5.000s 250.202us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.533m 10.013ms 971 1000 97.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 341.594us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 749.965us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.733m 10.073ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 33.000s 5.405ms 46 50 92.00
TOTAL 2502 2570 97.35

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.61 98.19 95.42 98.36 95.88 88.12 97.92 90.46 58.60

Failure Buckets

Past Results