ENTROPY_SRC Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 30.230us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 26.457us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 6.000s 154.217us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 19.000s 6.384ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 10.000s 81.215us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 29.568us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 6.000s 154.217us 20 20 100.00
entropy_src_csr_aliasing 10.000s 81.215us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 30.230us 50 50 100.00
entropy_src_rng 4.867m 10.096ms 300 300 100.00
entropy_src_fw_ov 2.467m 5.087ms 296 300 98.67
V2 firmware_mode entropy_src_fw_ov 2.467m 5.087ms 296 300 98.67
V2 rng_mode entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.050m 10.013ms 389 400 97.25
V2 health_checks entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2 conditioning entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2 interrupts entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2 alerts entropy_src_rng 4.867m 10.096ms 300 300 100.00
entropy_src_functional_alerts 5.000s 751.376us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 2.116ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 709.685us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 205.207us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 57.357us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 444.809us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 444.809us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 26.457us 5 5 100.00
entropy_src_csr_rw 6.000s 154.217us 20 20 100.00
entropy_src_csr_aliasing 10.000s 81.215us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 156.959us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 26.457us 5 5 100.00
entropy_src_csr_rw 6.000s 154.217us 20 20 100.00
entropy_src_csr_aliasing 10.000s 81.215us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 156.959us 20 20 100.00
V2 TOTAL 2246 2290 98.08
V2S tl_intg_err entropy_src_sec_cm 4.000s 550.467us 5 5 100.00
entropy_src_tl_intg_err 10.000s 365.132us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.867m 10.096ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 37.920us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.867m 10.096ms 300 300 100.00
entropy_src_fw_ov 2.467m 5.087ms 296 300 98.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 550.467us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 550.467us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.867m 10.096ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 550.467us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 550.467us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.833m 10.012ms 971 1000 97.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 751.376us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 365.132us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.967m 10.048ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 20.000s 1.817ms 42 50 84.00
TOTAL 2518 2570 97.98

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.45 98.17 95.37 98.33 95.84 88.15 96.88 90.46 58.02

Failure Buckets

Past Results